Rafael Espindola | 6d387ae | 2011-11-28 20:05:27 +0000 | [diff] [blame] | 1 | /*===---- cpuid.h - X86 cpu model detection --------------------------------=== |
Rafael Espindola | b816276 | 2011-11-26 20:53:19 +0000 | [diff] [blame] | 2 | * |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 4 | * of this software and associated documentation files (the "Software"), to deal |
| 5 | * in the Software without restriction, including without limitation the rights |
| 6 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 7 | * copies of the Software, and to permit persons to whom the Software is |
| 8 | * furnished to do so, subject to the following conditions: |
| 9 | * |
| 10 | * The above copyright notice and this permission notice shall be included in |
| 11 | * all copies or substantial portions of the Software. |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 16 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 17 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 18 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 19 | * THE SOFTWARE. |
| 20 | * |
| 21 | *===-----------------------------------------------------------------------=== |
| 22 | */ |
| 23 | |
Rafael Espindola | 1376ba9 | 2011-11-27 15:21:33 +0000 | [diff] [blame] | 24 | #if !(__x86_64__ || __i386__) |
| 25 | #error this header is for x86 only |
| 26 | #endif |
| 27 | |
Stephen Hines | 176edba | 2014-12-01 14:53:08 -0800 | [diff] [blame] | 28 | /* Responses identification request with %eax 0 */ |
| 29 | /* AMD: "AuthenticAMD" */ |
| 30 | #define signature_AMD_ebx 0x68747541 |
| 31 | #define signature_AMD_edx 0x69746e65 |
| 32 | #define signature_AMD_ecx 0x444d4163 |
| 33 | /* CENTAUR: "CentaurHauls" */ |
| 34 | #define signature_CENTAUR_ebx 0x746e6543 |
| 35 | #define signature_CENTAUR_edx 0x48727561 |
| 36 | #define signature_CENTAUR_ecx 0x736c7561 |
| 37 | /* CYRIX: "CyrixInstead" */ |
| 38 | #define signature_CYRIX_ebx 0x69727943 |
| 39 | #define signature_CYRIX_edx 0x736e4978 |
| 40 | #define signature_CYRIX_ecx 0x64616574 |
| 41 | /* INTEL: "GenuineIntel" */ |
| 42 | #define signature_INTEL_ebx 0x756e6547 |
| 43 | #define signature_INTEL_edx 0x49656e69 |
| 44 | #define signature_INTEL_ecx 0x6c65746e |
| 45 | /* TM1: "TransmetaCPU" */ |
| 46 | #define signature_TM1_ebx 0x6e617254 |
| 47 | #define signature_TM1_edx 0x74656d73 |
| 48 | #define signature_TM1_ecx 0x55504361 |
| 49 | /* TM2: "GenuineTMx86" */ |
| 50 | #define signature_TM2_ebx 0x756e6547 |
| 51 | #define signature_TM2_edx 0x54656e69 |
| 52 | #define signature_TM2_ecx 0x3638784d |
| 53 | /* NSC: "Geode by NSC" */ |
| 54 | #define signature_NSC_ebx 0x646f6547 |
| 55 | #define signature_NSC_edx 0x43534e20 |
| 56 | #define signature_NSC_ecx 0x79622065 |
| 57 | /* NEXGEN: "NexGenDriven" */ |
| 58 | #define signature_NEXGEN_ebx 0x4778654e |
| 59 | #define signature_NEXGEN_edx 0x72446e65 |
| 60 | #define signature_NEXGEN_ecx 0x6e657669 |
| 61 | /* RISE: "RiseRiseRise" */ |
| 62 | #define signature_RISE_ebx 0x65736952 |
| 63 | #define signature_RISE_edx 0x65736952 |
| 64 | #define signature_RISE_ecx 0x65736952 |
| 65 | /* SIS: "SiS SiS SiS " */ |
| 66 | #define signature_SIS_ebx 0x20536953 |
| 67 | #define signature_SIS_edx 0x20536953 |
| 68 | #define signature_SIS_ecx 0x20536953 |
| 69 | /* UMC: "UMC UMC UMC " */ |
| 70 | #define signature_UMC_ebx 0x20434d55 |
| 71 | #define signature_UMC_edx 0x20434d55 |
| 72 | #define signature_UMC_ecx 0x20434d55 |
| 73 | /* VIA: "VIA VIA VIA " */ |
| 74 | #define signature_VIA_ebx 0x20414956 |
| 75 | #define signature_VIA_edx 0x20414956 |
| 76 | #define signature_VIA_ecx 0x20414956 |
| 77 | /* VORTEX: "Vortex86 SoC" */ |
| 78 | #define signature_VORTEX_ebx 0x74726f56 |
| 79 | #define signature_VORTEX_edx 0x36387865 |
| 80 | #define signature_VORTEX_ecx 0x436f5320 |
| 81 | |
Roman Divacky | 7abbb85 | 2013-07-19 17:28:36 +0000 | [diff] [blame] | 82 | /* Features in %ecx for level 1 */ |
| 83 | #define bit_SSE3 0x00000001 |
| 84 | #define bit_PCLMULQDQ 0x00000002 |
| 85 | #define bit_DTES64 0x00000004 |
| 86 | #define bit_MONITOR 0x00000008 |
| 87 | #define bit_DSCPL 0x00000010 |
| 88 | #define bit_VMX 0x00000020 |
| 89 | #define bit_SMX 0x00000040 |
| 90 | #define bit_EIST 0x00000080 |
| 91 | #define bit_TM2 0x00000100 |
| 92 | #define bit_SSSE3 0x00000200 |
| 93 | #define bit_CNXTID 0x00000400 |
| 94 | #define bit_FMA 0x00001000 |
| 95 | #define bit_CMPXCHG16B 0x00002000 |
| 96 | #define bit_xTPR 0x00004000 |
| 97 | #define bit_PDCM 0x00008000 |
| 98 | #define bit_PCID 0x00020000 |
| 99 | #define bit_DCA 0x00040000 |
| 100 | #define bit_SSE41 0x00080000 |
| 101 | #define bit_SSE42 0x00100000 |
| 102 | #define bit_x2APIC 0x00200000 |
| 103 | #define bit_MOVBE 0x00400000 |
| 104 | #define bit_POPCNT 0x00800000 |
| 105 | #define bit_TSCDeadline 0x01000000 |
| 106 | #define bit_AESNI 0x02000000 |
| 107 | #define bit_XSAVE 0x04000000 |
| 108 | #define bit_OSXSAVE 0x08000000 |
| 109 | #define bit_AVX 0x10000000 |
Stephen Hines | 176edba | 2014-12-01 14:53:08 -0800 | [diff] [blame] | 110 | #define bit_RDRND 0x40000000 |
Roman Divacky | 7abbb85 | 2013-07-19 17:28:36 +0000 | [diff] [blame] | 111 | |
| 112 | /* Features in %edx for level 1 */ |
| 113 | #define bit_FPU 0x00000001 |
| 114 | #define bit_VME 0x00000002 |
| 115 | #define bit_DE 0x00000004 |
| 116 | #define bit_PSE 0x00000008 |
| 117 | #define bit_TSC 0x00000010 |
| 118 | #define bit_MSR 0x00000020 |
| 119 | #define bit_PAE 0x00000040 |
| 120 | #define bit_MCE 0x00000080 |
| 121 | #define bit_CX8 0x00000100 |
| 122 | #define bit_APIC 0x00000200 |
| 123 | #define bit_SEP 0x00000800 |
| 124 | #define bit_MTRR 0x00001000 |
| 125 | #define bit_PGE 0x00002000 |
| 126 | #define bit_MCA 0x00004000 |
| 127 | #define bit_CMOV 0x00008000 |
| 128 | #define bit_PAT 0x00010000 |
| 129 | #define bit_PSE36 0x00020000 |
| 130 | #define bit_PSN 0x00040000 |
| 131 | #define bit_CLFSH 0x00080000 |
| 132 | #define bit_DS 0x00200000 |
| 133 | #define bit_ACPI 0x00400000 |
| 134 | #define bit_MMX 0x00800000 |
| 135 | #define bit_FXSR 0x01000000 |
Stephen Hines | 651f13c | 2014-04-23 16:59:28 -0700 | [diff] [blame] | 136 | #define bit_FXSAVE bit_FXSR /* for gcc compat */ |
Roman Divacky | 7abbb85 | 2013-07-19 17:28:36 +0000 | [diff] [blame] | 137 | #define bit_SSE 0x02000000 |
| 138 | #define bit_SSE2 0x04000000 |
| 139 | #define bit_SS 0x08000000 |
| 140 | #define bit_HTT 0x10000000 |
| 141 | #define bit_TM 0x20000000 |
| 142 | #define bit_PBE 0x80000000 |
| 143 | |
| 144 | /* Features in %ebx for level 7 sub-leaf 0 */ |
| 145 | #define bit_FSGSBASE 0x00000001 |
| 146 | #define bit_SMEP 0x00000080 |
| 147 | #define bit_ENH_MOVSB 0x00000200 |
| 148 | |
Roman Divacky | 7abbb85 | 2013-07-19 17:28:36 +0000 | [diff] [blame] | 149 | #if __i386__ |
| 150 | #define __cpuid(__level, __eax, __ebx, __ecx, __edx) \ |
Roman Divacky | 7abbb85 | 2013-07-19 17:28:36 +0000 | [diff] [blame] | 151 | __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ |
| 152 | : "0"(__level)) |
| 153 | |
| 154 | #define __cpuid_count(__level, __count, __eax, __ebx, __ecx, __edx) \ |
| 155 | __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ |
| 156 | : "0"(__level), "2"(__count)) |
Stephen Hines | 176edba | 2014-12-01 14:53:08 -0800 | [diff] [blame] | 157 | #else |
| 158 | /* x86-64 uses %rbx as the base register, so preserve it. */ |
| 159 | #define __cpuid(__level, __eax, __ebx, __ecx, __edx) \ |
| 160 | __asm(" xchgq %%rbx,%q1\n" \ |
| 161 | " cpuid\n" \ |
| 162 | " xchgq %%rbx,%q1" \ |
| 163 | : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ |
| 164 | : "0"(__level)) |
| 165 | |
| 166 | #define __cpuid_count(__level, __count, __eax, __ebx, __ecx, __edx) \ |
| 167 | __asm(" xchgq %%rbx,%q1\n" \ |
| 168 | " cpuid\n" \ |
| 169 | " xchgq %%rbx,%q1" \ |
| 170 | : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ |
| 171 | : "0"(__level), "2"(__count)) |
Roman Divacky | 7abbb85 | 2013-07-19 17:28:36 +0000 | [diff] [blame] | 172 | #endif |
| 173 | |
Richard Smith | 4a3c6c6 | 2013-04-04 02:55:24 +0000 | [diff] [blame] | 174 | static __inline int __get_cpuid (unsigned int __level, unsigned int *__eax, |
| 175 | unsigned int *__ebx, unsigned int *__ecx, |
| 176 | unsigned int *__edx) { |
Roman Divacky | 7abbb85 | 2013-07-19 17:28:36 +0000 | [diff] [blame] | 177 | __cpuid(__level, *__eax, *__ebx, *__ecx, *__edx); |
Rafael Espindola | b816276 | 2011-11-26 20:53:19 +0000 | [diff] [blame] | 178 | return 1; |
| 179 | } |
Roman Divacky | 7abbb85 | 2013-07-19 17:28:36 +0000 | [diff] [blame] | 180 | |
| 181 | static __inline int __get_cpuid_max (unsigned int __level, unsigned int *__sig) |
| 182 | { |
| 183 | unsigned int __eax, __ebx, __ecx, __edx; |
| 184 | #if __i386__ |
| 185 | int __cpuid_supported; |
| 186 | |
| 187 | __asm(" pushfl\n" |
| 188 | " popl %%eax\n" |
| 189 | " movl %%eax,%%ecx\n" |
| 190 | " xorl $0x00200000,%%eax\n" |
| 191 | " pushl %%eax\n" |
| 192 | " popfl\n" |
| 193 | " pushfl\n" |
| 194 | " popl %%eax\n" |
| 195 | " movl $0,%0\n" |
| 196 | " cmpl %%eax,%%ecx\n" |
| 197 | " je 1f\n" |
| 198 | " movl $1,%0\n" |
| 199 | "1:" |
| 200 | : "=r" (__cpuid_supported) : : "eax", "ecx"); |
| 201 | if (!__cpuid_supported) |
| 202 | return 0; |
| 203 | #endif |
| 204 | |
| 205 | __cpuid(__level, __eax, __ebx, __ecx, __edx); |
| 206 | if (__sig) |
| 207 | *__sig = __ebx; |
| 208 | return __eax; |
| 209 | } |