Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1 | /* radeon_state.c -- State support for Radeon -*- linux-c -*- |
| 2 | * |
| 3 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 21 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 22 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | * Authors: |
David Dawes | 0e5b8d7 | 2001-03-19 17:45:52 +0000 | [diff] [blame] | 26 | * Gareth Hughes <gareth@valinux.com> |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 27 | * Kevin E. Martin <martin@valinux.com> |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 28 | */ |
| 29 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 30 | #include "radeon.h" |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 31 | #include "drmP.h" |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 32 | #include "drm.h" |
Jens Owen | 3903e5a | 2002-04-09 21:54:56 +0000 | [diff] [blame] | 33 | #include "radeon_drm.h" |
| 34 | #include "radeon_drv.h" |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 35 | |
| 36 | |
| 37 | /* ================================================================ |
| 38 | * CP hardware state programming functions |
| 39 | */ |
| 40 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 41 | static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv, |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 42 | drm_clip_rect_t *box ) |
| 43 | { |
| 44 | RING_LOCALS; |
| 45 | |
| 46 | DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n", |
| 47 | box->x1, box->y1, box->x2, box->y2 ); |
| 48 | |
Keith Whitwell | ca81e13 | 2002-07-04 11:55:44 +0000 | [diff] [blame] | 49 | BEGIN_RING( 4 ); |
| 50 | OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 51 | OUT_RING( (box->y1 << 16) | box->x1 ); |
Keith Whitwell | ca81e13 | 2002-07-04 11:55:44 +0000 | [diff] [blame] | 52 | OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) ); |
Michel Daenzer | 881a9b2 | 2002-07-18 23:17:13 +0000 | [diff] [blame] | 53 | OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 54 | ADVANCE_RING(); |
| 55 | } |
| 56 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 57 | /* Emit 1.1 state |
| 58 | */ |
| 59 | static void radeon_emit_state( drm_radeon_private_t *dev_priv, |
| 60 | drm_radeon_context_regs_t *ctx, |
| 61 | drm_radeon_texture_regs_t *tex, |
| 62 | unsigned int dirty ) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 63 | { |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 64 | RING_LOCALS; |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 65 | DRM_DEBUG( "dirty=0x%08x\n", dirty ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 66 | |
| 67 | if ( dirty & RADEON_UPLOAD_CONTEXT ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 68 | BEGIN_RING( 14 ); |
| 69 | OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) ); |
| 70 | OUT_RING( ctx->pp_misc ); |
| 71 | OUT_RING( ctx->pp_fog_color ); |
| 72 | OUT_RING( ctx->re_solid_color ); |
| 73 | OUT_RING( ctx->rb3d_blendcntl ); |
| 74 | OUT_RING( ctx->rb3d_depthoffset ); |
| 75 | OUT_RING( ctx->rb3d_depthpitch ); |
| 76 | OUT_RING( ctx->rb3d_zstencilcntl ); |
| 77 | OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) ); |
| 78 | OUT_RING( ctx->pp_cntl ); |
| 79 | OUT_RING( ctx->rb3d_cntl ); |
| 80 | OUT_RING( ctx->rb3d_coloroffset ); |
| 81 | OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) ); |
| 82 | OUT_RING( ctx->rb3d_colorpitch ); |
| 83 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | if ( dirty & RADEON_UPLOAD_VERTFMT ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 87 | BEGIN_RING( 2 ); |
| 88 | OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) ); |
| 89 | OUT_RING( ctx->se_coord_fmt ); |
| 90 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | if ( dirty & RADEON_UPLOAD_LINE ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 94 | BEGIN_RING( 5 ); |
| 95 | OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) ); |
| 96 | OUT_RING( ctx->re_line_pattern ); |
| 97 | OUT_RING( ctx->re_line_state ); |
| 98 | OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) ); |
| 99 | OUT_RING( ctx->se_line_width ); |
| 100 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | if ( dirty & RADEON_UPLOAD_BUMPMAP ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 104 | BEGIN_RING( 5 ); |
| 105 | OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) ); |
| 106 | OUT_RING( ctx->pp_lum_matrix ); |
| 107 | OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) ); |
| 108 | OUT_RING( ctx->pp_rot_matrix_0 ); |
| 109 | OUT_RING( ctx->pp_rot_matrix_1 ); |
| 110 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | if ( dirty & RADEON_UPLOAD_MASKS ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 114 | BEGIN_RING( 4 ); |
| 115 | OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) ); |
| 116 | OUT_RING( ctx->rb3d_stencilrefmask ); |
| 117 | OUT_RING( ctx->rb3d_ropcntl ); |
| 118 | OUT_RING( ctx->rb3d_planemask ); |
| 119 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | if ( dirty & RADEON_UPLOAD_VIEWPORT ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 123 | BEGIN_RING( 7 ); |
| 124 | OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) ); |
| 125 | OUT_RING( ctx->se_vport_xscale ); |
| 126 | OUT_RING( ctx->se_vport_xoffset ); |
| 127 | OUT_RING( ctx->se_vport_yscale ); |
| 128 | OUT_RING( ctx->se_vport_yoffset ); |
| 129 | OUT_RING( ctx->se_vport_zscale ); |
| 130 | OUT_RING( ctx->se_vport_zoffset ); |
| 131 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 132 | } |
| 133 | |
| 134 | if ( dirty & RADEON_UPLOAD_SETUP ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 135 | BEGIN_RING( 4 ); |
| 136 | OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) ); |
| 137 | OUT_RING( ctx->se_cntl ); |
| 138 | OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) ); |
| 139 | OUT_RING( ctx->se_cntl_status ); |
| 140 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | if ( dirty & RADEON_UPLOAD_MISC ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 144 | BEGIN_RING( 2 ); |
| 145 | OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) ); |
| 146 | OUT_RING( ctx->re_misc ); |
| 147 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | if ( dirty & RADEON_UPLOAD_TEX0 ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 151 | BEGIN_RING( 9 ); |
| 152 | OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) ); |
| 153 | OUT_RING( tex[0].pp_txfilter ); |
| 154 | OUT_RING( tex[0].pp_txformat ); |
| 155 | OUT_RING( tex[0].pp_txoffset ); |
| 156 | OUT_RING( tex[0].pp_txcblend ); |
| 157 | OUT_RING( tex[0].pp_txablend ); |
| 158 | OUT_RING( tex[0].pp_tfactor ); |
| 159 | OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) ); |
| 160 | OUT_RING( tex[0].pp_border_color ); |
| 161 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 162 | } |
| 163 | |
| 164 | if ( dirty & RADEON_UPLOAD_TEX1 ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 165 | BEGIN_RING( 9 ); |
| 166 | OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) ); |
| 167 | OUT_RING( tex[1].pp_txfilter ); |
| 168 | OUT_RING( tex[1].pp_txformat ); |
| 169 | OUT_RING( tex[1].pp_txoffset ); |
| 170 | OUT_RING( tex[1].pp_txcblend ); |
| 171 | OUT_RING( tex[1].pp_txablend ); |
| 172 | OUT_RING( tex[1].pp_tfactor ); |
| 173 | OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) ); |
| 174 | OUT_RING( tex[1].pp_border_color ); |
| 175 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 176 | } |
| 177 | |
| 178 | if ( dirty & RADEON_UPLOAD_TEX2 ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 179 | BEGIN_RING( 9 ); |
| 180 | OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) ); |
| 181 | OUT_RING( tex[2].pp_txfilter ); |
| 182 | OUT_RING( tex[2].pp_txformat ); |
| 183 | OUT_RING( tex[2].pp_txoffset ); |
| 184 | OUT_RING( tex[2].pp_txcblend ); |
| 185 | OUT_RING( tex[2].pp_txablend ); |
| 186 | OUT_RING( tex[2].pp_tfactor ); |
| 187 | OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) ); |
| 188 | OUT_RING( tex[2].pp_border_color ); |
| 189 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 190 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 191 | } |
| 192 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 193 | /* Emit 1.2 state |
| 194 | */ |
| 195 | static void radeon_emit_state2( drm_radeon_private_t *dev_priv, |
| 196 | drm_radeon_state_t *state ) |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 197 | { |
| 198 | RING_LOCALS; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 199 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 200 | if (state->dirty & RADEON_UPLOAD_ZBIAS) { |
| 201 | BEGIN_RING( 3 ); |
| 202 | OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) ); |
| 203 | OUT_RING( state->context2.se_zbias_factor ); |
| 204 | OUT_RING( state->context2.se_zbias_constant ); |
| 205 | ADVANCE_RING(); |
| 206 | } |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 207 | |
| 208 | radeon_emit_state( dev_priv, &state->context, |
| 209 | state->tex, state->dirty ); |
| 210 | } |
| 211 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 212 | /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in |
| 213 | * 1.3 cmdbuffers allow all previous state to be updated as well as |
| 214 | * the tcl scalar and vector areas. |
| 215 | */ |
| 216 | static struct { |
| 217 | int start; |
| 218 | int len; |
| 219 | const char *name; |
| 220 | } packet[RADEON_MAX_STATE_PACKETS] = { |
| 221 | { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, |
| 222 | { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" }, |
| 223 | { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" }, |
| 224 | { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" }, |
| 225 | { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" }, |
| 226 | { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" }, |
| 227 | { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" }, |
| 228 | { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" }, |
| 229 | { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" }, |
| 230 | { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" }, |
| 231 | { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" }, |
| 232 | { RADEON_RE_MISC,1,"RADEON_RE_MISC" }, |
| 233 | { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" }, |
| 234 | { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" }, |
| 235 | { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" }, |
| 236 | { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" }, |
| 237 | { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" }, |
| 238 | { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" }, |
| 239 | { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" }, |
| 240 | { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" }, |
| 241 | { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" }, |
| 242 | }; |
| 243 | |
| 244 | |
| 245 | |
| 246 | |
| 247 | |
| 248 | |
| 249 | |
| 250 | |
| 251 | |
| 252 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 253 | #if RADEON_PERFORMANCE_BOXES |
| 254 | /* ================================================================ |
| 255 | * Performance monitoring functions |
| 256 | */ |
| 257 | |
| 258 | static void radeon_clear_box( drm_radeon_private_t *dev_priv, |
| 259 | int x, int y, int w, int h, |
| 260 | int r, int g, int b ) |
| 261 | { |
| 262 | u32 pitch, offset; |
| 263 | u32 color; |
| 264 | RING_LOCALS; |
| 265 | |
| 266 | switch ( dev_priv->color_fmt ) { |
| 267 | case RADEON_COLOR_FORMAT_RGB565: |
| 268 | color = (((r & 0xf8) << 8) | |
| 269 | ((g & 0xfc) << 3) | |
| 270 | ((b & 0xf8) >> 3)); |
| 271 | break; |
| 272 | case RADEON_COLOR_FORMAT_ARGB8888: |
| 273 | default: |
| 274 | color = (((0xff) << 24) | (r << 16) | (g << 8) | b); |
| 275 | break; |
| 276 | } |
| 277 | |
| 278 | offset = dev_priv->back_offset; |
| 279 | pitch = dev_priv->back_pitch >> 3; |
| 280 | |
| 281 | BEGIN_RING( 6 ); |
| 282 | |
| 283 | OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); |
| 284 | OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| 285 | RADEON_GMC_BRUSH_SOLID_COLOR | |
| 286 | (dev_priv->color_fmt << 8) | |
| 287 | RADEON_GMC_SRC_DATATYPE_COLOR | |
| 288 | RADEON_ROP3_P | |
| 289 | RADEON_GMC_CLR_CMP_CNTL_DIS ); |
| 290 | |
| 291 | OUT_RING( (pitch << 22) | (offset >> 5) ); |
| 292 | OUT_RING( color ); |
| 293 | |
| 294 | OUT_RING( (x << 16) | y ); |
| 295 | OUT_RING( (w << 16) | h ); |
| 296 | |
| 297 | ADVANCE_RING(); |
| 298 | } |
| 299 | |
| 300 | static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv ) |
| 301 | { |
| 302 | if ( atomic_read( &dev_priv->idle_count ) == 0 ) { |
| 303 | radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); |
| 304 | } else { |
| 305 | atomic_set( &dev_priv->idle_count, 0 ); |
| 306 | } |
| 307 | } |
| 308 | |
| 309 | #endif |
| 310 | |
| 311 | |
| 312 | /* ================================================================ |
| 313 | * CP command dispatch functions |
| 314 | */ |
| 315 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 316 | static void radeon_cp_dispatch_clear( drm_device_t *dev, |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 317 | drm_radeon_clear_t *clear, |
| 318 | drm_radeon_clear_rect_t *depth_boxes ) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 319 | { |
| 320 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 321 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 322 | drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 323 | int nbox = sarea_priv->nbox; |
| 324 | drm_clip_rect_t *pbox = sarea_priv->boxes; |
| 325 | unsigned int flags = clear->flags; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 326 | u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 327 | int i; |
| 328 | RING_LOCALS; |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 329 | DRM_DEBUG( "flags = 0x%x\n", flags ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 330 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 331 | if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { |
| 332 | unsigned int tmp = flags; |
| 333 | |
| 334 | flags &= ~(RADEON_FRONT | RADEON_BACK); |
| 335 | if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK; |
| 336 | if ( tmp & RADEON_BACK ) flags |= RADEON_FRONT; |
| 337 | } |
| 338 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 339 | /* We have to clear the depth and/or stencil buffers by |
| 340 | * rendering a quad into just those buffers. Thus, we have to |
| 341 | * make sure the 3D engine is configured correctly. |
| 342 | */ |
| 343 | if ( flags & (RADEON_DEPTH | RADEON_STENCIL) ) { |
| 344 | rb3d_cntl = depth_clear->rb3d_cntl; |
| 345 | |
| 346 | if ( flags & RADEON_DEPTH ) { |
| 347 | rb3d_cntl |= RADEON_Z_ENABLE; |
| 348 | } else { |
| 349 | rb3d_cntl &= ~RADEON_Z_ENABLE; |
| 350 | } |
| 351 | |
| 352 | if ( flags & RADEON_STENCIL ) { |
| 353 | rb3d_cntl |= RADEON_STENCIL_ENABLE; |
| 354 | rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */ |
| 355 | } else { |
| 356 | rb3d_cntl &= ~RADEON_STENCIL_ENABLE; |
| 357 | rb3d_stencilrefmask = 0x00000000; |
| 358 | } |
| 359 | } |
| 360 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 361 | for ( i = 0 ; i < nbox ; i++ ) { |
| 362 | int x = pbox[i].x1; |
| 363 | int y = pbox[i].y1; |
| 364 | int w = pbox[i].x2 - x; |
| 365 | int h = pbox[i].y2 - y; |
| 366 | |
| 367 | DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", |
| 368 | x, y, w, h, flags ); |
| 369 | |
| 370 | if ( flags & (RADEON_FRONT | RADEON_BACK) ) { |
| 371 | BEGIN_RING( 4 ); |
| 372 | |
| 373 | /* Ensure the 3D stream is idle before doing a |
| 374 | * 2D fill to clear the front or back buffer. |
| 375 | */ |
| 376 | RADEON_WAIT_UNTIL_3D_IDLE(); |
| 377 | |
| 378 | OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 379 | OUT_RING( clear->color_mask ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 380 | |
| 381 | ADVANCE_RING(); |
| 382 | |
| 383 | /* Make sure we restore the 3D state next time. |
| 384 | */ |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 385 | dev_priv->sarea_priv->ctx_owner = 0; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | if ( flags & RADEON_FRONT ) { |
| 389 | BEGIN_RING( 6 ); |
| 390 | |
| 391 | OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); |
| 392 | OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| 393 | RADEON_GMC_BRUSH_SOLID_COLOR | |
| 394 | (dev_priv->color_fmt << 8) | |
| 395 | RADEON_GMC_SRC_DATATYPE_COLOR | |
| 396 | RADEON_ROP3_P | |
| 397 | RADEON_GMC_CLR_CMP_CNTL_DIS ); |
| 398 | |
| 399 | OUT_RING( dev_priv->front_pitch_offset ); |
| 400 | OUT_RING( clear->clear_color ); |
| 401 | |
| 402 | OUT_RING( (x << 16) | y ); |
| 403 | OUT_RING( (w << 16) | h ); |
| 404 | |
| 405 | ADVANCE_RING(); |
| 406 | } |
| 407 | |
| 408 | if ( flags & RADEON_BACK ) { |
| 409 | BEGIN_RING( 6 ); |
| 410 | |
| 411 | OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); |
| 412 | OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| 413 | RADEON_GMC_BRUSH_SOLID_COLOR | |
| 414 | (dev_priv->color_fmt << 8) | |
| 415 | RADEON_GMC_SRC_DATATYPE_COLOR | |
| 416 | RADEON_ROP3_P | |
| 417 | RADEON_GMC_CLR_CMP_CNTL_DIS ); |
| 418 | |
| 419 | OUT_RING( dev_priv->back_pitch_offset ); |
| 420 | OUT_RING( clear->clear_color ); |
| 421 | |
| 422 | OUT_RING( (x << 16) | y ); |
| 423 | OUT_RING( (w << 16) | h ); |
| 424 | |
| 425 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 426 | } |
| 427 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 428 | if ( flags & (RADEON_DEPTH | RADEON_STENCIL) ) { |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 429 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 430 | radeon_emit_clip_rect( dev_priv, |
| 431 | &sarea_priv->boxes[i] ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 432 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 433 | BEGIN_RING( 28 ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 434 | |
| 435 | RADEON_WAIT_UNTIL_2D_IDLE(); |
| 436 | |
| 437 | OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) ); |
| 438 | OUT_RING( 0x00000000 ); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 439 | OUT_RING( rb3d_cntl ); |
| 440 | |
| 441 | OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, |
| 442 | depth_clear->rb3d_zstencilcntl ); |
| 443 | OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, |
| 444 | rb3d_stencilrefmask ); |
| 445 | OUT_RING_REG( RADEON_RB3D_PLANEMASK, |
| 446 | 0x00000000 ); |
| 447 | OUT_RING_REG( RADEON_SE_CNTL, |
| 448 | depth_clear->se_cntl ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 449 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 450 | /* Radeon 7500 doesn't like vertices without |
| 451 | * color. |
| 452 | */ |
| 453 | OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) ); |
| 454 | OUT_RING( RADEON_VTX_Z_PRESENT | |
| 455 | RADEON_VTX_PKCOLOR_PRESENT); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 456 | OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | |
| 457 | RADEON_PRIM_WALK_RING | |
| 458 | RADEON_MAOS_ENABLE | |
| 459 | RADEON_VTX_FMT_RADEON_MODE | |
| 460 | (3 << RADEON_NUM_VERTICES_SHIFT)) ); |
| 461 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 462 | OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); |
| 463 | OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); |
| 464 | OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 465 | OUT_RING( 0x0 ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 466 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 467 | OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); |
| 468 | OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); |
| 469 | OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 470 | OUT_RING( 0x0 ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 471 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 472 | OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); |
| 473 | OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); |
| 474 | OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 475 | OUT_RING( 0x0 ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 476 | |
| 477 | ADVANCE_RING(); |
| 478 | |
| 479 | /* Make sure we restore the 3D state next time. |
| 480 | */ |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 481 | dev_priv->sarea_priv->ctx_owner = 0; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 482 | } |
| 483 | } |
| 484 | |
| 485 | /* Increment the clear counter. The client-side 3D driver must |
| 486 | * wait on this value before performing the clear ioctl. We |
| 487 | * need this because the card's so damned fast... |
| 488 | */ |
| 489 | dev_priv->sarea_priv->last_clear++; |
| 490 | |
| 491 | BEGIN_RING( 4 ); |
| 492 | |
| 493 | RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear ); |
| 494 | RADEON_WAIT_UNTIL_IDLE(); |
| 495 | |
| 496 | ADVANCE_RING(); |
| 497 | } |
| 498 | |
| 499 | static void radeon_cp_dispatch_swap( drm_device_t *dev ) |
| 500 | { |
| 501 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 502 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
| 503 | int nbox = sarea_priv->nbox; |
| 504 | drm_clip_rect_t *pbox = sarea_priv->boxes; |
| 505 | int i; |
| 506 | RING_LOCALS; |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 507 | DRM_DEBUG( "\n" ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 508 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 509 | #if RADEON_PERFORMANCE_BOXES |
| 510 | /* Do some trivial performance monitoring... |
| 511 | */ |
| 512 | radeon_cp_performance_boxes( dev_priv ); |
| 513 | #endif |
| 514 | |
| 515 | /* Wait for the 3D stream to idle before dispatching the bitblt. |
| 516 | * This will prevent data corruption between the two streams. |
| 517 | */ |
| 518 | BEGIN_RING( 2 ); |
| 519 | |
| 520 | RADEON_WAIT_UNTIL_3D_IDLE(); |
| 521 | |
| 522 | ADVANCE_RING(); |
| 523 | |
| 524 | for ( i = 0 ; i < nbox ; i++ ) { |
| 525 | int x = pbox[i].x1; |
| 526 | int y = pbox[i].y1; |
| 527 | int w = pbox[i].x2 - x; |
| 528 | int h = pbox[i].y2 - y; |
| 529 | |
| 530 | DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n", |
| 531 | x, y, w, h ); |
| 532 | |
| 533 | BEGIN_RING( 7 ); |
| 534 | |
| 535 | OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) ); |
| 536 | OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
| 537 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| 538 | RADEON_GMC_BRUSH_NONE | |
| 539 | (dev_priv->color_fmt << 8) | |
| 540 | RADEON_GMC_SRC_DATATYPE_COLOR | |
| 541 | RADEON_ROP3_S | |
| 542 | RADEON_DP_SRC_SOURCE_MEMORY | |
| 543 | RADEON_GMC_CLR_CMP_CNTL_DIS | |
| 544 | RADEON_GMC_WR_MSK_DIS ); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 545 | |
| 546 | /* Make this work even if front & back are flipped: |
| 547 | */ |
| 548 | if (dev_priv->current_page == 0) { |
| 549 | OUT_RING( dev_priv->back_pitch_offset ); |
| 550 | OUT_RING( dev_priv->front_pitch_offset ); |
| 551 | } |
| 552 | else { |
| 553 | OUT_RING( dev_priv->front_pitch_offset ); |
| 554 | OUT_RING( dev_priv->back_pitch_offset ); |
| 555 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 556 | |
| 557 | OUT_RING( (x << 16) | y ); |
| 558 | OUT_RING( (x << 16) | y ); |
| 559 | OUT_RING( (w << 16) | h ); |
| 560 | |
| 561 | ADVANCE_RING(); |
| 562 | } |
| 563 | |
| 564 | /* Increment the frame counter. The client-side 3D driver must |
| 565 | * throttle the framerate by waiting for this value before |
| 566 | * performing the swapbuffer ioctl. |
| 567 | */ |
| 568 | dev_priv->sarea_priv->last_frame++; |
| 569 | |
| 570 | BEGIN_RING( 4 ); |
| 571 | |
| 572 | RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); |
| 573 | RADEON_WAIT_UNTIL_2D_IDLE(); |
| 574 | |
| 575 | ADVANCE_RING(); |
| 576 | } |
| 577 | |
| 578 | static void radeon_cp_dispatch_flip( drm_device_t *dev ) |
| 579 | { |
| 580 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 581 | RING_LOCALS; |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 582 | DRM_DEBUG( "page=%d\n", dev_priv->current_page ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 583 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 584 | #if RADEON_PERFORMANCE_BOXES |
| 585 | /* Do some trivial performance monitoring... |
| 586 | */ |
| 587 | radeon_cp_performance_boxes( dev_priv ); |
| 588 | #endif |
| 589 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 590 | BEGIN_RING( 4 ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 591 | |
| 592 | RADEON_WAIT_UNTIL_3D_IDLE(); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 593 | /* |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 594 | RADEON_WAIT_UNTIL_PAGE_FLIPPED(); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 595 | */ |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 596 | OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET, 0 ) ); |
| 597 | |
| 598 | if ( dev_priv->current_page == 0 ) { |
| 599 | OUT_RING( dev_priv->back_offset ); |
| 600 | dev_priv->current_page = 1; |
| 601 | } else { |
| 602 | OUT_RING( dev_priv->front_offset ); |
| 603 | dev_priv->current_page = 0; |
| 604 | } |
| 605 | |
| 606 | ADVANCE_RING(); |
| 607 | |
| 608 | /* Increment the frame counter. The client-side 3D driver must |
| 609 | * throttle the framerate by waiting for this value before |
| 610 | * performing the swapbuffer ioctl. |
| 611 | */ |
| 612 | dev_priv->sarea_priv->last_frame++; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 613 | dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 614 | |
| 615 | BEGIN_RING( 2 ); |
| 616 | |
| 617 | RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); |
| 618 | |
| 619 | ADVANCE_RING(); |
| 620 | } |
| 621 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 622 | static int bad_prim_vertex_nr( int primitive, int nr ) |
| 623 | { |
| 624 | switch (primitive & RADEON_PRIM_TYPE_MASK) { |
| 625 | case RADEON_PRIM_TYPE_NONE: |
| 626 | case RADEON_PRIM_TYPE_POINT: |
| 627 | return nr < 1; |
| 628 | case RADEON_PRIM_TYPE_LINE: |
| 629 | return (nr & 1) || nr == 0; |
| 630 | case RADEON_PRIM_TYPE_LINE_STRIP: |
| 631 | return nr < 2; |
| 632 | case RADEON_PRIM_TYPE_TRI_LIST: |
| 633 | case RADEON_PRIM_TYPE_3VRT_POINT_LIST: |
| 634 | case RADEON_PRIM_TYPE_3VRT_LINE_LIST: |
| 635 | case RADEON_PRIM_TYPE_RECT_LIST: |
| 636 | return nr % 3 || nr == 0; |
| 637 | case RADEON_PRIM_TYPE_TRI_FAN: |
| 638 | case RADEON_PRIM_TYPE_TRI_STRIP: |
| 639 | return nr < 3; |
| 640 | default: |
| 641 | return 1; |
| 642 | } |
| 643 | } |
| 644 | |
| 645 | |
| 646 | |
| 647 | typedef struct { |
| 648 | unsigned int start; |
| 649 | unsigned int finish; |
| 650 | unsigned int prim; |
| 651 | unsigned int numverts; |
| 652 | unsigned int offset; |
| 653 | unsigned int vc_format; |
| 654 | } drm_radeon_tcl_prim_t; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 655 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 656 | static void radeon_cp_dispatch_vertex( drm_device_t *dev, |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 657 | drm_buf_t *buf, |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 658 | drm_radeon_tcl_prim_t *prim, |
| 659 | drm_clip_rect_t *boxes, |
| 660 | int nbox ) |
| 661 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 662 | { |
| 663 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 664 | drm_clip_rect_t box; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 665 | int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start; |
| 666 | int numverts = (int)prim->numverts; |
| 667 | int i = 0; |
| 668 | RING_LOCALS; |
| 669 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 670 | DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n", |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 671 | prim->prim, |
| 672 | prim->vc_format, |
| 673 | prim->start, |
| 674 | prim->finish, |
| 675 | prim->numverts); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 676 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 677 | if (bad_prim_vertex_nr( prim->prim, prim->numverts )) { |
| 678 | DRM_ERROR( "bad prim %x numverts %d\n", |
| 679 | prim->prim, prim->numverts ); |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 680 | return; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 681 | } |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 682 | |
| 683 | do { |
| 684 | /* Emit the next cliprect */ |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 685 | if ( i < nbox ) { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 686 | if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) )) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 687 | return; |
| 688 | |
| 689 | radeon_emit_clip_rect( dev_priv, &box ); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 690 | } |
| 691 | |
| 692 | /* Emit the vertex buffer rendering commands */ |
| 693 | BEGIN_RING( 5 ); |
| 694 | |
| 695 | OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) ); |
| 696 | OUT_RING( offset ); |
| 697 | OUT_RING( numverts ); |
| 698 | OUT_RING( prim->vc_format ); |
| 699 | OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST | |
| 700 | RADEON_COLOR_ORDER_RGBA | |
| 701 | RADEON_VTX_FMT_RADEON_MODE | |
| 702 | (numverts << RADEON_NUM_VERTICES_SHIFT) ); |
| 703 | |
| 704 | ADVANCE_RING(); |
| 705 | |
| 706 | i++; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 707 | } while ( i < nbox ); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 708 | } |
| 709 | |
| 710 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 711 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 712 | static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf ) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 713 | { |
| 714 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 715 | drm_radeon_buf_priv_t *buf_priv = buf->dev_private; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 716 | RING_LOCALS; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 717 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 718 | buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 719 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 720 | /* Emit the vertex buffer age */ |
| 721 | BEGIN_RING( 2 ); |
| 722 | RADEON_DISPATCH_AGE( buf_priv->age ); |
| 723 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 724 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 725 | buf->pending = 1; |
| 726 | buf->used = 0; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 727 | } |
| 728 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 729 | static void radeon_cp_dispatch_indirect( drm_device_t *dev, |
| 730 | drm_buf_t *buf, |
| 731 | int start, int end ) |
| 732 | { |
| 733 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 734 | RING_LOCALS; |
| 735 | DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", |
| 736 | buf->idx, start, end ); |
| 737 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 738 | if ( start != end ) { |
| 739 | int offset = (dev_priv->agp_buffers_offset |
| 740 | + buf->offset + start); |
| 741 | int dwords = (end - start + 3) / sizeof(u32); |
| 742 | |
| 743 | /* Indirect buffer data must be an even number of |
| 744 | * dwords, so if we've been given an odd number we must |
| 745 | * pad the data with a Type-2 CP packet. |
| 746 | */ |
| 747 | if ( dwords & 1 ) { |
| 748 | u32 *data = (u32 *) |
| 749 | ((char *)dev_priv->buffers->handle |
| 750 | + buf->offset + start); |
| 751 | data[dwords++] = RADEON_CP_PACKET2; |
| 752 | } |
| 753 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 754 | /* Fire off the indirect buffer */ |
| 755 | BEGIN_RING( 3 ); |
| 756 | |
| 757 | OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) ); |
| 758 | OUT_RING( offset ); |
| 759 | OUT_RING( dwords ); |
| 760 | |
| 761 | ADVANCE_RING(); |
| 762 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 763 | } |
| 764 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 765 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 766 | static void radeon_cp_dispatch_indices( drm_device_t *dev, |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 767 | drm_buf_t *elt_buf, |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 768 | drm_radeon_tcl_prim_t *prim, |
| 769 | drm_clip_rect_t *boxes, |
| 770 | int nbox ) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 771 | { |
| 772 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 773 | drm_clip_rect_t box; |
| 774 | int offset = dev_priv->agp_buffers_offset + prim->offset; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 775 | u32 *data; |
| 776 | int dwords; |
| 777 | int i = 0; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 778 | int start = prim->start + RADEON_INDEX_PRIM_OFFSET; |
| 779 | int count = (prim->finish - start) / sizeof(u16); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 780 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 781 | DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 782 | prim->prim, |
| 783 | prim->vc_format, |
| 784 | prim->start, |
| 785 | prim->finish, |
| 786 | prim->offset, |
| 787 | prim->numverts); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 788 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 789 | if (bad_prim_vertex_nr( prim->prim, count )) { |
| 790 | DRM_ERROR( "bad prim %x count %d\n", |
| 791 | prim->prim, count ); |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 792 | return; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 793 | } |
| 794 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 795 | |
| 796 | if ( start >= prim->finish || |
| 797 | (prim->start & 0x7) ) { |
| 798 | DRM_ERROR( "buffer prim %d\n", prim->prim ); |
| 799 | return; |
| 800 | } |
| 801 | |
| 802 | dwords = (prim->finish - prim->start + 3) / sizeof(u32); |
| 803 | |
| 804 | data = (u32 *)((char *)dev_priv->buffers->handle + |
| 805 | elt_buf->offset + prim->start); |
| 806 | |
| 807 | data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 ); |
| 808 | data[1] = offset; |
| 809 | data[2] = prim->numverts; |
| 810 | data[3] = prim->vc_format; |
| 811 | data[4] = (prim->prim | |
| 812 | RADEON_PRIM_WALK_IND | |
| 813 | RADEON_COLOR_ORDER_RGBA | |
| 814 | RADEON_VTX_FMT_RADEON_MODE | |
| 815 | (count << RADEON_NUM_VERTICES_SHIFT) ); |
| 816 | |
| 817 | do { |
| 818 | if ( i < nbox ) { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 819 | if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) )) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 820 | return; |
| 821 | |
| 822 | radeon_emit_clip_rect( dev_priv, &box ); |
| 823 | } |
| 824 | |
| 825 | radeon_cp_dispatch_indirect( dev, elt_buf, |
| 826 | prim->start, |
| 827 | prim->finish ); |
| 828 | |
| 829 | i++; |
| 830 | } while ( i < nbox ); |
| 831 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 832 | } |
| 833 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 834 | #define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32)) |
| 835 | |
| 836 | static int radeon_cp_dispatch_texture( drm_device_t *dev, |
| 837 | drm_radeon_texture_t *tex, |
| 838 | drm_radeon_tex_image_t *image ) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 839 | { |
| 840 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 841 | drm_buf_t *buf; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 842 | u32 format; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 843 | u32 *buffer; |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 844 | const u8 *data; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 845 | int size, dwords, tex_width, blit_width; |
| 846 | u32 y, height; |
| 847 | int ret = 0, i; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 848 | RING_LOCALS; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 849 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 850 | /* FIXME: Be smarter about this... |
| 851 | */ |
| 852 | buf = radeon_freelist_get( dev ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 853 | if ( !buf ) return DRM_ERR(EAGAIN); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 854 | |
| 855 | DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", |
| 856 | tex->offset >> 10, tex->pitch, tex->format, |
| 857 | image->x, image->y, image->width, image->height ); |
| 858 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 859 | /* The compiler won't optimize away a division by a variable, |
| 860 | * even if the only legal values are powers of two. Thus, we'll |
| 861 | * use a shift instead. |
| 862 | */ |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 863 | switch ( tex->format ) { |
| 864 | case RADEON_TXFORMAT_ARGB8888: |
| 865 | case RADEON_TXFORMAT_RGBA8888: |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 866 | format = RADEON_COLOR_FORMAT_ARGB8888; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 867 | tex_width = tex->width * 4; |
| 868 | blit_width = image->width * 4; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 869 | break; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 870 | case RADEON_TXFORMAT_AI88: |
| 871 | case RADEON_TXFORMAT_ARGB1555: |
| 872 | case RADEON_TXFORMAT_RGB565: |
| 873 | case RADEON_TXFORMAT_ARGB4444: |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 874 | format = RADEON_COLOR_FORMAT_RGB565; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 875 | tex_width = tex->width * 2; |
| 876 | blit_width = image->width * 2; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 877 | break; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 878 | case RADEON_TXFORMAT_I8: |
| 879 | case RADEON_TXFORMAT_RGB332: |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 880 | format = RADEON_COLOR_FORMAT_CI8; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 881 | tex_width = tex->width * 1; |
| 882 | blit_width = image->width * 1; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 883 | break; |
| 884 | default: |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 885 | DRM_ERROR( "invalid texture format %d\n", tex->format ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 886 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 887 | } |
| 888 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 889 | DRM_DEBUG( " tex=%dx%d blit=%d\n", |
| 890 | tex_width, tex->height, blit_width ); |
| 891 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 892 | /* Flush the pixel cache. This ensures no pixel data gets mixed |
| 893 | * up with the texture data from the host data blit, otherwise |
| 894 | * part of the texture image may be corrupted. |
| 895 | */ |
| 896 | BEGIN_RING( 4 ); |
| 897 | |
| 898 | RADEON_FLUSH_CACHE(); |
| 899 | RADEON_WAIT_UNTIL_IDLE(); |
| 900 | |
| 901 | ADVANCE_RING(); |
| 902 | |
Michel Daenzer | 5676a2a | 2002-06-02 16:00:45 +0000 | [diff] [blame] | 903 | #ifdef __BIG_ENDIAN |
| 904 | /* The Mesa texture functions provide the data in little endian as the |
| 905 | * chip wants it, but we need to compensate for the fact that the CP |
| 906 | * ring gets byte-swapped |
| 907 | */ |
| 908 | BEGIN_RING( 2 ); |
| 909 | OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT ); |
| 910 | ADVANCE_RING(); |
| 911 | #endif |
| 912 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 913 | /* Make a copy of the parameters in case we have to update them |
| 914 | * for a multi-pass texture blit. |
| 915 | */ |
| 916 | y = image->y; |
| 917 | height = image->height; |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 918 | data = (const u8 *)image->data; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 919 | |
| 920 | size = height * blit_width; |
| 921 | |
| 922 | if ( size > RADEON_MAX_TEXTURE_SIZE ) { |
| 923 | /* Texture image is too large, do a multipass upload */ |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 924 | ret = DRM_ERR(EAGAIN); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 925 | |
| 926 | /* Adjust the blit size to fit the indirect buffer */ |
| 927 | height = RADEON_MAX_TEXTURE_SIZE / blit_width; |
| 928 | size = height * blit_width; |
| 929 | |
| 930 | /* Update the input parameters for next time */ |
| 931 | image->y += height; |
| 932 | image->height -= height; |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 933 | image->data = (const char *)image->data + size; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 934 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 935 | if ( DRM_COPY_TO_USER( tex->image, image, sizeof(*image) ) ) { |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 936 | DRM_ERROR( "EFAULT on tex->image\n" ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 937 | return DRM_ERR(EFAULT); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 938 | } |
David Dawes | 44aa4d6 | 2002-01-27 20:05:42 +0000 | [diff] [blame] | 939 | } else if ( size < 4 && size > 0 ) { |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 940 | size = 4; |
| 941 | } |
| 942 | |
| 943 | dwords = size / 4; |
| 944 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 945 | /* Dispatch the indirect buffer. |
| 946 | */ |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 947 | buffer = (u32 *)((char *)dev_priv->buffers->handle + buf->offset); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 948 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 949 | buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 ); |
| 950 | buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| 951 | RADEON_GMC_BRUSH_NONE | |
| 952 | (format << 8) | |
| 953 | RADEON_GMC_SRC_DATATYPE_COLOR | |
| 954 | RADEON_ROP3_S | |
| 955 | RADEON_DP_SRC_SOURCE_HOST_DATA | |
| 956 | RADEON_GMC_CLR_CMP_CNTL_DIS | |
| 957 | RADEON_GMC_WR_MSK_DIS); |
| 958 | |
| 959 | buffer[2] = (tex->pitch << 22) | (tex->offset >> 10); |
| 960 | buffer[3] = 0xffffffff; |
| 961 | buffer[4] = 0xffffffff; |
| 962 | buffer[5] = (y << 16) | image->x; |
| 963 | buffer[6] = (height << 16) | image->width; |
| 964 | buffer[7] = dwords; |
| 965 | |
| 966 | buffer += 8; |
| 967 | |
| 968 | if ( tex_width >= 32 ) { |
| 969 | /* Texture image width is larger than the minimum, so we |
| 970 | * can upload it directly. |
| 971 | */ |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 972 | if ( DRM_COPY_FROM_USER( buffer, data, dwords * sizeof(u32) ) ) { |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 973 | DRM_ERROR( "EFAULT on data, %d dwords\n", dwords ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 974 | return DRM_ERR(EFAULT); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 975 | } |
| 976 | } else { |
| 977 | /* Texture image width is less than the minimum, so we |
| 978 | * need to pad out each image scanline to the minimum |
| 979 | * width. |
| 980 | */ |
| 981 | for ( i = 0 ; i < tex->height ; i++ ) { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 982 | if ( DRM_COPY_FROM_USER( buffer, data, tex_width ) ) { |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 983 | DRM_ERROR( "EFAULT on pad, %d bytes\n", |
| 984 | tex_width ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 985 | return DRM_ERR(EFAULT); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 986 | } |
| 987 | buffer += 8; |
| 988 | data += tex_width; |
| 989 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 990 | } |
| 991 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 992 | buf->pid = DRM_CURRENTPID; |
David Dawes | 0e5b8d7 | 2001-03-19 17:45:52 +0000 | [diff] [blame] | 993 | buf->used = (dwords + 8) * sizeof(u32); |
| 994 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 995 | radeon_cp_dispatch_indirect( dev, buf, 0, buf->used ); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 996 | radeon_cp_discard_buffer( dev, buf ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 997 | |
| 998 | /* Flush the pixel cache after the blit completes. This ensures |
| 999 | * the texture data is written out to memory before rendering |
| 1000 | * continues. |
| 1001 | */ |
| 1002 | BEGIN_RING( 4 ); |
| 1003 | |
| 1004 | RADEON_FLUSH_CACHE(); |
| 1005 | RADEON_WAIT_UNTIL_2D_IDLE(); |
| 1006 | |
| 1007 | ADVANCE_RING(); |
| 1008 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1009 | return ret; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1010 | } |
| 1011 | |
| 1012 | static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple ) |
| 1013 | { |
| 1014 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1015 | int i; |
| 1016 | RING_LOCALS; |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1017 | DRM_DEBUG( "\n" ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1018 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1019 | BEGIN_RING( 35 ); |
| 1020 | |
| 1021 | OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) ); |
| 1022 | OUT_RING( 0x00000000 ); |
| 1023 | |
| 1024 | OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) ); |
| 1025 | for ( i = 0 ; i < 32 ; i++ ) { |
| 1026 | OUT_RING( stipple[i] ); |
| 1027 | } |
| 1028 | |
| 1029 | ADVANCE_RING(); |
| 1030 | } |
| 1031 | |
| 1032 | |
| 1033 | /* ================================================================ |
| 1034 | * IOCTL functions |
| 1035 | */ |
| 1036 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1037 | int radeon_cp_clear( DRM_IOCTL_ARGS ) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1038 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1039 | DRM_DEVICE; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1040 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1041 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
| 1042 | drm_radeon_clear_t clear; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1043 | drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1044 | DRM_DEBUG( "\n" ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1045 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1046 | LOCK_TEST_WITH_RETURN( dev ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1047 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1048 | DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t *)data, |
| 1049 | sizeof(clear) ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1050 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1051 | RING_SPACE_TEST_WITH_RETURN( dev_priv ); |
| 1052 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1053 | if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) |
| 1054 | sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; |
| 1055 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1056 | if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes, |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1057 | sarea_priv->nbox * sizeof(depth_boxes[0]) ) ) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1058 | return DRM_ERR(EFAULT); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1059 | |
| 1060 | radeon_cp_dispatch_clear( dev, &clear, depth_boxes ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1061 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1062 | COMMIT_RING(); |
| 1063 | return 0; |
| 1064 | } |
| 1065 | |
| 1066 | |
| 1067 | |
| 1068 | /* Not sure why this isn't set all the time: |
| 1069 | */ |
| 1070 | static int radeon_do_init_pageflip( drm_device_t *dev ) |
| 1071 | { |
| 1072 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Keith Whitwell | 24025ca | 2002-07-04 12:03:15 +0000 | [diff] [blame] | 1073 | RING_LOCALS; |
| 1074 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1075 | DRM_DEBUG( "\n" ); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1076 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1077 | dev_priv->crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL ); |
| 1078 | |
Keith Whitwell | 24025ca | 2002-07-04 12:03:15 +0000 | [diff] [blame] | 1079 | BEGIN_RING( 4 ); |
| 1080 | RADEON_WAIT_UNTIL_3D_IDLE(); |
| 1081 | OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) ); |
| 1082 | OUT_RING( dev_priv->crtc_offset_cntl | RADEON_CRTC_OFFSET_FLIP_CNTL ); |
| 1083 | ADVANCE_RING(); |
| 1084 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1085 | dev_priv->page_flipping = 1; |
| 1086 | dev_priv->current_page = 0; |
Keith Whitwell | bb91bc0 | 2002-06-27 17:56:39 +0000 | [diff] [blame] | 1087 | dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1088 | |
| 1089 | return 0; |
| 1090 | } |
| 1091 | |
| 1092 | int radeon_do_cleanup_pageflip( drm_device_t *dev ) |
| 1093 | { |
| 1094 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1095 | DRM_DEBUG( "\n" ); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1096 | |
Keith Whitwell | 24025ca | 2002-07-04 12:03:15 +0000 | [diff] [blame] | 1097 | if (dev_priv->current_page != 0) |
| 1098 | radeon_cp_dispatch_flip( dev ); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1099 | |
Keith Whitwell | 24025ca | 2002-07-04 12:03:15 +0000 | [diff] [blame] | 1100 | /* FIXME: If the X server changes screen resolution, it |
| 1101 | * clobbers the value of RADEON_CRTC_OFFSET_CNTL, above, |
| 1102 | * leading to a flashing efect. |
| 1103 | */ |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1104 | dev_priv->page_flipping = 0; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1105 | return 0; |
| 1106 | } |
| 1107 | |
| 1108 | /* Swapping and flipping are different operations, need different ioctls. |
| 1109 | * They can & should be intermixed to support multiple 3d windows. |
| 1110 | */ |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1111 | int radeon_cp_flip( DRM_IOCTL_ARGS ) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1112 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1113 | DRM_DEVICE; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1114 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1115 | DRM_DEBUG( "\n" ); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1116 | |
| 1117 | LOCK_TEST_WITH_RETURN( dev ); |
| 1118 | |
| 1119 | RING_SPACE_TEST_WITH_RETURN( dev_priv ); |
| 1120 | |
| 1121 | if (!dev_priv->page_flipping) |
| 1122 | radeon_do_init_pageflip( dev ); |
| 1123 | |
| 1124 | radeon_cp_dispatch_flip( dev ); |
| 1125 | |
| 1126 | COMMIT_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1127 | return 0; |
| 1128 | } |
| 1129 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1130 | int radeon_cp_swap( DRM_IOCTL_ARGS ) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1131 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1132 | DRM_DEVICE; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1133 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1134 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1135 | DRM_DEBUG( "\n" ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1136 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1137 | LOCK_TEST_WITH_RETURN( dev ); |
| 1138 | |
| 1139 | RING_SPACE_TEST_WITH_RETURN( dev_priv ); |
Gareth Hughes | 4d2a445 | 2001-01-24 15:34:46 +0000 | [diff] [blame] | 1140 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1141 | if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) |
| 1142 | sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; |
| 1143 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1144 | radeon_cp_dispatch_swap( dev ); |
| 1145 | dev_priv->sarea_priv->ctx_owner = 0; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1146 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1147 | COMMIT_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1148 | return 0; |
| 1149 | } |
| 1150 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1151 | int radeon_cp_vertex( DRM_IOCTL_ARGS ) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1152 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1153 | DRM_DEVICE; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1154 | drm_radeon_private_t *dev_priv = dev->dev_private; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1155 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1156 | drm_device_dma_t *dma = dev->dma; |
| 1157 | drm_buf_t *buf; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1158 | drm_radeon_vertex_t vertex; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1159 | drm_radeon_tcl_prim_t prim; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1160 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1161 | LOCK_TEST_WITH_RETURN( dev ); |
| 1162 | |
| 1163 | if ( !dev_priv ) { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1164 | DRM_ERROR( "%s called with no initialization\n", __func__ ); |
| 1165 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1166 | } |
| 1167 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1168 | DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t *)data, |
| 1169 | sizeof(vertex) ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1170 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1171 | DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", |
| 1172 | DRM_CURRENTPID, |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1173 | vertex.idx, vertex.count, vertex.discard ); |
| 1174 | |
| 1175 | if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { |
| 1176 | DRM_ERROR( "buffer index %d (of %d max)\n", |
| 1177 | vertex.idx, dma->buf_count - 1 ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1178 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1179 | } |
| 1180 | if ( vertex.prim < 0 || |
| 1181 | vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { |
| 1182 | DRM_ERROR( "buffer prim %d\n", vertex.prim ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1183 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1184 | } |
| 1185 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1186 | RING_SPACE_TEST_WITH_RETURN( dev_priv ); |
| 1187 | VB_AGE_TEST_WITH_RETURN( dev_priv ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1188 | |
| 1189 | buf = dma->buflist[vertex.idx]; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1190 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1191 | if ( buf->pid != DRM_CURRENTPID ) { |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1192 | DRM_ERROR( "process %d using buffer owned by %d\n", |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1193 | DRM_CURRENTPID, buf->pid ); |
| 1194 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1195 | } |
| 1196 | if ( buf->pending ) { |
| 1197 | DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1198 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1199 | } |
| 1200 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1201 | /* Build up a prim_t record: |
| 1202 | */ |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 1203 | if (vertex.count) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1204 | buf->used = vertex.count; /* not used? */ |
| 1205 | |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 1206 | if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { |
| 1207 | radeon_emit_state( dev_priv, |
| 1208 | &sarea_priv->context_state, |
| 1209 | sarea_priv->tex_state, |
| 1210 | sarea_priv->dirty ); |
| 1211 | |
| 1212 | sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | |
| 1213 | RADEON_UPLOAD_TEX1IMAGES | |
| 1214 | RADEON_UPLOAD_TEX2IMAGES | |
| 1215 | RADEON_REQUIRE_QUIESCENCE); |
| 1216 | } |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1217 | |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 1218 | prim.start = 0; |
| 1219 | prim.finish = vertex.count; /* unused */ |
| 1220 | prim.prim = vertex.prim; |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 1221 | prim.numverts = vertex.count; |
| 1222 | prim.vc_format = dev_priv->sarea_priv->vc_format; |
| 1223 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1224 | radeon_cp_dispatch_vertex( dev, buf, &prim, |
| 1225 | dev_priv->sarea_priv->boxes, |
| 1226 | dev_priv->sarea_priv->nbox ); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1227 | } |
| 1228 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1229 | if (vertex.discard) { |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 1230 | radeon_cp_discard_buffer( dev, buf ); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1231 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1232 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1233 | COMMIT_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1234 | return 0; |
| 1235 | } |
| 1236 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1237 | int radeon_cp_indices( DRM_IOCTL_ARGS ) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1238 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1239 | DRM_DEVICE; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1240 | drm_radeon_private_t *dev_priv = dev->dev_private; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1241 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1242 | drm_device_dma_t *dma = dev->dma; |
| 1243 | drm_buf_t *buf; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1244 | drm_radeon_indices_t elts; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1245 | drm_radeon_tcl_prim_t prim; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1246 | int count; |
| 1247 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1248 | LOCK_TEST_WITH_RETURN( dev ); |
| 1249 | |
| 1250 | if ( !dev_priv ) { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1251 | DRM_ERROR( "%s called with no initialization\n", __func__ ); |
| 1252 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1253 | } |
| 1254 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1255 | DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t *)data, |
| 1256 | sizeof(elts) ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1257 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1258 | DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n", |
| 1259 | DRM_CURRENTPID, |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1260 | elts.idx, elts.start, elts.end, elts.discard ); |
| 1261 | |
| 1262 | if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { |
| 1263 | DRM_ERROR( "buffer index %d (of %d max)\n", |
| 1264 | elts.idx, dma->buf_count - 1 ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1265 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1266 | } |
| 1267 | if ( elts.prim < 0 || |
| 1268 | elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { |
| 1269 | DRM_ERROR( "buffer prim %d\n", elts.prim ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1270 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1271 | } |
| 1272 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1273 | RING_SPACE_TEST_WITH_RETURN( dev_priv ); |
| 1274 | VB_AGE_TEST_WITH_RETURN( dev_priv ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1275 | |
| 1276 | buf = dma->buflist[elts.idx]; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1277 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1278 | if ( buf->pid != DRM_CURRENTPID ) { |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1279 | DRM_ERROR( "process %d using buffer owned by %d\n", |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1280 | DRM_CURRENTPID, buf->pid ); |
| 1281 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1282 | } |
| 1283 | if ( buf->pending ) { |
| 1284 | DRM_ERROR( "sending pending buffer %d\n", elts.idx ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1285 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1286 | } |
| 1287 | |
| 1288 | count = (elts.end - elts.start) / sizeof(u16); |
| 1289 | elts.start -= RADEON_INDEX_PRIM_OFFSET; |
| 1290 | |
| 1291 | if ( elts.start & 0x7 ) { |
| 1292 | DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1293 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1294 | } |
| 1295 | if ( elts.start < buf->used ) { |
| 1296 | DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1297 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1298 | } |
| 1299 | |
| 1300 | buf->used = elts.end; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1301 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1302 | if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { |
| 1303 | radeon_emit_state( dev_priv, |
| 1304 | &sarea_priv->context_state, |
| 1305 | sarea_priv->tex_state, |
| 1306 | sarea_priv->dirty ); |
| 1307 | |
| 1308 | sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | |
| 1309 | RADEON_UPLOAD_TEX1IMAGES | |
| 1310 | RADEON_UPLOAD_TEX2IMAGES | |
| 1311 | RADEON_REQUIRE_QUIESCENCE); |
| 1312 | } |
| 1313 | |
| 1314 | |
| 1315 | /* Build up a prim_t record: |
| 1316 | */ |
| 1317 | prim.start = elts.start; |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 1318 | prim.finish = elts.end; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1319 | prim.prim = elts.prim; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1320 | prim.offset = 0; /* offset from start of dma buffers */ |
| 1321 | prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1322 | prim.vc_format = dev_priv->sarea_priv->vc_format; |
| 1323 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1324 | radeon_cp_dispatch_indices( dev, buf, &prim, |
| 1325 | dev_priv->sarea_priv->boxes, |
| 1326 | dev_priv->sarea_priv->nbox ); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1327 | if (elts.discard) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1328 | radeon_cp_discard_buffer( dev, buf ); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1329 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1330 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1331 | COMMIT_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1332 | return 0; |
| 1333 | } |
| 1334 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1335 | int radeon_cp_texture( DRM_IOCTL_ARGS ) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1336 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1337 | DRM_DEVICE; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1338 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1339 | drm_radeon_texture_t tex; |
| 1340 | drm_radeon_tex_image_t image; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1341 | int ret; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1342 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1343 | LOCK_TEST_WITH_RETURN( dev ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1344 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1345 | DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t *)data, sizeof(tex) ); |
Gareth Hughes | 3a74d3a | 2001-03-06 04:37:37 +0000 | [diff] [blame] | 1346 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1347 | if ( tex.image == NULL ) { |
| 1348 | DRM_ERROR( "null texture image!\n" ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1349 | return DRM_ERR(EINVAL); |
David Dawes | 0e5b8d7 | 2001-03-19 17:45:52 +0000 | [diff] [blame] | 1350 | } |
| 1351 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1352 | if ( DRM_COPY_FROM_USER( &image, |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1353 | (drm_radeon_tex_image_t *)tex.image, |
| 1354 | sizeof(image) ) ) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1355 | return DRM_ERR(EFAULT); |
David Dawes | 0e5b8d7 | 2001-03-19 17:45:52 +0000 | [diff] [blame] | 1356 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1357 | RING_SPACE_TEST_WITH_RETURN( dev_priv ); |
| 1358 | VB_AGE_TEST_WITH_RETURN( dev_priv ); |
| 1359 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1360 | ret = radeon_cp_dispatch_texture( dev, &tex, &image ); |
| 1361 | |
| 1362 | COMMIT_RING(); |
| 1363 | return ret; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1364 | } |
| 1365 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1366 | int radeon_cp_stipple( DRM_IOCTL_ARGS ) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1367 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1368 | DRM_DEVICE; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1369 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1370 | drm_radeon_stipple_t stipple; |
| 1371 | u32 mask[32]; |
| 1372 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1373 | LOCK_TEST_WITH_RETURN( dev ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1374 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1375 | DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t *)data, |
| 1376 | sizeof(stipple) ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1377 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1378 | if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) ) |
| 1379 | return DRM_ERR(EFAULT); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1380 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1381 | RING_SPACE_TEST_WITH_RETURN( dev_priv ); |
| 1382 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1383 | radeon_cp_dispatch_stipple( dev, mask ); |
| 1384 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1385 | COMMIT_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1386 | return 0; |
| 1387 | } |
| 1388 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1389 | int radeon_cp_indirect( DRM_IOCTL_ARGS ) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1390 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1391 | DRM_DEVICE; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1392 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1393 | drm_device_dma_t *dma = dev->dma; |
| 1394 | drm_buf_t *buf; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1395 | drm_radeon_indirect_t indirect; |
| 1396 | RING_LOCALS; |
| 1397 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1398 | LOCK_TEST_WITH_RETURN( dev ); |
| 1399 | |
| 1400 | if ( !dev_priv ) { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1401 | DRM_ERROR( "%s called with no initialization\n", __func__ ); |
| 1402 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1403 | } |
| 1404 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1405 | DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t *)data, |
| 1406 | sizeof(indirect) ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1407 | |
| 1408 | DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", |
| 1409 | indirect.idx, indirect.start, |
| 1410 | indirect.end, indirect.discard ); |
| 1411 | |
| 1412 | if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { |
| 1413 | DRM_ERROR( "buffer index %d (of %d max)\n", |
| 1414 | indirect.idx, dma->buf_count - 1 ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1415 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1416 | } |
| 1417 | |
| 1418 | buf = dma->buflist[indirect.idx]; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1419 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1420 | if ( buf->pid != DRM_CURRENTPID ) { |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1421 | DRM_ERROR( "process %d using buffer owned by %d\n", |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1422 | DRM_CURRENTPID, buf->pid ); |
| 1423 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1424 | } |
| 1425 | if ( buf->pending ) { |
| 1426 | DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1427 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1428 | } |
| 1429 | |
| 1430 | if ( indirect.start < buf->used ) { |
| 1431 | DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", |
| 1432 | indirect.start, buf->used ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1433 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1434 | } |
| 1435 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1436 | RING_SPACE_TEST_WITH_RETURN( dev_priv ); |
| 1437 | VB_AGE_TEST_WITH_RETURN( dev_priv ); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1438 | |
| 1439 | buf->used = indirect.end; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1440 | |
| 1441 | /* Wait for the 3D stream to idle before the indirect buffer |
| 1442 | * containing 2D acceleration commands is processed. |
| 1443 | */ |
| 1444 | BEGIN_RING( 2 ); |
| 1445 | |
| 1446 | RADEON_WAIT_UNTIL_3D_IDLE(); |
| 1447 | |
| 1448 | ADVANCE_RING(); |
| 1449 | |
| 1450 | /* Dispatch the indirect buffer full of commands from the |
| 1451 | * X server. This is insecure and is thus only available to |
| 1452 | * privileged clients. |
| 1453 | */ |
| 1454 | radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end ); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1455 | if (indirect.discard) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1456 | radeon_cp_discard_buffer( dev, buf ); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1457 | } |
| 1458 | |
| 1459 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1460 | COMMIT_RING(); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1461 | return 0; |
| 1462 | } |
| 1463 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1464 | int radeon_cp_vertex2( DRM_IOCTL_ARGS ) |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1465 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1466 | DRM_DEVICE; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1467 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1468 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1469 | drm_device_dma_t *dma = dev->dma; |
| 1470 | drm_buf_t *buf; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1471 | drm_radeon_vertex2_t vertex; |
| 1472 | int i; |
| 1473 | unsigned char laststate; |
| 1474 | |
| 1475 | LOCK_TEST_WITH_RETURN( dev ); |
| 1476 | |
| 1477 | if ( !dev_priv ) { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1478 | DRM_ERROR( "%s called with no initialization\n", __func__ ); |
| 1479 | return DRM_ERR(EINVAL); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1480 | } |
| 1481 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1482 | DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t *)data, |
| 1483 | sizeof(vertex) ); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1484 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1485 | DRM_DEBUG( "pid=%d index=%d discard=%d\n", |
| 1486 | DRM_CURRENTPID, |
| 1487 | vertex.idx, vertex.discard ); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1488 | |
| 1489 | if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { |
| 1490 | DRM_ERROR( "buffer index %d (of %d max)\n", |
| 1491 | vertex.idx, dma->buf_count - 1 ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1492 | return DRM_ERR(EINVAL); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1493 | } |
| 1494 | |
| 1495 | RING_SPACE_TEST_WITH_RETURN( dev_priv ); |
| 1496 | VB_AGE_TEST_WITH_RETURN( dev_priv ); |
| 1497 | |
| 1498 | buf = dma->buflist[vertex.idx]; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1499 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1500 | if ( buf->pid != DRM_CURRENTPID ) { |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1501 | DRM_ERROR( "process %d using buffer owned by %d\n", |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1502 | DRM_CURRENTPID, buf->pid ); |
| 1503 | return DRM_ERR(EINVAL); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1504 | } |
| 1505 | |
| 1506 | if ( buf->pending ) { |
| 1507 | DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1508 | return DRM_ERR(EINVAL); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1509 | } |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1510 | |
| 1511 | if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1512 | return DRM_ERR(EINVAL); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1513 | |
| 1514 | for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) { |
| 1515 | drm_radeon_prim_t prim; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1516 | drm_radeon_tcl_prim_t tclprim; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1517 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1518 | if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) ) |
| 1519 | return DRM_ERR(EFAULT); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1520 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1521 | if ( prim.stateidx != laststate ) { |
| 1522 | drm_radeon_state_t state; |
| 1523 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1524 | if ( DRM_COPY_FROM_USER( &state, |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1525 | &vertex.state[prim.stateidx], |
| 1526 | sizeof(state) ) ) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1527 | return DRM_ERR(EFAULT); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1528 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1529 | radeon_emit_state2( dev_priv, &state ); |
| 1530 | |
| 1531 | laststate = prim.stateidx; |
| 1532 | } |
| 1533 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1534 | tclprim.start = prim.start; |
| 1535 | tclprim.finish = prim.finish; |
| 1536 | tclprim.prim = prim.prim; |
| 1537 | tclprim.vc_format = prim.vc_format; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1538 | |
| 1539 | if ( prim.prim & RADEON_PRIM_WALK_IND ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1540 | tclprim.offset = prim.numverts * 64; |
| 1541 | tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ |
| 1542 | |
| 1543 | radeon_cp_dispatch_indices( dev, buf, &tclprim, |
| 1544 | sarea_priv->boxes, |
| 1545 | sarea_priv->nbox); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1546 | } else { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1547 | tclprim.numverts = prim.numverts; |
| 1548 | tclprim.offset = 0; /* not used */ |
| 1549 | |
| 1550 | radeon_cp_dispatch_vertex( dev, buf, &tclprim, |
| 1551 | sarea_priv->boxes, |
| 1552 | sarea_priv->nbox); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1553 | } |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1554 | |
| 1555 | if (sarea_priv->nbox == 1) |
| 1556 | sarea_priv->nbox = 0; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1557 | } |
| 1558 | |
| 1559 | if ( vertex.discard ) { |
| 1560 | radeon_cp_discard_buffer( dev, buf ); |
| 1561 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1562 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1563 | COMMIT_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1564 | return 0; |
| 1565 | } |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1566 | |
| 1567 | |
| 1568 | static int radeon_emit_packets( |
| 1569 | drm_radeon_private_t *dev_priv, |
| 1570 | drm_radeon_cmd_header_t header, |
| 1571 | drm_radeon_cmd_buffer_t *cmdbuf ) |
| 1572 | { |
| 1573 | int id = (int)header.packet.packet_id; |
| 1574 | int sz = packet[id].len; |
| 1575 | int reg = packet[id].start; |
| 1576 | int *data = (int *)cmdbuf->buf; |
| 1577 | RING_LOCALS; |
| 1578 | |
| 1579 | if (sz * sizeof(int) > cmdbuf->bufsz) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1580 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1581 | |
| 1582 | BEGIN_RING(sz+1); |
| 1583 | OUT_RING( CP_PACKET0( reg, (sz-1) ) ); |
| 1584 | OUT_RING_USER_TABLE( data, sz ); |
| 1585 | ADVANCE_RING(); |
| 1586 | |
| 1587 | cmdbuf->buf += sz * sizeof(int); |
| 1588 | cmdbuf->bufsz -= sz * sizeof(int); |
| 1589 | return 0; |
| 1590 | } |
| 1591 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1592 | static __inline__ int radeon_emit_scalars( |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1593 | drm_radeon_private_t *dev_priv, |
| 1594 | drm_radeon_cmd_header_t header, |
| 1595 | drm_radeon_cmd_buffer_t *cmdbuf ) |
| 1596 | { |
| 1597 | int sz = header.scalars.count; |
| 1598 | int *data = (int *)cmdbuf->buf; |
| 1599 | int start = header.scalars.offset; |
| 1600 | int stride = header.scalars.stride; |
| 1601 | RING_LOCALS; |
| 1602 | |
| 1603 | BEGIN_RING( 3+sz ); |
| 1604 | OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); |
| 1605 | OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); |
| 1606 | OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); |
| 1607 | OUT_RING_USER_TABLE( data, sz ); |
| 1608 | ADVANCE_RING(); |
| 1609 | cmdbuf->buf += sz * sizeof(int); |
| 1610 | cmdbuf->bufsz -= sz * sizeof(int); |
| 1611 | return 0; |
| 1612 | } |
| 1613 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1614 | static __inline__ int radeon_emit_vectors( |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1615 | drm_radeon_private_t *dev_priv, |
| 1616 | drm_radeon_cmd_header_t header, |
| 1617 | drm_radeon_cmd_buffer_t *cmdbuf ) |
| 1618 | { |
| 1619 | int sz = header.vectors.count; |
| 1620 | int *data = (int *)cmdbuf->buf; |
| 1621 | int start = header.vectors.offset; |
| 1622 | int stride = header.vectors.stride; |
| 1623 | RING_LOCALS; |
| 1624 | |
| 1625 | BEGIN_RING( 3+sz ); |
| 1626 | OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) ); |
| 1627 | OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); |
| 1628 | OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) ); |
| 1629 | OUT_RING_USER_TABLE( data, sz ); |
| 1630 | ADVANCE_RING(); |
| 1631 | |
| 1632 | cmdbuf->buf += sz * sizeof(int); |
| 1633 | cmdbuf->bufsz -= sz * sizeof(int); |
| 1634 | return 0; |
| 1635 | } |
| 1636 | |
| 1637 | |
| 1638 | static int radeon_emit_packet3( drm_device_t *dev, |
| 1639 | drm_radeon_cmd_buffer_t *cmdbuf ) |
| 1640 | { |
| 1641 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1642 | int cmdsz, tmp; |
| 1643 | int *cmd = (int *)cmdbuf->buf; |
| 1644 | RING_LOCALS; |
| 1645 | |
| 1646 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1647 | DRM_DEBUG("\n"); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1648 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1649 | if (DRM_GET_USER_UNCHECKED( tmp, &cmd[0])) |
| 1650 | return DRM_ERR(EFAULT); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1651 | |
| 1652 | cmdsz = 2 + ((tmp & RADEON_CP_PACKET_COUNT_MASK) >> 16); |
| 1653 | |
| 1654 | if ((tmp & 0xc0000000) != RADEON_CP_PACKET3 || |
| 1655 | cmdsz * 4 > cmdbuf->bufsz) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1656 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1657 | |
| 1658 | BEGIN_RING( cmdsz ); |
| 1659 | OUT_RING_USER_TABLE( cmd, cmdsz ); |
| 1660 | ADVANCE_RING(); |
| 1661 | |
| 1662 | cmdbuf->buf += cmdsz * 4; |
| 1663 | cmdbuf->bufsz -= cmdsz * 4; |
| 1664 | return 0; |
| 1665 | } |
| 1666 | |
| 1667 | |
| 1668 | static int radeon_emit_packet3_cliprect( drm_device_t *dev, |
Keith Whitwell | 33d5713 | 2002-08-12 07:26:00 +0000 | [diff] [blame^] | 1669 | drm_radeon_cmd_buffer_t *cmdbuf, |
| 1670 | int orig_nbox ) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1671 | { |
| 1672 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1673 | drm_clip_rect_t box; |
| 1674 | int cmdsz, tmp; |
| 1675 | int *cmd = (int *)cmdbuf->buf; |
| 1676 | drm_clip_rect_t *boxes = cmdbuf->boxes; |
| 1677 | int i = 0; |
| 1678 | RING_LOCALS; |
| 1679 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1680 | DRM_DEBUG("\n"); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1681 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1682 | if (DRM_GET_USER_UNCHECKED( tmp, &cmd[0])) |
| 1683 | return DRM_ERR(EFAULT); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1684 | |
| 1685 | cmdsz = 2 + ((tmp & RADEON_CP_PACKET_COUNT_MASK) >> 16); |
| 1686 | |
| 1687 | if ((tmp & 0xc0000000) != RADEON_CP_PACKET3 || |
| 1688 | cmdsz * 4 > cmdbuf->bufsz) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1689 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1690 | |
Keith Whitwell | 33d5713 | 2002-08-12 07:26:00 +0000 | [diff] [blame^] | 1691 | if (!orig_nbox) |
| 1692 | goto out; |
| 1693 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1694 | do { |
| 1695 | if ( i < cmdbuf->nbox ) { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1696 | if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) )) |
| 1697 | return DRM_ERR(EFAULT); |
Tim Smith | 8fa8db1 | 2002-07-17 08:30:36 +0000 | [diff] [blame] | 1698 | /* FIXME The second and subsequent times round this loop, send a |
| 1699 | * WAIT_UNTIL_3D_IDLE before calling emit_clip_rect(). This |
| 1700 | * fixes a lockup on fast machines when sending several |
| 1701 | * cliprects with a cmdbuf, as when waving a 2D window over |
| 1702 | * a 3D window. Something in the commands from user space |
| 1703 | * seems to hang the card when they're sent several times |
| 1704 | * in a row. That would be the correct place to fix it but |
| 1705 | * this works around it until I can figure that out - Tim Smith */ |
| 1706 | if ( i ) { |
| 1707 | BEGIN_RING( 2 ); |
| 1708 | RADEON_WAIT_UNTIL_3D_IDLE(); |
| 1709 | ADVANCE_RING(); |
| 1710 | } |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1711 | radeon_emit_clip_rect( dev_priv, &box ); |
| 1712 | } |
| 1713 | |
| 1714 | BEGIN_RING( cmdsz ); |
| 1715 | OUT_RING_USER_TABLE( cmd, cmdsz ); |
| 1716 | ADVANCE_RING(); |
| 1717 | |
| 1718 | } while ( ++i < cmdbuf->nbox ); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1719 | if (cmdbuf->nbox == 1) |
| 1720 | cmdbuf->nbox = 0; |
| 1721 | |
Keith Whitwell | 33d5713 | 2002-08-12 07:26:00 +0000 | [diff] [blame^] | 1722 | out: |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1723 | cmdbuf->buf += cmdsz * 4; |
| 1724 | cmdbuf->bufsz -= cmdsz * 4; |
| 1725 | return 0; |
| 1726 | } |
| 1727 | |
| 1728 | |
| 1729 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1730 | int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1731 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1732 | DRM_DEVICE; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1733 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1734 | drm_device_dma_t *dma = dev->dma; |
| 1735 | drm_buf_t *buf = 0; |
| 1736 | int idx; |
| 1737 | drm_radeon_cmd_buffer_t cmdbuf; |
| 1738 | drm_radeon_cmd_header_t header; |
Keith Whitwell | 33d5713 | 2002-08-12 07:26:00 +0000 | [diff] [blame^] | 1739 | int orig_nbox; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1740 | |
| 1741 | LOCK_TEST_WITH_RETURN( dev ); |
| 1742 | |
| 1743 | if ( !dev_priv ) { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1744 | DRM_ERROR( "%s called with no initialization\n", __func__ ); |
| 1745 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1746 | } |
| 1747 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1748 | DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t *)data, |
| 1749 | sizeof(cmdbuf) ); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1750 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1751 | DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1752 | RING_SPACE_TEST_WITH_RETURN( dev_priv ); |
| 1753 | VB_AGE_TEST_WITH_RETURN( dev_priv ); |
| 1754 | |
| 1755 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1756 | if (DRM_VERIFYAREA_READ( cmdbuf.buf, cmdbuf.bufsz )) |
| 1757 | return DRM_ERR(EFAULT); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1758 | |
| 1759 | if (cmdbuf.nbox && |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1760 | DRM_VERIFYAREA_READ(cmdbuf.boxes, |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1761 | cmdbuf.nbox * sizeof(drm_clip_rect_t))) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1762 | return DRM_ERR(EFAULT); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1763 | |
Keith Whitwell | 33d5713 | 2002-08-12 07:26:00 +0000 | [diff] [blame^] | 1764 | orig_nbox = cmdbuf.nbox; |
| 1765 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1766 | while ( cmdbuf.bufsz >= sizeof(header) ) { |
| 1767 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1768 | if (DRM_GET_USER_UNCHECKED( header.i, (int *)cmdbuf.buf )) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1769 | DRM_ERROR("__get_user %p\n", cmdbuf.buf); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1770 | return DRM_ERR(EFAULT); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1771 | } |
| 1772 | |
| 1773 | cmdbuf.buf += sizeof(header); |
| 1774 | cmdbuf.bufsz -= sizeof(header); |
| 1775 | |
| 1776 | switch (header.header.cmd_type) { |
| 1777 | case RADEON_CMD_PACKET: |
| 1778 | if (radeon_emit_packets( dev_priv, header, &cmdbuf )) { |
| 1779 | DRM_ERROR("radeon_emit_packets failed\n"); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1780 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1781 | } |
| 1782 | break; |
| 1783 | |
| 1784 | case RADEON_CMD_SCALARS: |
| 1785 | if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) { |
| 1786 | DRM_ERROR("radeon_emit_scalars failed\n"); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1787 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1788 | } |
| 1789 | break; |
| 1790 | |
| 1791 | case RADEON_CMD_VECTORS: |
| 1792 | if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) { |
| 1793 | DRM_ERROR("radeon_emit_vectors failed\n"); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1794 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1795 | } |
| 1796 | break; |
| 1797 | |
| 1798 | case RADEON_CMD_DMA_DISCARD: |
| 1799 | idx = header.dma.buf_idx; |
| 1800 | if ( idx < 0 || idx >= dma->buf_count ) { |
| 1801 | DRM_ERROR( "buffer index %d (of %d max)\n", |
| 1802 | idx, dma->buf_count - 1 ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1803 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1804 | } |
| 1805 | |
| 1806 | buf = dma->buflist[idx]; |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1807 | if ( buf->pid != DRM_CURRENTPID || buf->pending ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1808 | DRM_ERROR( "bad buffer\n" ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1809 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1810 | } |
| 1811 | |
| 1812 | radeon_cp_discard_buffer( dev, buf ); |
| 1813 | break; |
| 1814 | |
| 1815 | case RADEON_CMD_PACKET3: |
| 1816 | if (radeon_emit_packet3( dev, &cmdbuf )) { |
| 1817 | DRM_ERROR("radeon_emit_packet3 failed\n"); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1818 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1819 | } |
| 1820 | break; |
| 1821 | |
| 1822 | case RADEON_CMD_PACKET3_CLIP: |
Keith Whitwell | 33d5713 | 2002-08-12 07:26:00 +0000 | [diff] [blame^] | 1823 | if (radeon_emit_packet3_cliprect( dev, &cmdbuf, orig_nbox )) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1824 | DRM_ERROR("radeon_emit_packet3_clip failed\n"); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1825 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1826 | } |
| 1827 | break; |
| 1828 | |
| 1829 | default: |
| 1830 | DRM_ERROR("bad cmd_type %d at %p\n", |
| 1831 | header.header.cmd_type, |
| 1832 | cmdbuf.buf - sizeof(header)); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1833 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1834 | } |
| 1835 | } |
| 1836 | |
| 1837 | |
| 1838 | COMMIT_RING(); |
| 1839 | return 0; |
| 1840 | } |
| 1841 | |
| 1842 | |
| 1843 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1844 | int radeon_cp_getparam( DRM_IOCTL_ARGS ) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1845 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1846 | DRM_DEVICE; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1847 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1848 | drm_radeon_getparam_t param; |
| 1849 | int value; |
| 1850 | |
| 1851 | if ( !dev_priv ) { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1852 | DRM_ERROR( "%s called with no initialization\n", __func__ ); |
| 1853 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1854 | } |
| 1855 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1856 | DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t *)data, |
| 1857 | sizeof(param) ); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1858 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1859 | DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1860 | |
| 1861 | switch( param.param ) { |
| 1862 | case RADEON_PARAM_AGP_BUFFER_OFFSET: |
| 1863 | value = dev_priv->agp_buffers_offset; |
| 1864 | break; |
Michel Daenzer | fd86ac9 | 2002-07-11 20:31:12 +0000 | [diff] [blame] | 1865 | case RADEON_PARAM_LAST_FRAME: |
Michel Daenzer | d0ac4e5 | 2002-08-11 15:56:44 +0000 | [diff] [blame] | 1866 | value = GET_SCRATCH( 0 ); |
Michel Daenzer | fd86ac9 | 2002-07-11 20:31:12 +0000 | [diff] [blame] | 1867 | break; |
| 1868 | case RADEON_PARAM_LAST_DISPATCH: |
Michel Daenzer | d0ac4e5 | 2002-08-11 15:56:44 +0000 | [diff] [blame] | 1869 | value = GET_SCRATCH( 1 ); |
Michel Daenzer | fd86ac9 | 2002-07-11 20:31:12 +0000 | [diff] [blame] | 1870 | break; |
| 1871 | case RADEON_PARAM_LAST_CLEAR: |
Michel Daenzer | d0ac4e5 | 2002-08-11 15:56:44 +0000 | [diff] [blame] | 1872 | value = GET_SCRATCH( 2 ); |
Michel Daenzer | fd86ac9 | 2002-07-11 20:31:12 +0000 | [diff] [blame] | 1873 | break; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1874 | default: |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1875 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1876 | } |
| 1877 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1878 | if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1879 | DRM_ERROR( "copy_to_user\n" ); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1880 | return DRM_ERR(EFAULT); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1881 | } |
| 1882 | |
| 1883 | return 0; |
| 1884 | } |