lib/Target/X86/X86AsmPrinter.cpp - fp2-dev/platform/external/llvm - Gitiles

 //===-- X86AsmPrinter.cpp - Convert X86 LLVM code to Intel assembly -------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains a printer that converts from our internal representation
 // of machine-dependent LLVM code to Intel-format assembly language. This
 // printer is the output mechanism used by `llc' and `lli -print-machineinstrs'
 // on X86.
 //
 //===----------------------------------------------------------------------===//

 #include "X86.h"
 #include "X86InstrInfo.h"
 #include "X86TargetMachine.h"
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/Module.h"
 #include "llvm/Assembly/Writer.h"
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/MachineCodeEmitter.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Mangler.h"
 #include "Support/Statistic.h"
 #include "Support/StringExtras.h"
 #include "Support/CommandLine.h"
 using namespace llvm;

 namespace {
   Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");

   struct GasBugWorkaroundEmitter : public MachineCodeEmitter {
     GasBugWorkaroundEmitter(std::ostream& o)
       : O(o), OldFlags(O.flags()), firstByte(true) {
       O << std::hex;
     }

     ~GasBugWorkaroundEmitter() {
       O.flags(OldFlags);
     }

     virtual void emitByte(unsigned char B) {
       if (!firstByte) O << "\n\t";
       firstByte = false;
       O << ".byte 0x" << (unsigned) B;
     }

     // These should never be called
     virtual void emitWord(unsigned W) { assert(0); }
     virtual uint64_t getGlobalValueAddress(GlobalValue *V) { abort(); }
     virtual uint64_t getGlobalValueAddress(const std::string &Name) { abort(); }
     virtual uint64_t getConstantPoolEntryAddress(unsigned Index) { abort(); }
     virtual uint64_t getCurrentPCValue() { abort(); }
     virtual uint64_t forceCompilationOf(Function *F) { abort(); }

   private:
     std::ostream& O;
     std::ios::fmtflags OldFlags;
     bool firstByte;
   };

   struct X86AsmPrinter : public AsmPrinter {
     X86AsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) { }

     virtual const char *getPassName() const {
       return "X86 Assembly Printer";
     }

     /// printInstruction - This method is automatically generated by tablegen
     /// from the instruction set description.  This method returns true if the
     /// machine instruction was sufficiently described to print it, otherwise it
     /// returns false.
     bool printInstruction(const MachineInstr *MI);

     // This method is used by the tablegen'erated instruction printer.
     void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
       const MachineOperand &MO = MI->getOperand(OpNo);
       if (MO.getType() == MachineOperand::MO_MachineRegister) {
         assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
         // Bug Workaround: See note in Printer::doInitialization about %.
         O << "%" << TM.getRegisterInfo()->get(MO.getReg()).Name;
       } else {
         printOp(MO);
       }
     }

     void printCallOperand(const MachineInstr *MI, unsigned OpNo,
                           MVT::ValueType VT) {
       printOp(MI->getOperand(OpNo), true); // Don't print "OFFSET".
     }

     void printMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                             MVT::ValueType VT) {
       switch (VT) {
       default: assert(0 && "Unknown arg size!");
       case MVT::i8:   O << "BYTE PTR "; break;
       case MVT::i16:  O << "WORD PTR "; break;
       case MVT::i32:
       case MVT::f32:  O << "DWORD PTR "; break;
       case MVT::i64:
       case MVT::f64:  O << "QWORD PTR "; break;
       case MVT::f80:  O << "XWORD PTR "; break;
       }
       printMemReference(MI, OpNo);
     }

     void printMachineInstruction(const MachineInstr *MI);
     void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
     void printMemReference(const MachineInstr *MI, unsigned Op);
     void printConstantPool(MachineConstantPool *MCP);
     bool runOnMachineFunction(MachineFunction &F);
     bool doInitialization(Module &M);
     bool doFinalization(Module &M);
     void emitGlobalConstant(const Constant* CV);
   };
 } // end of anonymous namespace

 /// createX86CodePrinterPass - Returns a pass that prints the X86
 /// assembly code for a MachineFunction to the given output stream,
 /// using the given target machine description.  This should work
 /// regardless of whether the function is in SSA form.
 ///
 FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
   return new X86AsmPrinter(o, tm);
 }


 // Include the auto-generated portion of the assembly writer.
 #include "X86GenAsmWriter.inc"


 /// toOctal - Convert the low order bits of X into an octal digit.
 ///
 static inline char toOctal(int X) {
   return (X&7)+'0';
 }

 /// getAsCString - Return the specified array as a C compatible
 /// string, only if the predicate isStringCompatible is true.
 ///
 static void printAsCString(std::ostream &O, const ConstantArray *CVA) {
   assert(CVA->isString() && "Array is not string compatible!");

   O << "\"";
   for (unsigned i = 0; i != CVA->getNumOperands(); ++i) {
     unsigned char C = cast<ConstantInt>(CVA->getOperand(i))->getRawValue();

     if (C == '"') {
       O << "\\\"";
     } else if (C == '\\') {
       O << "\\\\";
     } else if (isprint(C)) {
       O << C;
     } else {
       switch(C) {
       case '\b': O << "\\b"; break;
       case '\f': O << "\\f"; break;
       case '\n': O << "\\n"; break;
       case '\r': O << "\\r"; break;
       case '\t': O << "\\t"; break;
       default:
         O << '\\';
         O << toOctal(C >> 6);
         O << toOctal(C >> 3);
         O << toOctal(C >> 0);
         break;
       }
     }
   }
   O << "\"";
 }

 // Print a constant value or values, with the appropriate storage class as a
 // prefix.
 void X86AsmPrinter::emitGlobalConstant(const Constant *CV) {
   const TargetData &TD = TM.getTargetData();

   if (CV->isNullValue()) {
     O << "\t.zero\t " << TD.getTypeSize(CV->getType()) << "\n";
     return;
   } else if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) {
     if (CVA->isString()) {
       O << "\t.ascii\t";
       printAsCString(O, CVA);
       O << "\n";
     } else { // Not a string.  Print the values in successive locations
       for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i)
         emitGlobalConstant(CVA->getOperand(i));
     }
     return;
   } else if (const ConstantStruct *CVS = dyn_cast<ConstantStruct>(CV)) {
     // Print the fields in successive locations. Pad to align if needed!
     const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType());
     unsigned sizeSoFar = 0;
     for (unsigned i = 0, e = CVS->getNumOperands(); i != e; ++i) {
       const Constant* field = CVS->getOperand(i);

       // Check if padding is needed and insert one or more 0s.
       unsigned fieldSize = TD.getTypeSize(field->getType());
       unsigned padSize = ((i == e-1? cvsLayout->StructSize
                            : cvsLayout->MemberOffsets[i+1])
                           - cvsLayout->MemberOffsets[i]) - fieldSize;
       sizeSoFar += fieldSize + padSize;

       // Now print the actual field value
       emitGlobalConstant(field);

       // Insert the field padding unless it's zero bytes...
       if (padSize)
         O << "\t.zero\t " << padSize << "\n";
     }
     assert(sizeSoFar == cvsLayout->StructSize &&
            "Layout of constant struct may be incorrect!");
     return;
   } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
     // FP Constants are printed as integer constants to avoid losing
     // precision...
     double Val = CFP->getValue();
     switch (CFP->getType()->getTypeID()) {
     default: assert(0 && "Unknown floating point type!");
     case Type::FloatTyID: {
       union FU {                            // Abide by C TBAA rules
         float FVal;
         unsigned UVal;
       } U;
       U.FVal = Val;
       O << ".long\t" << U.UVal << "\t# float " << Val << "\n";
       return;
     }
     case Type::DoubleTyID: {
       union DU {                            // Abide by C TBAA rules
         double FVal;
         uint64_t UVal;
       } U;
       U.FVal = Val;
       O << ".quad\t" << U.UVal << "\t# double " << Val << "\n";
       return;
     }
     }
   }

   const Type *type = CV->getType();
   O << "\t";
   switch (type->getTypeID()) {
   case Type::BoolTyID: case Type::UByteTyID: case Type::SByteTyID:
     O << ".byte";
     break;
   case Type::UShortTyID: case Type::ShortTyID:
     O << ".word";
     break;
   case Type::FloatTyID: case Type::PointerTyID:
   case Type::UIntTyID: case Type::IntTyID:
     O << ".long";
     break;
   case Type::DoubleTyID:
   case Type::ULongTyID: case Type::LongTyID:
     O << ".quad";
     break;
   default:
     assert (0 && "Can't handle printing this type of thing");
     break;
   }
   O << "\t";
   emitConstantValueOnly(CV);
   O << "\n";
 }

 /// printConstantPool - Print to the current output stream assembly
 /// representations of the constants in the constant pool MCP. This is
 /// used to print out constants which have been "spilled to memory" by
 /// the code generator.
 ///
 void X86AsmPrinter::printConstantPool(MachineConstantPool *MCP) {
   const std::vector<Constant*> &CP = MCP->getConstants();
   const TargetData &TD = TM.getTargetData();

   if (CP.empty()) return;

   for (unsigned i = 0, e = CP.size(); i != e; ++i) {
     O << "\t.section .rodata\n";
     O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType())
       << "\n";
     O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t#"
       << *CP[i] << "\n";
     emitGlobalConstant(CP[i]);
   }
 }

 /// runOnMachineFunction - This uses the printMachineInstruction()
 /// method to print assembly for each instruction.
 ///
 bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   setupMachineFunction(MF);
   O << "\n\n";

   // Print out constants referenced by the function
   printConstantPool(MF.getConstantPool());

   // Print out labels for the function.
   O << "\t.text\n";
   O << "\t.align 16\n";
   O << "\t.globl\t" << CurrentFnName << "\n";
   O << "\t.type\t" << CurrentFnName << ", @function\n";
   O << CurrentFnName << ":\n";

   // Print out code for the function.
   for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
        I != E; ++I) {
     // Print a label for the basic block.
     O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t# "
       << I->getBasicBlock()->getName() << "\n";
     for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
          II != E; ++II) {
       // Print the assembly for the instruction.
       O << "\t";
       printMachineInstruction(II);
     }
   }

   // We didn't modify anything.
   return false;
 }

 static bool isScale(const MachineOperand &MO) {
   return MO.isImmediate() &&
     (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
      MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
 }

 static bool isMem(const MachineInstr *MI, unsigned Op) {
   if (MI->getOperand(Op).isFrameIndex()) return true;
   if (MI->getOperand(Op).isConstantPoolIndex()) return true;
   return Op+4 <= MI->getNumOperands() &&
     MI->getOperand(Op  ).isRegister() && isScale(MI->getOperand(Op+1)) &&
     MI->getOperand(Op+2).isRegister() && MI->getOperand(Op+3).isImmediate();
 }


 void X86AsmPrinter::printOp(const MachineOperand &MO,
                             bool elideOffsetKeyword /* = false */) {
   const MRegisterInfo &RI = *TM.getRegisterInfo();
   switch (MO.getType()) {
   case MachineOperand::MO_VirtualRegister:
     if (Value *V = MO.getVRegValueOrNull()) {
       O << "<" << V->getName() << ">";
       return;
     }
     // FALLTHROUGH
   case MachineOperand::MO_MachineRegister:
     if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
       // Bug Workaround: See note in Printer::doInitialization about %.
       O << "%" << RI.get(MO.getReg()).Name;
     else
       O << "%reg" << MO.getReg();
     return;

   case MachineOperand::MO_SignExtendedImmed:
   case MachineOperand::MO_UnextendedImmed:
     O << (int)MO.getImmedValue();
     return;
   case MachineOperand::MO_MachineBasicBlock: {
     MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
     O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
       << "_" << MBBOp->getNumber () << "\t# "
       << MBBOp->getBasicBlock ()->getName ();
     return;
   }
   case MachineOperand::MO_PCRelativeDisp:
     std::cerr << "Shouldn't use addPCDisp() when building X86 MachineInstrs";
     abort ();
     return;
   case MachineOperand::MO_GlobalAddress:
     if (!elideOffsetKeyword)
       O << "OFFSET ";
     O << Mang->getValueName(MO.getGlobal());
     return;
   case MachineOperand::MO_ExternalSymbol:
     O << MO.getSymbolName();
     return;
   default:
     O << "<unknown operand type>"; return;
   }
 }

 void X86AsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op) {
   assert(isMem(MI, Op) && "Invalid memory reference!");

   if (MI->getOperand(Op).isFrameIndex()) {
     O << "[frame slot #" << MI->getOperand(Op).getFrameIndex();
     if (MI->getOperand(Op+3).getImmedValue())
       O << " + " << MI->getOperand(Op+3).getImmedValue();
     O << "]";
     return;
   } else if (MI->getOperand(Op).isConstantPoolIndex()) {
     O << "[.CPI" << CurrentFnName << "_"
       << MI->getOperand(Op).getConstantPoolIndex();
     if (MI->getOperand(Op+3).getImmedValue())
       O << " + " << MI->getOperand(Op+3).getImmedValue();
     O << "]";
     return;
   }

   const MachineOperand &BaseReg  = MI->getOperand(Op);
   int ScaleVal                   = MI->getOperand(Op+1).getImmedValue();
   const MachineOperand &IndexReg = MI->getOperand(Op+2);
   int DispVal                    = MI->getOperand(Op+3).getImmedValue();

   O << "[";
   bool NeedPlus = false;
   if (BaseReg.getReg()) {
     printOp(BaseReg);
     NeedPlus = true;
   }

   if (IndexReg.getReg()) {
     if (NeedPlus) O << " + ";
     if (ScaleVal != 1)
       O << ScaleVal << "*";
     printOp(IndexReg);
     NeedPlus = true;
   }

   if (DispVal) {
     if (NeedPlus)
       if (DispVal > 0)
         O << " + ";
       else {
         O << " - ";
         DispVal = -DispVal;
       }
     O << DispVal;
   }
   O << "]";
 }


 /// printMachineInstruction -- Print out a single X86 LLVM instruction
 /// MI in Intel syntax to the current output stream.
 ///
 void X86AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
   ++EmittedInsts;

   // gas bugs:
   //
   // The 80-bit FP store-pop instruction "fstp XWORD PTR [...]"  is misassembled
   // by gas in intel_syntax mode as its 32-bit equivalent "fstp DWORD PTR
   // [...]". Workaround: Output the raw opcode bytes instead of the instruction.
   //
   // The 80-bit FP load instruction "fld XWORD PTR [...]" is misassembled by gas
   // in intel_syntax mode as its 32-bit equivalent "fld DWORD PTR
   // [...]". Workaround: Output the raw opcode bytes instead of the instruction.
   //
   // gas intel_syntax mode treats "fild QWORD PTR [...]" as an invalid opcode,
   // saying "64 bit operations are only supported in 64 bit modes." libopcodes
   // disassembles it as "fild DWORD PTR [...]", which is wrong. Workaround:
   // Output the raw opcode bytes instead of the instruction.
   //
   // gas intel_syntax mode treats "fistp QWORD PTR [...]" as an invalid opcode,
   // saying "64 bit operations are only supported in 64 bit modes." libopcodes
   // disassembles it as "fistpll DWORD PTR [...]", which is wrong. Workaround:
   // Output the raw opcode bytes instead of the instruction.
   switch (MI->getOpcode()) {
   case X86::FSTP80m:
   case X86::FLD80m:
   case X86::FILD64m:
   case X86::FISTP64m:
     GasBugWorkaroundEmitter gwe(O);
     X86::emitInstruction(gwe, (X86InstrInfo&)*TM.getInstrInfo(), *MI);
     O << "\t# ";
   }

   // Call the autogenerated instruction printer routines.
   bool Handled = printInstruction(MI);
   if (!Handled) {
     MI->dump();
     assert(0 && "Do not know how to print this instruction!");
     abort();
   }
 }

 bool X86AsmPrinter::doInitialization(Module &M) {
   AsmPrinter::doInitialization(M);
   // Tell gas we are outputting Intel syntax (not AT&T syntax) assembly.
   //
   // Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an
   // instruction as a reference to the register named sp, and if you try to
   // reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets lowercased
   // before being looked up in the symbol table. This creates spurious
   // `undefined symbol' errors when linking. Workaround: Do not use `noprefix'
   // mode, and decorate all register names with percent signs.
   O << "\t.intel_syntax\n";
   return false;
 }

 // SwitchSection - Switch to the specified section of the executable if we are
 // not already in it!
 //
 static void SwitchSection(std::ostream &OS, std::string &CurSection,
                           const char *NewSection) {
   if (CurSection != NewSection) {
     CurSection = NewSection;
     if (!CurSection.empty())
       OS << "\t" << NewSection << "\n";
   }
 }

 bool X86AsmPrinter::doFinalization(Module &M) {
   const TargetData &TD = TM.getTargetData();
   std::string CurSection;

   // Print out module-level global variables here.
   for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I)
     if (I->hasInitializer()) {   // External global require no code
       O << "\n\n";
       std::string name = Mang->getValueName(I);
       Constant *C = I->getInitializer();
       unsigned Size = TD.getTypeSize(C->getType());
       unsigned Align = TD.getTypeAlignment(C->getType());

       if (C->isNullValue() &&
           (I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
            I->hasWeakLinkage() /* FIXME: Verify correct */)) {
         SwitchSection(O, CurSection, ".data");
         if (I->hasInternalLinkage())
           O << "\t.local " << name << "\n";

         O << "\t.comm " << name << "," << TD.getTypeSize(C->getType())
           << "," << (unsigned)TD.getTypeAlignment(C->getType());
         O << "\t\t# ";
         WriteAsOperand(O, I, true, true, &M);
         O << "\n";
       } else {
         switch (I->getLinkage()) {
         case GlobalValue::LinkOnceLinkage:
         case GlobalValue::WeakLinkage:   // FIXME: Verify correct for weak.
           // Nonnull linkonce -> weak
           O << "\t.weak " << name << "\n";
           SwitchSection(O, CurSection, "");
           O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\",@progbits\n";
           break;

         case GlobalValue::AppendingLinkage:
           // FIXME: appending linkage variables should go into a section of
           // their name or something.  For now, just emit them as external.
         case GlobalValue::ExternalLinkage:
           // If external or appending, declare as a global symbol
           O << "\t.globl " << name << "\n";
           // FALL THROUGH
         case GlobalValue::InternalLinkage:
           if (C->isNullValue())
             SwitchSection(O, CurSection, ".bss");
           else
             SwitchSection(O, CurSection, ".data");
           break;
         }

         O << "\t.align " << Align << "\n";
         O << "\t.type " << name << ",@object\n";
         O << "\t.size " << name << "," << Size << "\n";
         O << name << ":\t\t\t\t# ";
         WriteAsOperand(O, I, true, true, &M);
         O << " = ";
         WriteAsOperand(O, C, false, false, &M);
         O << "\n";
         emitGlobalConstant(C);
       }
     }

   AsmPrinter::doFinalization(M);
   return false; // success
 }
	//===-- X86AsmPrinter.cpp - Convert X86 LLVM code to Intel assembly -------===//
	//
	// The LLVM Compiler Infrastructure
	//
	// This file was developed by the LLVM research group and is distributed under
	// the University of Illinois Open Source License. See LICENSE.TXT for details.
	//
	//===----------------------------------------------------------------------===//
	//
	// This file contains a printer that converts from our internal representation
	// of machine-dependent LLVM code to Intel-format assembly language. This
	// printer is the output mechanism used by `llc' and `lli -print-machineinstrs'
	// on X86.
	//
	//===----------------------------------------------------------------------===//

	#include "X86.h"
	#include "X86InstrInfo.h"
	#include "X86TargetMachine.h"
	#include "llvm/Constants.h"
	#include "llvm/DerivedTypes.h"
	#include "llvm/Module.h"
	#include "llvm/Assembly/Writer.h"
	#include "llvm/CodeGen/AsmPrinter.h"
	#include "llvm/CodeGen/MachineCodeEmitter.h"
	#include "llvm/CodeGen/MachineConstantPool.h"
	#include "llvm/CodeGen/MachineFunctionPass.h"
	#include "llvm/CodeGen/MachineInstr.h"
	#include "llvm/CodeGen/ValueTypes.h"
	#include "llvm/Target/TargetMachine.h"
	#include "llvm/Support/Mangler.h"
	#include "Support/Statistic.h"
	#include "Support/StringExtras.h"
	#include "Support/CommandLine.h"
	using namespace llvm;

	namespace {
	Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");

	struct GasBugWorkaroundEmitter : public MachineCodeEmitter {
	GasBugWorkaroundEmitter(std::ostream& o)
	: O(o), OldFlags(O.flags()), firstByte(true) {
	O << std::hex;
	}

	~GasBugWorkaroundEmitter() {
	O.flags(OldFlags);
	}

	virtual void emitByte(unsigned char B) {
	if (!firstByte) O << "\n\t";
	firstByte = false;
	O << ".byte 0x" << (unsigned) B;
	}

	// These should never be called
	virtual void emitWord(unsigned W) { assert(0); }
	virtual uint64_t getGlobalValueAddress(GlobalValue *V) { abort(); }
	virtual uint64_t getGlobalValueAddress(const std::string &Name) { abort(); }
	virtual uint64_t getConstantPoolEntryAddress(unsigned Index) { abort(); }
	virtual uint64_t getCurrentPCValue() { abort(); }
	virtual uint64_t forceCompilationOf(Function *F) { abort(); }

	private:
	std::ostream& O;
	std::ios::fmtflags OldFlags;
	bool firstByte;
	};

	struct X86AsmPrinter : public AsmPrinter {
	X86AsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) { }

	virtual const char *getPassName() const {
	return "X86 Assembly Printer";
	}

	/// printInstruction - This method is automatically generated by tablegen
	/// from the instruction set description. This method returns true if the
	/// machine instruction was sufficiently described to print it, otherwise it
	/// returns false.
	bool printInstruction(const MachineInstr *MI);

	// This method is used by the tablegen'erated instruction printer.
	void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
	const MachineOperand &MO = MI->getOperand(OpNo);
	if (MO.getType() == MachineOperand::MO_MachineRegister) {
	assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
	// Bug Workaround: See note in Printer::doInitialization about %.
	O << "%" << TM.getRegisterInfo()->get(MO.getReg()).Name;
	} else {
	printOp(MO);
	}
	}

	void printCallOperand(const MachineInstr *MI, unsigned OpNo,
	MVT::ValueType VT) {
	printOp(MI->getOperand(OpNo), true); // Don't print "OFFSET".
	}

	void printMemoryOperand(const MachineInstr *MI, unsigned OpNo,
	MVT::ValueType VT) {
	switch (VT) {
	default: assert(0 && "Unknown arg size!");
	case MVT::i8: O << "BYTE PTR "; break;
	case MVT::i16: O << "WORD PTR "; break;
	case MVT::i32:
	case MVT::f32: O << "DWORD PTR "; break;
	case MVT::i64:
	case MVT::f64: O << "QWORD PTR "; break;
	case MVT::f80: O << "XWORD PTR "; break;
	}
	printMemReference(MI, OpNo);
	}

	void printMachineInstruction(const MachineInstr *MI);
	void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
	void printMemReference(const MachineInstr *MI, unsigned Op);
	void printConstantPool(MachineConstantPool *MCP);
	bool runOnMachineFunction(MachineFunction &F);
	bool doInitialization(Module &M);
	bool doFinalization(Module &M);
	void emitGlobalConstant(const Constant* CV);
	};
	} // end of anonymous namespace

	/// createX86CodePrinterPass - Returns a pass that prints the X86
	/// assembly code for a MachineFunction to the given output stream,
	/// using the given target machine description. This should work
	/// regardless of whether the function is in SSA form.
	///
	FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
	return new X86AsmPrinter(o, tm);
	}


	// Include the auto-generated portion of the assembly writer.
	#include "X86GenAsmWriter.inc"


	/// toOctal - Convert the low order bits of X into an octal digit.
	///
	static inline char toOctal(int X) {
	return (X&7)+'0';
	}

	/// getAsCString - Return the specified array as a C compatible
	/// string, only if the predicate isStringCompatible is true.
	///
	static void printAsCString(std::ostream &O, const ConstantArray *CVA) {
	assert(CVA->isString() && "Array is not string compatible!");

	O << "\"";
	for (unsigned i = 0; i != CVA->getNumOperands(); ++i) {
	unsigned char C = cast<ConstantInt>(CVA->getOperand(i))->getRawValue();

	if (C == '"') {
	O << "\\\"";
	} else if (C == '\\') {
	O << "\\\\";
	} else if (isprint(C)) {
	O << C;
	} else {
	switch(C) {
	case '\b': O << "\\b"; break;
	case '\f': O << "\\f"; break;
	case '\n': O << "\\n"; break;
	case '\r': O << "\\r"; break;
	case '\t': O << "\\t"; break;
	default:
	O << '\\';
	O << toOctal(C >> 6);
	O << toOctal(C >> 3);
	O << toOctal(C >> 0);
	break;
	}
	}
	}
	O << "\"";
	}

	// Print a constant value or values, with the appropriate storage class as a
	// prefix.
	void X86AsmPrinter::emitGlobalConstant(const Constant *CV) {
	const TargetData &TD = TM.getTargetData();

	if (CV->isNullValue()) {
	O << "\t.zero\t " << TD.getTypeSize(CV->getType()) << "\n";
	return;
	} else if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) {
	if (CVA->isString()) {
	O << "\t.ascii\t";
	printAsCString(O, CVA);
	O << "\n";
	} else { // Not a string. Print the values in successive locations
	for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i)
	emitGlobalConstant(CVA->getOperand(i));
	}
	return;
	} else if (const ConstantStruct *CVS = dyn_cast<ConstantStruct>(CV)) {
	// Print the fields in successive locations. Pad to align if needed!
	const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType());
	unsigned sizeSoFar = 0;
	for (unsigned i = 0, e = CVS->getNumOperands(); i != e; ++i) {
	const Constant* field = CVS->getOperand(i);

	// Check if padding is needed and insert one or more 0s.
	unsigned fieldSize = TD.getTypeSize(field->getType());
	unsigned padSize = ((i == e-1? cvsLayout->StructSize
	: cvsLayout->MemberOffsets[i+1])
	- cvsLayout->MemberOffsets[i]) - fieldSize;
	sizeSoFar += fieldSize + padSize;

	// Now print the actual field value
	emitGlobalConstant(field);

	// Insert the field padding unless it's zero bytes...
	if (padSize)
	O << "\t.zero\t " << padSize << "\n";
	}
	assert(sizeSoFar == cvsLayout->StructSize &&
	"Layout of constant struct may be incorrect!");
	return;
	} else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
	// FP Constants are printed as integer constants to avoid losing
	// precision...
	double Val = CFP->getValue();
	switch (CFP->getType()->getTypeID()) {
	default: assert(0 && "Unknown floating point type!");
	case Type::FloatTyID: {
	union FU { // Abide by C TBAA rules
	float FVal;
	unsigned UVal;
	} U;
	U.FVal = Val;
	O << ".long\t" << U.UVal << "\t# float " << Val << "\n";
	return;
	}
	case Type::DoubleTyID: {
	union DU { // Abide by C TBAA rules
	double FVal;
	uint64_t UVal;
	} U;
	U.FVal = Val;
	O << ".quad\t" << U.UVal << "\t# double " << Val << "\n";
	return;
	}
	}
	}

	const Type *type = CV->getType();
	O << "\t";
	switch (type->getTypeID()) {
	case Type::BoolTyID: case Type::UByteTyID: case Type::SByteTyID:
	O << ".byte";
	break;
	case Type::UShortTyID: case Type::ShortTyID:
	O << ".word";
	break;
	case Type::FloatTyID: case Type::PointerTyID:
	case Type::UIntTyID: case Type::IntTyID:
	O << ".long";
	break;
	case Type::DoubleTyID:
	case Type::ULongTyID: case Type::LongTyID:
	O << ".quad";
	break;
	default:
	assert (0 && "Can't handle printing this type of thing");
	break;
	}
	O << "\t";
	emitConstantValueOnly(CV);
	O << "\n";
	}

	/// printConstantPool - Print to the current output stream assembly
	/// representations of the constants in the constant pool MCP. This is
	/// used to print out constants which have been "spilled to memory" by
	/// the code generator.
	///
	void X86AsmPrinter::printConstantPool(MachineConstantPool *MCP) {
	const std::vector<Constant*> &CP = MCP->getConstants();
	const TargetData &TD = TM.getTargetData();

	if (CP.empty()) return;

	for (unsigned i = 0, e = CP.size(); i != e; ++i) {
	O << "\t.section .rodata\n";
	O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType())
	<< "\n";
	O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t#"
	<< *CP[i] << "\n";
	emitGlobalConstant(CP[i]);
	}
	}

	/// runOnMachineFunction - This uses the printMachineInstruction()
	/// method to print assembly for each instruction.
	///
	bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
	setupMachineFunction(MF);
	O << "\n\n";

	// Print out constants referenced by the function
	printConstantPool(MF.getConstantPool());

	// Print out labels for the function.
	O << "\t.text\n";
	O << "\t.align 16\n";
	O << "\t.globl\t" << CurrentFnName << "\n";
	O << "\t.type\t" << CurrentFnName << ", @function\n";
	O << CurrentFnName << ":\n";

	// Print out code for the function.
	for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
	I != E; ++I) {
	// Print a label for the basic block.
	O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t# "
	<< I->getBasicBlock()->getName() << "\n";
	for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
	II != E; ++II) {
	// Print the assembly for the instruction.
	O << "\t";
	printMachineInstruction(II);
	}
	}

	// We didn't modify anything.
	return false;
	}

	static bool isScale(const MachineOperand &MO) {
	return MO.isImmediate() &&
	(MO.getImmedValue() == 1 \|\| MO.getImmedValue() == 2 \|\|
	MO.getImmedValue() == 4 \|\| MO.getImmedValue() == 8);
	}

	static bool isMem(const MachineInstr *MI, unsigned Op) {
	if (MI->getOperand(Op).isFrameIndex()) return true;
	if (MI->getOperand(Op).isConstantPoolIndex()) return true;
	return Op+4 <= MI->getNumOperands() &&
	MI->getOperand(Op ).isRegister() && isScale(MI->getOperand(Op+1)) &&
	MI->getOperand(Op+2).isRegister() && MI->getOperand(Op+3).isImmediate();
	}



	void X86AsmPrinter::printOp(const MachineOperand &MO,
	bool elideOffsetKeyword /* = false */) {
	const MRegisterInfo &RI = *TM.getRegisterInfo();
	switch (MO.getType()) {
	case MachineOperand::MO_VirtualRegister:
	if (Value *V = MO.getVRegValueOrNull()) {
	O << "<" << V->getName() << ">";
	return;
	}
	// FALLTHROUGH
	case MachineOperand::MO_MachineRegister:
	if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
	// Bug Workaround: See note in Printer::doInitialization about %.
	O << "%" << RI.get(MO.getReg()).Name;
	else
	O << "%reg" << MO.getReg();
	return;

	case MachineOperand::MO_SignExtendedImmed:
	case MachineOperand::MO_UnextendedImmed:
	O << (int)MO.getImmedValue();
	return;
	case MachineOperand::MO_MachineBasicBlock: {
	MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
	O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
	<< "_" << MBBOp->getNumber () << "\t# "
	<< MBBOp->getBasicBlock ()->getName ();
	return;
	}
	case MachineOperand::MO_PCRelativeDisp:
	std::cerr << "Shouldn't use addPCDisp() when building X86 MachineInstrs";
	abort ();
	return;
	case MachineOperand::MO_GlobalAddress:
	if (!elideOffsetKeyword)
	O << "OFFSET ";
	O << Mang->getValueName(MO.getGlobal());
	return;
	case MachineOperand::MO_ExternalSymbol:
	O << MO.getSymbolName();
	return;
	default:
	O << "<unknown operand type>"; return;
	}
	}

	void X86AsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op) {
	assert(isMem(MI, Op) && "Invalid memory reference!");

	if (MI->getOperand(Op).isFrameIndex()) {
	O << "[frame slot #" << MI->getOperand(Op).getFrameIndex();
	if (MI->getOperand(Op+3).getImmedValue())
	O << " + " << MI->getOperand(Op+3).getImmedValue();
	O << "]";
	return;
	} else if (MI->getOperand(Op).isConstantPoolIndex()) {
	O << "[.CPI" << CurrentFnName << "_"
	<< MI->getOperand(Op).getConstantPoolIndex();
	if (MI->getOperand(Op+3).getImmedValue())
	O << " + " << MI->getOperand(Op+3).getImmedValue();
	O << "]";
	return;
	}

	const MachineOperand &BaseReg = MI->getOperand(Op);
	int ScaleVal = MI->getOperand(Op+1).getImmedValue();
	const MachineOperand &IndexReg = MI->getOperand(Op+2);
	int DispVal = MI->getOperand(Op+3).getImmedValue();

	O << "[";
	bool NeedPlus = false;
	if (BaseReg.getReg()) {
	printOp(BaseReg);
	NeedPlus = true;
	}

	if (IndexReg.getReg()) {
	if (NeedPlus) O << " + ";
	if (ScaleVal != 1)
	O << ScaleVal << "*";
	printOp(IndexReg);
	NeedPlus = true;
	}

	if (DispVal) {
	if (NeedPlus)
	if (DispVal > 0)
	O << " + ";
	else {
	O << " - ";
	DispVal = -DispVal;
	}
	O << DispVal;
	}
	O << "]";
	}


	/// printMachineInstruction -- Print out a single X86 LLVM instruction
	/// MI in Intel syntax to the current output stream.
	///
	void X86AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
	++EmittedInsts;

	// gas bugs:
	//
	// The 80-bit FP store-pop instruction "fstp XWORD PTR [...]" is misassembled
	// by gas in intel_syntax mode as its 32-bit equivalent "fstp DWORD PTR
	// [...]". Workaround: Output the raw opcode bytes instead of the instruction.
	//
	// The 80-bit FP load instruction "fld XWORD PTR [...]" is misassembled by gas
	// in intel_syntax mode as its 32-bit equivalent "fld DWORD PTR
	// [...]". Workaround: Output the raw opcode bytes instead of the instruction.
	//
	// gas intel_syntax mode treats "fild QWORD PTR [...]" as an invalid opcode,
	// saying "64 bit operations are only supported in 64 bit modes." libopcodes
	// disassembles it as "fild DWORD PTR [...]", which is wrong. Workaround:
	// Output the raw opcode bytes instead of the instruction.
	//
	// gas intel_syntax mode treats "fistp QWORD PTR [...]" as an invalid opcode,
	// saying "64 bit operations are only supported in 64 bit modes." libopcodes
	// disassembles it as "fistpll DWORD PTR [...]", which is wrong. Workaround:
	// Output the raw opcode bytes instead of the instruction.
	switch (MI->getOpcode()) {
	case X86::FSTP80m:
	case X86::FLD80m:
	case X86::FILD64m:
	case X86::FISTP64m:
	GasBugWorkaroundEmitter gwe(O);
	X86::emitInstruction(gwe, (X86InstrInfo&)TM.getInstrInfo(), MI);
	O << "\t# ";
	}

	// Call the autogenerated instruction printer routines.
	bool Handled = printInstruction(MI);
	if (!Handled) {
	MI->dump();
	assert(0 && "Do not know how to print this instruction!");
	abort();
	}
	}

	bool X86AsmPrinter::doInitialization(Module &M) {
	AsmPrinter::doInitialization(M);
	// Tell gas we are outputting Intel syntax (not AT&T syntax) assembly.
	//
	// Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an
	// instruction as a reference to the register named sp, and if you try to
	// reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets lowercased
	// before being looked up in the symbol table. This creates spurious
	// `undefined symbol' errors when linking. Workaround: Do not use `noprefix'
	// mode, and decorate all register names with percent signs.
	O << "\t.intel_syntax\n";
	return false;
	}

	// SwitchSection - Switch to the specified section of the executable if we are
	// not already in it!
	//
	static void SwitchSection(std::ostream &OS, std::string &CurSection,
	const char *NewSection) {
	if (CurSection != NewSection) {
	CurSection = NewSection;
	if (!CurSection.empty())
	OS << "\t" << NewSection << "\n";
	}
	}

	bool X86AsmPrinter::doFinalization(Module &M) {
	const TargetData &TD = TM.getTargetData();
	std::string CurSection;

	// Print out module-level global variables here.
	for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I)
	if (I->hasInitializer()) { // External global require no code
	O << "\n\n";
	std::string name = Mang->getValueName(I);
	Constant *C = I->getInitializer();
	unsigned Size = TD.getTypeSize(C->getType());
	unsigned Align = TD.getTypeAlignment(C->getType());

	if (C->isNullValue() &&
	(I->hasLinkOnceLinkage() \|\| I->hasInternalLinkage() \|\|
	I->hasWeakLinkage() /* FIXME: Verify correct */)) {
	SwitchSection(O, CurSection, ".data");
	if (I->hasInternalLinkage())
	O << "\t.local " << name << "\n";

	O << "\t.comm " << name << "," << TD.getTypeSize(C->getType())
	<< "," << (unsigned)TD.getTypeAlignment(C->getType());
	O << "\t\t# ";
	WriteAsOperand(O, I, true, true, &M);
	O << "\n";
	} else {
	switch (I->getLinkage()) {
	case GlobalValue::LinkOnceLinkage:
	case GlobalValue::WeakLinkage: // FIXME: Verify correct for weak.
	// Nonnull linkonce -> weak
	O << "\t.weak " << name << "\n";
	SwitchSection(O, CurSection, "");
	O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\",@progbits\n";
	break;

	case GlobalValue::AppendingLinkage:
	// FIXME: appending linkage variables should go into a section of
	// their name or something. For now, just emit them as external.
	case GlobalValue::ExternalLinkage:
	// If external or appending, declare as a global symbol
	O << "\t.globl " << name << "\n";
	// FALL THROUGH
	case GlobalValue::InternalLinkage:
	if (C->isNullValue())
	SwitchSection(O, CurSection, ".bss");
	else
	SwitchSection(O, CurSection, ".data");
	break;
	}

	O << "\t.align " << Align << "\n";
	O << "\t.type " << name << ",@object\n";
	O << "\t.size " << name << "," << Size << "\n";
	O << name << ":\t\t\t\t# ";
	WriteAsOperand(O, I, true, true, &M);
	O << " = ";
	WriteAsOperand(O, C, false, false, &M);
	O << "\n";
	emitGlobalConstant(C);
	}
	}

	AsmPrinter::doFinalization(M);
	return false; // success
	}