Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index 6f96ff0..a602770 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -194,7 +194,7 @@
else
abort();
MachineInstrBuilder MIB =
- BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
+ BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
@@ -239,7 +239,7 @@
else
abort();
MachineInstrBuilder MIB =
- BuildMI(get(Opc), DestReg);
+ BuildMI(MF, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
@@ -272,7 +272,7 @@
bool isKill = MI->getOperand(1).isKill();
Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
- NewMI = BuildMI(get(Opc)).addReg(InReg, false, false, isKill)
+ NewMI = BuildMI(MF, get(Opc)).addReg(InReg, false, false, isKill)
.addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
} else { // load -> move
@@ -280,7 +280,7 @@
bool isDead = MI->getOperand(0).isDead();
Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
- NewMI = BuildMI(get(Opc)).addReg(OutReg, true, false, false, isDead)
+ NewMI = BuildMI(MF, get(Opc)).addReg(OutReg, true, false, false, isDead)
.addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
}