Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the
instructions take a consistent reg class. Implement ISD::UNDEF in the dag->dag
selector to generate this, fixing UnitTests/2003-07-06-IntOverflow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23028 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 4e753d1..22082a4 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -830,7 +830,10 @@
Node->dump(); std::cerr << '\n';
assert(0 && "Node not handled!\n");
case ISD::UNDEF:
- BuildMI(BB, PPC::IMPLICIT_DEF, 0, Result);
+ if (Node->getValueType(0) == MVT::i32)
+ BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Result);
+ else
+ BuildMI(BB, PPC::IMPLICIT_DEF_FP, 0, Result);
return Result;
case ISD::DYNAMIC_STACKALLOC:
// Generate both result values. FIXME: Need a better commment here?
@@ -1872,8 +1875,11 @@
return;
case ISD::ImplicitDef:
Select(N.getOperand(0));
- BuildMI(BB, PPC::IMPLICIT_DEF, 0,
- cast<RegisterSDNode>(N.getOperand(1))->getReg());
+ Tmp1 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
+ if (N.getOperand(1).getValueType() == MVT::i32)
+ BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Tmp1);
+ else
+ BuildMI(BB, PPC::IMPLICIT_DEF_FP, 0, Tmp1);
return;
case ISD::RET:
switch (N.getNumOperands()) {