commit 31e874490a259a19c31c4dad9ee3365ea2c0cd8f
author Anton Korobeynikov <asl@math.spbu.ru> Sat Jul 18 13:33:17 2009 +0000
committer Anton Korobeynikov <asl@math.spbu.ru> Sat Jul 18 13:33:17 2009 +0000
tree 583b4fe2b09be784dae89f55fa4d65a49fc11c41
parent 87e412b92189a87f2850688ebd77d275fd579980

Turn few asserts into errors / unreachable's

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76313 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/SystemZ/SystemZInstrInfo.cpp

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 27bd47d..b7dfab5 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -81,7 +81,7 @@
   } else if (RC == &SystemZ::GR128RegClass) {
     Opc = SystemZ::MOV128mr;
   } else
-    assert(0 && "Unsupported regclass to store");
+    llvm_unreachable("Unsupported regclass to store");
 
   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
     .addReg(SrcReg, getKillRegState(isKill));
@@ -110,7 +110,7 @@
   } else if (RC == &SystemZ::GR128RegClass) {
     Opc = SystemZ::MOV128rm;
   } else
-    assert(0 && "Unsupported regclass to load");
+    llvm_unreachable("Unsupported regclass to load");
 
   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
 }
@@ -584,7 +584,7 @@
 SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
   switch (CC) {
   default:
-    assert(0 && "Unknown condition code!");
+   llvm_unreachable("Unknown condition code!");
   case SystemZCC::O:   return get(SystemZ::JO);
   case SystemZCC::H:   return get(SystemZ::JH);
   case SystemZCC::NLE: return get(SystemZ::JNLE);
@@ -627,7 +627,7 @@
 SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const {
   switch (CC) {
   default:
-   assert(0 && "Invalid condition!");
+    llvm_unreachable("Invalid condition!");
   case SystemZCC::O:   return SystemZCC::NO;
   case SystemZCC::H:   return SystemZCC::NH;
   case SystemZCC::NLE: return SystemZCC::LE;
@@ -649,7 +649,7 @@
 SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
   switch (Opc) {
   default:
-   assert(0 && "Don't have long disp version of this instruction");
+    llvm_unreachable("Don't have long disp version of this instruction");
   case SystemZ::MOV32mr:   return get(SystemZ::MOV32mry);
   case SystemZ::MOV32rm:   return get(SystemZ::MOV32rmy);
   case SystemZ::MOVSX32rm16: return get(SystemZ::MOVSX32rm16y);