Rename MachineInstrInfo -> TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/FloatingPoint.cpp b/lib/Target/X86/FloatingPoint.cpp
index 7fdd97f..aac3fbc 100644
--- a/lib/Target/X86/FloatingPoint.cpp
+++ b/lib/Target/X86/FloatingPoint.cpp
@@ -10,7 +10,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include <algorithm>
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp
index 43f2532..ee8318f 100644
--- a/lib/Target/X86/InstSelectSimple.cpp
+++ b/lib/Target/X86/InstSelectSimple.cpp
@@ -437,7 +437,7 @@
/// the current one.
///
void ISel::SelectPHINodes() {
- const MachineInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &TII = TM.getInstrInfo();
const Function &LF = *F->getFunction(); // The LLVM function...
for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
const BasicBlock *BB = I;
@@ -468,7 +468,7 @@
//
MachineBasicBlock::iterator PI = PredMBB->end();
while (PI != PredMBB->begin() &&
- MII.isTerminatorInstr((*(PI-1))->getOpcode()))
+ TII.isTerminatorInstr((*(PI-1))->getOpcode()))
--PI;
unsigned ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI);
PhiMI->addRegOperand(ValReg);
diff --git a/lib/Target/X86/MachineCodeEmitter.cpp b/lib/Target/X86/MachineCodeEmitter.cpp
index 1e2ce9d..5721d4b 100644
--- a/lib/Target/X86/MachineCodeEmitter.cpp
+++ b/lib/Target/X86/MachineCodeEmitter.cpp
@@ -220,7 +220,7 @@
}
}
-unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
+unsigned sizeOfPtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
case X86II::Arg8: return 1;
case X86II::Arg16: return 2;
@@ -236,7 +236,7 @@
void Emitter::emitInstruction(MachineInstr &MI) {
unsigned Opcode = MI.getOpcode();
- const MachineInstrDescriptor &Desc = II->get(Opcode);
+ const TargetInstrDescriptor &Desc = II->get(Opcode);
// Emit instruction prefixes if neccesary
if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
diff --git a/lib/Target/X86/Printer.cpp b/lib/Target/X86/Printer.cpp
index b71f3f2..95e8642 100644
--- a/lib/Target/X86/Printer.cpp
+++ b/lib/Target/X86/Printer.cpp
@@ -59,7 +59,7 @@
bool Printer::runOnMachineFunction(MachineFunction &MF) {
static unsigned BBNumber = 0;
const TargetMachine &TM = MF.getTarget();
- const MachineInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &TII = TM.getInstrInfo();
// Print out constants referenced by the function
printConstantPool(MF.getConstantPool(), TM.getTargetData());
@@ -80,7 +80,7 @@
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
- MII.print(*II, O, TM);
+ TII.print(*II, O, TM);
}
}
@@ -136,7 +136,7 @@
}
}
-static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
+static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
default: assert(0 && "Unknown arg size!");
case X86II::Arg8: return "BYTE PTR";
@@ -204,7 +204,7 @@
void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const {
unsigned Opcode = MI->getOpcode();
- const MachineInstrDescriptor &Desc = get(Opcode);
+ const TargetInstrDescriptor &Desc = get(Opcode);
switch (Desc.TSFlags & X86II::FormMask) {
case X86II::Pseudo:
diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp
index b71f3f2..95e8642 100644
--- a/lib/Target/X86/X86AsmPrinter.cpp
+++ b/lib/Target/X86/X86AsmPrinter.cpp
@@ -59,7 +59,7 @@
bool Printer::runOnMachineFunction(MachineFunction &MF) {
static unsigned BBNumber = 0;
const TargetMachine &TM = MF.getTarget();
- const MachineInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &TII = TM.getInstrInfo();
// Print out constants referenced by the function
printConstantPool(MF.getConstantPool(), TM.getTargetData());
@@ -80,7 +80,7 @@
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
- MII.print(*II, O, TM);
+ TII.print(*II, O, TM);
}
}
@@ -136,7 +136,7 @@
}
}
-static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
+static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
default: assert(0 && "Unknown arg size!");
case X86II::Arg8: return "BYTE PTR";
@@ -204,7 +204,7 @@
void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const {
unsigned Opcode = MI->getOpcode();
- const MachineInstrDescriptor &Desc = get(Opcode);
+ const TargetInstrDescriptor &Desc = get(Opcode);
switch (Desc.TSFlags & X86II::FormMask) {
case X86II::Pseudo:
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index 1e2ce9d..5721d4b 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -220,7 +220,7 @@
}
}
-unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
+unsigned sizeOfPtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
case X86II::Arg8: return 1;
case X86II::Arg16: return 2;
@@ -236,7 +236,7 @@
void Emitter::emitInstruction(MachineInstr &MI) {
unsigned Opcode = MI.getOpcode();
- const MachineInstrDescriptor &Desc = II->get(Opcode);
+ const TargetInstrDescriptor &Desc = II->get(Opcode);
// Emit instruction prefixes if neccesary
if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 7fdd97f..aac3fbc 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -10,7 +10,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include <algorithm>
diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index 43f2532..ee8318f 100644
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -437,7 +437,7 @@
/// the current one.
///
void ISel::SelectPHINodes() {
- const MachineInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &TII = TM.getInstrInfo();
const Function &LF = *F->getFunction(); // The LLVM function...
for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
const BasicBlock *BB = I;
@@ -468,7 +468,7 @@
//
MachineBasicBlock::iterator PI = PredMBB->end();
while (PI != PredMBB->begin() &&
- MII.isTerminatorInstr((*(PI-1))->getOpcode()))
+ TII.isTerminatorInstr((*(PI-1))->getOpcode()))
--PI;
unsigned ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI);
PhiMI->addRegOperand(ValReg);
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 813d983..6b2fd64 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1,6 +1,6 @@
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
//
-// This file contains the X86 implementation of the MachineInstrInfo class.
+// This file contains the X86 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
@@ -17,7 +17,7 @@
// X86Insts - Turn the InstrInfo.def file into a bunch of instruction
// descriptors
//
-static const MachineInstrDescriptor X86Insts[] = {
+static const TargetInstrDescriptor X86Insts[] = {
#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPUSES, IMPDEFS) \
{ NAME, \
-1, /* Always vararg */ \
@@ -35,7 +35,7 @@
};
X86InstrInfo::X86InstrInfo()
- : MachineInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
+ : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
}
diff --git a/lib/Target/X86/X86InstrInfo.def b/lib/Target/X86/X86InstrInfo.def
index 8528932..9d45d3b 100644
--- a/lib/Target/X86/X86InstrInfo.def
+++ b/lib/Target/X86/X86InstrInfo.def
@@ -51,7 +51,7 @@
// #2: Opcode name, as used by the gnu assembler
// #3: The base opcode for the instruction
// #4: Instruction Flags - This should be a field or'd together that contains
-// constants from the MachineInstrInfo.h file.
+// constants from the TargetInstrInfo.h file.
// #5: Target Specific Flags - Another bitfield containing X86 specific flags
// that we are interested in for each instruction. These should be flags
// defined in X86InstrInfo.h in the X86II namespace.
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index 022c2d1..593fc0e 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -1,13 +1,13 @@
//===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===//
//
-// This file contains the X86 implementation of the MachineInstrInfo class.
+// This file contains the X86 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef X86INSTRUCTIONINFO_H
#define X86INSTRUCTIONINFO_H
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "X86RegisterInfo.h"
/// X86II - This namespace holds all of the target specific flags that
@@ -137,12 +137,12 @@
};
}
-class X86InstrInfo : public MachineInstrInfo {
+class X86InstrInfo : public TargetInstrInfo {
const X86RegisterInfo RI;
public:
X86InstrInfo();
- /// getRegisterInfo - MachineInstrInfo is a superset of MRegister info. As
+ /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///