commit 46df4eb46e784036cf895db271fe29e1cf2a975a
author Evan Cheng <evan.cheng@apple.com> Wed Jun 16 07:35:02 2010 +0000
committer Evan Cheng <evan.cheng@apple.com> Wed Jun 16 07:35:02 2010 +0000
tree 7a7225e258b7af507f92aec209f538b3bcf78671
parent ffd33cd36494cf29a0b0c80f00ed1a51b599b31f

Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMISelLowering.cpp

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 1a35f6f..78ce2f0 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -62,6 +62,11 @@
   cl::desc("Generate calls via indirect call instructions."),
   cl::init(false));
 
+static cl::opt<bool>
+ARMInterworking("arm-interworking", cl::Hidden,
+  cl::desc("Enable / disable ARM interworking (for debugging only)"),
+  cl::init(true));
+
 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
                                    CCValAssign::LocInfo &LocInfo,
                                    ISD::ArgFlagsTy &ArgFlags,
@@ -1188,7 +1193,7 @@
                    getTargetMachine().getRelocationModel() != Reloc::Static;
     isARMFunc = !Subtarget->isThumb() || isStub;
     // ARM call to a local ARM function is predicable.
-    isLocalARMFunc = !Subtarget->isThumb() && !isExt;
+    isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
     // tBX takes a register source operand.
     if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
       unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();

lib/Target/ARM/ARMTargetMachine.cpp

diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index 4ec26db..2101da8 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -27,6 +27,11 @@
   cl::desc("Form IT blocks early before register allocation"),
   cl::init(false));
 
+static cl::opt<bool>
+EarlyIfConvert("arm-early-if-convert", cl::Hidden,
+  cl::desc("Run if-conversion before post-ra scheduling"),
+  cl::init(false));
+
 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
   Triple TheTriple(TT);
   switch (TheTriple.getOS()) {
@@ -125,13 +130,17 @@
   // proper scheduling.
   PM.add(createARMExpandPseudoPass());
 
+  if (EarlyIfConvert && OptLevel != CodeGenOpt::None) {
+    if (!Subtarget.isThumb1Only()) 
+      PM.add(createIfConverterPass());
+  }
+
   return true;
 }
 
 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
                                           CodeGenOpt::Level OptLevel) {
-  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
-  if (OptLevel != CodeGenOpt::None) {
+  if (!EarlyIfConvert && OptLevel != CodeGenOpt::None) {
     if (!Subtarget.isThumb1Only())
       PM.add(createIfConverterPass());
   }