Encode the register list operands for ARM mode LDM/STM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 8693ec3..b74fa73 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -98,6 +98,9 @@
unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const;
+ unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const;
+
+
unsigned getNumFixupKinds() const {
assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
return 0;
@@ -285,6 +288,18 @@
return lsb | (msb << 5);
}
+unsigned ARMMCCodeEmitter::getRegisterListOpValue(const MCInst &MI,
+ unsigned Op) const {
+ // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
+ // register in the list, set the corresponding bit.
+ unsigned Binary = 0;
+ for (unsigned i = Op; i < MI.getNumOperands(); ++i) {
+ unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
+ Binary |= 1 << regno;
+ }
+ return Binary;
+}
+
void ARMMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {