Split RegisterAllocation stuff OUT of Sparc.cpp into a well defined pass
that has a very minimal interface (like it should have).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1667 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 61a2019..6ba63e3 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -10,6 +10,7 @@
// 9/10/01 - Ruchira Sasanka - created.
//**************************************************************************/
+#include "llvm/CodeGen/RegisterAllocation.h"
#include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForMethod.h"
@@ -23,8 +24,6 @@
// ***TODO: There are several places we add instructions. Validate the order
// of adding these instructions.
-
-
cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
"enable register allocation debugging information",
clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
@@ -32,6 +31,22 @@
clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
+bool RegisterAllocation::runOnMethod(Method *M) {
+ if (DEBUG_RA)
+ cerr << "\n******************** Method "<< M->getName()
+ << " ********************\n";
+
+ MethodLiveVarInfo LVI(M ); // Analyze live varaibles
+ LVI.analyze();
+
+ PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
+ PRA.allocateRegisters();
+
+ if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
+ return false;
+}
+
+
//----------------------------------------------------------------------------
// Constructor: Init local composite objects and create register classes.
//----------------------------------------------------------------------------
diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
index 2476a5f..8ca947a 100644
--- a/lib/Target/SparcV9/SparcV9TargetMachine.cpp
+++ b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
@@ -16,7 +16,7 @@
#include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineCodeForMethod.h"
-#include "llvm/CodeGen/PhyRegAlloc.h"
+#include "llvm/CodeGen/RegisterAllocation.h"
#include "llvm/Method.h"
#include "llvm/PassManager.h"
#include <iostream>
@@ -40,32 +40,6 @@
TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
-//----------------------------------------------------------------------------
-// Entry point for register allocation for a module
-//----------------------------------------------------------------------------
-
-class RegisterAllocation : public MethodPass {
- TargetMachine &Target;
-public:
- inline RegisterAllocation(TargetMachine &T) : Target(T) {}
- bool runOnMethod(Method *M) {
- if (DEBUG_RA)
- cerr << "\n******************** Method "<< M->getName()
- << " ********************\n";
-
- MethodLiveVarInfo LVI(M ); // Analyze live varaibles
- LVI.analyze();
-
- PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
- PRA.allocateRegisters();
-
- if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
- return false;
- }
-};
-
-static MachineInstr* minstrVec[MAX_INSTR_PER_VMINSTR];
-
//---------------------------------------------------------------------------
// class InsertPrologEpilogCode
//
@@ -77,6 +51,7 @@
// with the leaf method optimization.
//
//---------------------------------------------------------------------------
+static MachineInstr* minstrVec[MAX_INSTR_PER_VMINSTR];
class InsertPrologEpilogCode : public MethodPass {
TargetMachine &Target;