commit 73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42
author Evan Cheng <evan.cheng@apple.com> Mon Jun 27 18:32:37 2011 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Jun 27 18:32:37 2011 +0000
tree 2fbec79bd4724de8e90eec820cb0f789b03d203e
parent 4ef4c171dba8e479f5f3fe7acb22e9fe97a4d6f8

Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/TableGen.cpp

diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index b11ef6f..6f220c9 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -54,7 +54,7 @@
 enum ActionType {
   PrintRecords,
   GenEmitter,
-  GenRegisterEnums, GenRegisterDesc, GenRegisterInfo, GenRegisterInfoHeader,
+  GenRegisterInfo,
   GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
   GenARMDecoder,
   GenDisassembler,
@@ -93,14 +93,8 @@
                                "Print all records to stdout (default)"),
                     clEnumValN(GenEmitter, "gen-emitter",
                                "Generate machine code emitter"),
-                    clEnumValN(GenRegisterEnums, "gen-register-enums",
-                               "Generate enum values for registers"),
-                    clEnumValN(GenRegisterDesc, "gen-register-desc",
-                               "Generate register descriptions"),
                     clEnumValN(GenRegisterInfo, "gen-register-info",
-                               "Generate registers & reg-classes info"),
-                    clEnumValN(GenRegisterInfoHeader, "gen-register-info-header",
-                               "Generate registers & reg-classes info header"),
+                               "Generate registers and register classes info"),
                     clEnumValN(GenInstrEnums, "gen-instr-enums",
                                "Generate enum values for instructions"),
                     clEnumValN(GenInstrs, "gen-instr-desc",
@@ -263,18 +257,9 @@
     case GenEmitter:
       CodeEmitterGen(Records).run(Out.os());
       break;
-    case GenRegisterEnums:
-      RegisterInfoEmitter(Records).runEnums(Out.os());
-      break;
-    case GenRegisterDesc:
-      RegisterInfoEmitter(Records).runDesc(Out.os());
-      break;
     case GenRegisterInfo:
       RegisterInfoEmitter(Records).run(Out.os());
       break;
-    case GenRegisterInfoHeader:
-      RegisterInfoEmitter(Records).runHeader(Out.os());
-      break;
     case GenInstrEnums:
       InstrEnumEmitter(Records).run(Out.os());
       break;