rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 62d4da4..2105f14 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -55,7 +55,7 @@
void emitInstruction(const MachineInstr &MI);
int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);
- unsigned getBaseOpcodeFor(const TargetInstrDescriptor *TID);
+ unsigned getBaseOpcodeFor(const TargetInstrDesc &TID);
unsigned getBinaryCodeForInstr(const MachineInstr &MI);
void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
@@ -103,8 +103,8 @@
}
/// getBaseOpcodeFor - Return the opcode value
-unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) {
- return (TID->TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
+unsigned Emitter::getBaseOpcodeFor(const TargetInstrDesc &TID) {
+ return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
}
/// getShiftOp - Verify which is the shift opcode (bit[6:5]) of the
@@ -201,15 +201,15 @@
}
unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
- const TargetInstrDescriptor *Desc = MI.getDesc();
- unsigned opcode = Desc->Opcode;
+ const TargetInstrDesc &Desc = MI.getDesc();
+ unsigned opcode = Desc.Opcode;
// initial instruction mask
unsigned Value = 0xE0000000;
unsigned op;
- switch (Desc->TSFlags & ARMII::AddrModeMask) {
+ switch (Desc.TSFlags & ARMII::AddrModeMask) {
case ARMII::AddrModeNone: {
- switch(Desc->TSFlags & ARMII::FormMask) {
+ switch(Desc.TSFlags & ARMII::FormMask) {
default: {
assert(0 && "Unknown instruction subtype!");
// treat special instruction CLZ
@@ -241,7 +241,7 @@
unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
Value |= BaseOpcode << 4;
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = (Desc.TSFlags & ARMII::FormMask);
if (Format == ARMII::MulSMUL)
Value |= 1 << 22;
@@ -342,7 +342,7 @@
// treat 3 special instructions: MOVsra_flag, MOVsrl_flag and
// MOVrx.
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = Desc.TSFlags & ARMII::FormMask;
if (Format == ARMII::DPRdMisc) {
Value |= getMachineOpValue(MI,0) << ARMII::RegRdShift;
Value |= getMachineOpValue(MI,1);
@@ -499,7 +499,7 @@
// bit 26 is always 1
Value |= 1 << 26;
- unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
+ unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
// if the instruction uses offset addressing or pre-indexed addressing,
// set bit P(24) to 1
if (Index == ARMII::IndexModePre || Index == 0)
@@ -508,7 +508,7 @@
if (Index == ARMII::IndexModePre)
Value |= 1 << 21;
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = Desc.TSFlags & ARMII::FormMask;
// If it is a load instruction (except LDRD), set bit L(20) to 1
if (Format == ARMII::LdFrm)
Value |= 1 << ARMII::L_BitShift;
@@ -555,14 +555,13 @@
break;
}
case ARMII::AddrMode3: {
-
- unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
+ unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
// if the instruction uses offset addressing or pre-indexed addressing,
// set bit P(24) to 1
if (Index == ARMII::IndexModePre || Index == 0)
Value |= 1 << ARMII::IndexShift;
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = Desc.TSFlags & ARMII::FormMask;
// If it is a load instruction (except LDRD), set bit L(20) to 1
if (Format == ARMII::LdFrm && opcode != ARM::LDRD)
Value |= 1 << ARMII::L_BitShift;
@@ -607,7 +606,7 @@
// bit 27 is always 1
Value |= 1 << 27;
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = Desc.TSFlags & ARMII::FormMask;
// if it is a load instr, set bit L(20) to 1
if (Format == ARMII::LdFrm)
Value |= 1 << ARMII::L_BitShift;
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index 5f54e1f..ea1ee9e 100644
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -371,7 +371,7 @@
MBBSize += ARM::GetInstSize(I);
int Opc = I->getOpcode();
- if (I->getDesc()->isBranch()) {
+ if (I->getDesc().isBranch()) {
bool isCond = false;
unsigned Bits = 0;
unsigned Scale = 1;
@@ -423,7 +423,7 @@
// Basic size info comes from the TSFlags field.
unsigned Bits = 0;
unsigned Scale = 1;
- unsigned TSFlags = I->getDesc()->TSFlags;
+ unsigned TSFlags = I->getDesc().TSFlags;
switch (TSFlags & ARMII::AddrModeMask) {
default:
// Constant pool entries can reach anything.
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 2e9d802..513f9ec 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -63,7 +63,7 @@
return true;
case ARM::MOVr:
case ARM::tMOVr:
- assert(MI.getDesc()->getNumOperands() >= 2 &&
+ assert(MI.getDesc().getNumOperands() >= 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"Invalid ARM MOV instruction");
@@ -180,7 +180,7 @@
return NULL;
MachineInstr *MI = MBBI;
- unsigned TSFlags = MI->getDesc()->TSFlags;
+ unsigned TSFlags = MI->getDesc().TSFlags;
bool isPre = false;
switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
default: return NULL;
@@ -200,9 +200,9 @@
MachineInstr *UpdateMI = NULL;
MachineInstr *MemMI = NULL;
unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
- const TargetInstrDescriptor *TID = MI->getDesc();
- unsigned NumOps = TID->getNumOperands();
- bool isLoad = TID->isSimpleLoad();
+ const TargetInstrDesc &TID = MI->getDesc();
+ unsigned NumOps = TID.getNumOperands();
+ bool isLoad = TID.isSimpleLoad();
const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
const MachineOperand &Base = MI->getOperand(2);
const MachineOperand &Offset = MI->getOperand(NumOps-3);
@@ -837,8 +837,8 @@
bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const {
- const TargetInstrDescriptor *TID = MI->getDesc();
- if (!TID->getImplicitDefs() && !TID->hasOptionalDef())
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
return false;
bool Found = false;
@@ -870,8 +870,8 @@
const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
// Basic size info comes from the TSFlags field.
- const TargetInstrDescriptor *TID = MI->getDesc();
- unsigned TSFlags = TID->TSFlags;
+ const TargetInstrDesc &TID = MI->getDesc();
+ unsigned TSFlags = TID.TSFlags;
switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
default:
@@ -897,9 +897,9 @@
case ARM::tBR_JTr: {
// These are jumptable branches, i.e. a branch followed by an inlined
// jumptable. The size is 4 + 4 * number of entries.
- unsigned NumOps = TID->getNumOperands();
+ unsigned NumOps = TID.getNumOperands();
MachineOperand JTOP =
- MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
+ MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
unsigned JTI = JTOP.getIndex();
MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 29da83d..347ed8b 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -599,8 +599,8 @@
unsigned Base = MBBI->getOperand(1).getReg();
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
- const TargetInstrDescriptor *TID = MBBI->getDesc();
- unsigned OffField = MBBI->getOperand(TID->getNumOperands()-3).getImm();
+ unsigned NumOperands = MBBI->getDesc().getNumOperands();
+ unsigned OffField = MBBI->getOperand(NumOperands-3).getImm();
int Offset = isAM2
? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
if (isAM2) {
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index fc72132..01d0841 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -581,7 +581,7 @@
}
unsigned Opcode = MI.getOpcode();
- const TargetInstrDescriptor &Desc = *MI.getDesc();
+ const TargetInstrDesc &Desc = MI.getDesc();
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
bool isSub = false;
@@ -1036,7 +1036,7 @@
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (I->getOperand(i).isFrameIndex()) {
unsigned Opcode = I->getOpcode();
- const TargetInstrDescriptor &Desc = TII.get(Opcode);
+ const TargetInstrDesc &Desc = TII.get(Opcode);
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
if (AddrMode == ARMII::AddrMode3) {
Limit = (1 << 8) - 1;