Generalize opcode selection in ARMBaseRegisterInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 0aaa311..ab0a391 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -73,6 +73,7 @@
   case ARMII::BR_JTr: return ARM::BR_JTr;
   case ARMII::BR_JTm: return ARM::BR_JTm;
   case ARMII::BR_JTadd: return ARM::BR_JTadd;
+  case ARMII::BX_RET: return ARM::BX_RET;
   case ARMII::FCPYS: return ARM::FCPYS;
   case ARMII::FCPYD: return ARM::FCPYD;
   case ARMII::FLDD: return ARM::FLDD;
@@ -120,7 +121,7 @@
               const MachineInstr *Orig) const {
   DebugLoc dl = Orig->getDebugLoc();
   if (Orig->getOpcode() == ARM::MOVi2pieces) {
-    RI.emitLoadConstPool(MBB, I, this, dl,
+    RI.emitLoadConstPool(MBB, I, dl,
                          DestReg,
                          Orig->getOperand(1).getImm(),
                          (ARMCC::CondCodes)Orig->getOperand(2).getImm(),