Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,
BtnezT8SltiX16, BtnezT8SltiuX16 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175486 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp
index b619439..22cb963 100644
--- a/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -132,7 +132,6 @@
bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
MachineBasicBlock &MBB = *MI->getParent();
-
switch(MI->getDesc().getOpcode()) {
default:
return false;
@@ -146,11 +145,19 @@
case Mips::BteqzT8SltX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16);
break;
+ case Mips::BteqzT8SltiX16:
+ ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
+ Mips::SltiRxImm16, Mips::SltiRxImmX16);
+ break;
case Mips::BteqzT8SltuX16:
// TBD: figure out a way to get this or remove the instruction
// altogether.
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16);
break;
+ case Mips::BteqzT8SltiuX16:
+ ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
+ Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
+ break;
case Mips::BtnezT8CmpX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
break;
@@ -161,11 +168,19 @@
case Mips::BtnezT8SltX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltRxRy16);
break;
+ case Mips::BtnezT8SltiX16:
+ ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
+ Mips::SltiRxImm16, Mips::SltiRxImmX16);
+ break;
case Mips::BtnezT8SltuX16:
// TBD: figure out a way to get this or remove the instruction
// altogether.
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltuRxRy16);
break;
+ case Mips::BtnezT8SltiuX16:
+ ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
+ Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
+ break;
case Mips::RetRA16:
ExpandRetRA16(MBB, MI, Mips::JrcRa16);
break;