Adjust to changes in Makefile.rules
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17167 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/Makefile b/lib/Target/PowerPC/Makefile
index e76bc3b..f06567b 100644
--- a/lib/Target/PowerPC/Makefile
+++ b/lib/Target/PowerPC/Makefile
@@ -8,45 +8,13 @@
##===----------------------------------------------------------------------===##
LEVEL = ../../..
LIBRARYNAME = powerpc
-include $(LEVEL)/Makefile.common
-
TARGET = PowerPC
+
# Make sure that tblgen is run, first thing.
-$(SourceDepend): PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
- PowerPCGenAsmWriter.inc PPC32GenCodeEmitter.inc \
+BUILT_SOURCES = PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
+ PowerPCGenAsmWriter.inc PPC32GenCodeEmitter.inc \
PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc PPC32GenInstrInfo.inc \
PPC64GenRegisterInfo.h.inc PPC64GenRegisterInfo.inc PPC64GenInstrInfo.inc
-TDFILES = $(wildcard $(SourceDir)/*.td) $(SourceDir)/../Target.td
-
-%GenRegisterNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET) register names with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
-
-%GenRegisterInfo.h.inc:: %.td $(TDFILES) $(TBLGEN)
- @echo "Building `basename $<` register information header with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
-
-%GenRegisterInfo.inc:: %.td $(TDFILES) $(TBLGEN)
- @echo "Building `basename $<` register information implementation with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
-
-$(TARGET)GenInstrNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET) instruction names with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
-
-%GenInstrInfo.inc:: %.td $(TDFILES) $(TBLGEN)
- @echo "Building `basename $<` instruction information with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
-
-%GenCodeEmitter.inc:: %.td $(TDFILES) $(TBLGEN)
- @echo "Building `basename $<` code emitter with tblgen"
- $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
-
-$(TARGET)GenAsmWriter.inc:: $(TARGET).td $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET).td assembly writer with tblgen"
- $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@
-
-clean::
- $(VERB) rm -f *.inc
+include $(LEVEL)/Makefile.common
diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 3adce5d..44d307d 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -2144,7 +2144,7 @@
if (CI_1 && OrI && OrI->getOpcode() == Instruction::Or) {
Value *Op0 = OrI->getOperand(0);
Value *Op1 = OrI->getOperand(1);
- BinaryOperator *AndI_2;
+ BinaryOperator *AndI_2 = 0;
// Whichever operand our initial And instruction is to the Or instruction,
// Look at the other operand to determine if it is also an And instruction
if (AndI == Op0) {