Pass "earlyclobber" bit through to machine
representation; coalescer and RA need to know
about it. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56161 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 9fbae68..4cdf064 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -104,7 +104,8 @@
/// the specified value. If an operand is known to be an register already,
/// the setReg method should be used.
void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
- bool isKill, bool isDead) {
+ bool isKill, bool isDead,
+ bool isEarlyClobber) {
// If this operand is already a register operand, use setReg to update the
// register's use/def lists.
if (isReg()) {
@@ -126,6 +127,7 @@
IsImp = isImp;
IsKill = isKill;
IsDead = isDead;
+ IsEarlyClobber = isEarlyClobber;
SubReg = 0;
}
@@ -181,13 +183,15 @@
OS << "%mreg" << getReg();
}
- if (isDef() || isKill() || isDead() || isImplicit()) {
+ if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
OS << "<";
bool NeedComma = false;
if (isImplicit()) {
OS << (isDef() ? "imp-def" : "imp-use");
NeedComma = true;
} else if (isDef()) {
+ if (isEarlyClobber())
+ OS << "earlyclobber,";
OS << "def";
NeedComma = true;
}