| //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // This file describes the ARM instructions in TableGen format. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| //===----------------------------------------------------------------------===// |
| // ARM specific DAG Nodes. |
| // |
| |
| // Type profiles. |
| def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; |
| def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; |
| |
| def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; |
| |
| def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; |
| |
| def SDT_ARMCMov : SDTypeProfile<1, 3, |
| [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| SDTCisVT<3, i32>]>; |
| |
| def SDT_ARMBrcond : SDTypeProfile<0, 2, |
| [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; |
| |
| def SDT_ARMBrJT : SDTypeProfile<0, 3, |
| [SDTCisPtrTy<0>, SDTCisVT<1, i32>, |
| SDTCisVT<2, i32>]>; |
| |
| def SDT_ARMBr2JT : SDTypeProfile<0, 4, |
| [SDTCisPtrTy<0>, SDTCisVT<1, i32>, |
| SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; |
| |
| def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, |
| [SDTCisVT<0, i32>, |
| SDTCisVT<1, i32>, SDTCisVT<2, i32>, |
| SDTCisVT<3, i32>, SDTCisVT<4, i32>, |
| SDTCisVT<5, OtherVT>]>; |
| |
| def SDT_ARMAnd : SDTypeProfile<1, 2, |
| [SDTCisVT<0, i32>, SDTCisVT<1, i32>, |
| SDTCisVT<2, i32>]>; |
| |
| def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; |
| |
| def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, |
| SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; |
| |
| def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; |
| def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, |
| SDTCisInt<2>]>; |
| def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; |
| |
| def SDT_ARMMEMBARRIER : SDTypeProfile<0, 0, []>; |
| def SDT_ARMSYNCBARRIER : SDTypeProfile<0, 0, []>; |
| def SDT_ARMMEMBARRIERMCR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| def SDT_ARMSYNCBARRIERMCR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| |
| def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; |
| |
| def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, |
| SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; |
| |
| // Node definitions. |
| def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; |
| def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; |
| |
| def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, |
| [SDNPHasChain, SDNPOutFlag]>; |
| def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, |
| [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
| |
| def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, |
| [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, |
| SDNPVariadic]>; |
| def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, |
| [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, |
| SDNPVariadic]>; |
| def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, |
| [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, |
| SDNPVariadic]>; |
| |
| def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, |
| [SDNPHasChain, SDNPOptInFlag]>; |
| |
| def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, |
| [SDNPInFlag]>; |
| def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov, |
| [SDNPInFlag]>; |
| |
| def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, |
| [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; |
| |
| def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, |
| [SDNPHasChain]>; |
| def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, |
| [SDNPHasChain]>; |
| |
| def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, |
| [SDNPHasChain]>; |
| |
| def ARMand : SDNode<"ARMISD::AND", SDT_ARMAnd, |
| [SDNPOutFlag]>; |
| |
| def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, |
| [SDNPOutFlag]>; |
| |
| def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, |
| [SDNPOutFlag, SDNPCommutative]>; |
| |
| def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; |
| |
| def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; |
| def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; |
| def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>; |
| |
| def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; |
| def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", |
| SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>; |
| def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", |
| SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>; |
| |
| def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER, |
| [SDNPHasChain]>; |
| def ARMSyncBarrier : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIER, |
| [SDNPHasChain]>; |
| def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERMCR, |
| [SDNPHasChain]>; |
| def ARMSyncBarrierMCR : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERMCR, |
| [SDNPHasChain]>; |
| |
| def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>; |
| |
| def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, |
| [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>; |
| |
| |
| def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; |
| |
| //===----------------------------------------------------------------------===// |
| // ARM Instruction Predicate Definitions. |
| // |
| def HasV4T : Predicate<"Subtarget->hasV4TOps()">; |
| def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; |
| def HasV5T : Predicate<"Subtarget->hasV5TOps()">; |
| def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">; |
| def HasV6 : Predicate<"Subtarget->hasV6Ops()">; |
| def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">; |
| def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; |
| def HasV7 : Predicate<"Subtarget->hasV7Ops()">; |
| def NoVFP : Predicate<"!Subtarget->hasVFP2()">; |
| def HasVFP2 : Predicate<"Subtarget->hasVFP2()">; |
| def HasVFP3 : Predicate<"Subtarget->hasVFP3()">; |
| def HasNEON : Predicate<"Subtarget->hasNEON()">; |
| def HasDivide : Predicate<"Subtarget->hasDivide()">; |
| def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">; |
| def HasDB : Predicate<"Subtarget->hasDataBarrier()">; |
| def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; |
| def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; |
| def IsThumb : Predicate<"Subtarget->isThumb()">; |
| def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; |
| def IsThumb2 : Predicate<"Subtarget->isThumb2()">; |
| def IsARM : Predicate<"!Subtarget->isThumb()">; |
| def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; |
| def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; |
| |
| // FIXME: Eventually this will be just "hasV6T2Ops". |
| def UseMovt : Predicate<"Subtarget->useMovt()">; |
| def DontUseMovt : Predicate<"!Subtarget->useMovt()">; |
| def UseVMLx : Predicate<"Subtarget->useVMLx()">; |
| |
| //===----------------------------------------------------------------------===// |
| // ARM Flag Definitions. |
| |
| class RegConstraint<string C> { |
| string Constraints = C; |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // ARM specific transformation functions and pattern fragments. |
| // |
| |
| // so_imm_neg_XFORM - Return a so_imm value packed into the format described for |
| // so_imm_neg def below. |
| def so_imm_neg_XFORM : SDNodeXForm<imm, [{ |
| return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); |
| }]>; |
| |
| // so_imm_not_XFORM - Return a so_imm value packed into the format described for |
| // so_imm_not def below. |
| def so_imm_not_XFORM : SDNodeXForm<imm, [{ |
| return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32); |
| }]>; |
| |
| /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15]. |
| def imm1_15 : PatLeaf<(i32 imm), [{ |
| return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16; |
| }]>; |
| |
| /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. |
| def imm16_31 : PatLeaf<(i32 imm), [{ |
| return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32; |
| }]>; |
| |
| def so_imm_neg : |
| PatLeaf<(imm), [{ |
| return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1; |
| }], so_imm_neg_XFORM>; |
| |
| def so_imm_not : |
| PatLeaf<(imm), [{ |
| return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1; |
| }], so_imm_not_XFORM>; |
| |
| // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. |
| def sext_16_node : PatLeaf<(i32 GPR:$a), [{ |
| return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; |
| }]>; |
| |
| /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield |
| /// e.g., 0xf000ffff |
| def bf_inv_mask_imm : Operand<i32>, |
| PatLeaf<(imm), [{ |
| return ARM::isBitFieldInvertedMask(N->getZExtValue()); |
| }] > { |
| let PrintMethod = "printBitfieldInvMaskImmOperand"; |
| } |
| |
| /// Split a 32-bit immediate into two 16 bit parts. |
| def hi16 : SDNodeXForm<imm, [{ |
| return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); |
| }]>; |
| |
| def lo16AllZero : PatLeaf<(i32 imm), [{ |
| // Returns true if all low 16-bits are 0. |
| return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; |
| }], hi16>; |
| |
| /// imm0_65535 predicate - True if the 32-bit immediate is in the range |
| /// [0.65535]. |
| def imm0_65535 : PatLeaf<(i32 imm), [{ |
| return (uint32_t)N->getZExtValue() < 65536; |
| }]>; |
| |
| class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; |
| class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; |
| |
| /// adde and sube predicates - True based on whether the carry flag output |
| /// will be needed or not. |
| def adde_dead_carry : |
| PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS), |
| [{return !N->hasAnyUseOfValue(1);}]>; |
| def sube_dead_carry : |
| PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS), |
| [{return !N->hasAnyUseOfValue(1);}]>; |
| def adde_live_carry : |
| PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS), |
| [{return N->hasAnyUseOfValue(1);}]>; |
| def sube_live_carry : |
| PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS), |
| [{return N->hasAnyUseOfValue(1);}]>; |
| |
| //===----------------------------------------------------------------------===// |
| // Operand Definitions. |
| // |
| |
| // Branch target. |
| def brtarget : Operand<OtherVT>; |
| |
| // A list of registers separated by comma. Used by load/store multiple. |
| def reglist : Operand<i32> { |
| let PrintMethod = "printRegisterList"; |
| } |
| |
| // An operand for the CONSTPOOL_ENTRY pseudo-instruction. |
| def cpinst_operand : Operand<i32> { |
| let PrintMethod = "printCPInstOperand"; |
| } |
| |
| def jtblock_operand : Operand<i32> { |
| let PrintMethod = "printJTBlockOperand"; |
| } |
| def jt2block_operand : Operand<i32> { |
| let PrintMethod = "printJT2BlockOperand"; |
| } |
| |
| // Local PC labels. |
| def pclabel : Operand<i32> { |
| let PrintMethod = "printPCLabel"; |
| } |
| |
| // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. |
| def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ |
| int32_t v = (int32_t)N->getZExtValue(); |
| return v == 8 || v == 16 || v == 24; }]> { |
| string EncoderMethod = "getRotImmOpValue"; |
| } |
| |
| // shift_imm: An integer that encodes a shift amount and the type of shift |
| // (currently either asr or lsl) using the same encoding used for the |
| // immediates in so_reg operands. |
| def shift_imm : Operand<i32> { |
| let PrintMethod = "printShiftImmOperand"; |
| } |
| |
| // shifter_operand operands: so_reg and so_imm. |
| def so_reg : Operand<i32>, // reg reg imm |
| ComplexPattern<i32, 3, "SelectShifterOperandReg", |
| [shl,srl,sra,rotr]> { |
| string EncoderMethod = "getSORegOpValue"; |
| let PrintMethod = "printSORegOperand"; |
| let MIOperandInfo = (ops GPR, GPR, i32imm); |
| } |
| |
| // so_imm - Match a 32-bit shifter_operand immediate operand, which is an |
| // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are |
| // represented in the imm field in the same 12-bit form that they are encoded |
| // into so_imm instructions: the 8-bit immediate is the least significant bits |
| // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11]. |
| def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> { |
| string EncoderMethod = "getSOImmOpValue"; |
| let PrintMethod = "printSOImmOperand"; |
| } |
| |
| // Break so_imm's up into two pieces. This handles immediates with up to 16 |
| // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to |
| // get the first/second pieces. |
| def so_imm2part : Operand<i32>, |
| PatLeaf<(imm), [{ |
| return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); |
| }]> { |
| let PrintMethod = "printSOImm2PartOperand"; |
| } |
| |
| def so_imm2part_1 : SDNodeXForm<imm, [{ |
| unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue()); |
| return CurDAG->getTargetConstant(V, MVT::i32); |
| }]>; |
| |
| def so_imm2part_2 : SDNodeXForm<imm, [{ |
| unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue()); |
| return CurDAG->getTargetConstant(V, MVT::i32); |
| }]>; |
| |
| def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{ |
| return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue()); |
| }]> { |
| let PrintMethod = "printSOImm2PartOperand"; |
| } |
| |
| def so_neg_imm2part_1 : SDNodeXForm<imm, [{ |
| unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue()); |
| return CurDAG->getTargetConstant(V, MVT::i32); |
| }]>; |
| |
| def so_neg_imm2part_2 : SDNodeXForm<imm, [{ |
| unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue()); |
| return CurDAG->getTargetConstant(V, MVT::i32); |
| }]>; |
| |
| /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. |
| def imm0_31 : Operand<i32>, PatLeaf<(imm), [{ |
| return (int32_t)N->getZExtValue() < 32; |
| }]>; |
| |
| // Define ARM specific addressing modes. |
| |
| // addrmode2base := reg +/- imm12 |
| // |
| def addrmode2base : Operand<i32>, |
| ComplexPattern<i32, 3, "SelectAddrMode2Base", []> { |
| let PrintMethod = "printAddrMode2Operand"; |
| let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); |
| } |
| // addrmode2shop := reg +/- reg shop imm |
| // |
| def addrmode2shop : Operand<i32>, |
| ComplexPattern<i32, 3, "SelectAddrMode2ShOp", []> { |
| let PrintMethod = "printAddrMode2Operand"; |
| let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); |
| } |
| |
| // addrmode2 := (addrmode2base || addrmode2shop) |
| // |
| def addrmode2 : Operand<i32>, |
| ComplexPattern<i32, 3, "SelectAddrMode2", []> { |
| let PrintMethod = "printAddrMode2Operand"; |
| let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); |
| } |
| |
| def am2offset : Operand<i32>, |
| ComplexPattern<i32, 2, "SelectAddrMode2Offset", |
| [], [SDNPWantRoot]> { |
| let PrintMethod = "printAddrMode2OffsetOperand"; |
| let MIOperandInfo = (ops GPR, i32imm); |
| } |
| |
| // addrmode3 := reg +/- reg |
| // addrmode3 := reg +/- imm8 |
| // |
| def addrmode3 : Operand<i32>, |
| ComplexPattern<i32, 3, "SelectAddrMode3", []> { |
| let PrintMethod = "printAddrMode3Operand"; |
| let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); |
| } |
| |
| def am3offset : Operand<i32>, |
| ComplexPattern<i32, 2, "SelectAddrMode3Offset", |
| [], [SDNPWantRoot]> { |
| let PrintMethod = "printAddrMode3OffsetOperand"; |
| let MIOperandInfo = (ops GPR, i32imm); |
| } |
| |
| // addrmode4 := reg, <mode|W> |
| // |
| def addrmode4 : Operand<i32>, |
| ComplexPattern<i32, 2, "SelectAddrMode4", []> { |
| let PrintMethod = "printAddrMode4Operand"; |
| let MIOperandInfo = (ops GPR:$addr, i32imm); |
| } |
| |
| // addrmode5 := reg +/- imm8*4 |
| // |
| def addrmode5 : Operand<i32>, |
| ComplexPattern<i32, 2, "SelectAddrMode5", []> { |
| let PrintMethod = "printAddrMode5Operand"; |
| let MIOperandInfo = (ops GPR:$base, i32imm); |
| } |
| |
| // addrmode6 := reg with optional writeback |
| // |
| def addrmode6 : Operand<i32>, |
| ComplexPattern<i32, 2, "SelectAddrMode6", []> { |
| let PrintMethod = "printAddrMode6Operand"; |
| let MIOperandInfo = (ops GPR:$addr, i32imm); |
| } |
| |
| def am6offset : Operand<i32> { |
| let PrintMethod = "printAddrMode6OffsetOperand"; |
| let MIOperandInfo = (ops GPR); |
| } |
| |
| // addrmodepc := pc + reg |
| // |
| def addrmodepc : Operand<i32>, |
| ComplexPattern<i32, 2, "SelectAddrModePC", []> { |
| let PrintMethod = "printAddrModePCOperand"; |
| let MIOperandInfo = (ops GPR, i32imm); |
| } |
| |
| def nohash_imm : Operand<i32> { |
| let PrintMethod = "printNoHashImmediate"; |
| } |
| |
| //===----------------------------------------------------------------------===// |
| |
| include "ARMInstrFormats.td" |
| |
| //===----------------------------------------------------------------------===// |
| // Multiclass helpers... |
| // |
| |
| /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a |
| /// binop that produces a value. |
| multiclass AsI1_bin_irs<bits<4> opcod, string opc, |
| InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, |
| PatFrag opnode, bit Commutable = 0> { |
| // The register-immediate version is re-materializable. This is useful |
| // in particular for taking the address of a local. |
| let isReMaterializable = 1 in { |
| def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, |
| iii, opc, "\t$Rd, $Rn, $imm", |
| [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> { |
| bits<4> Rd; |
| bits<4> Rn; |
| bits<12> imm; |
| let Inst{25} = 1; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = Rn; |
| let Inst{11-0} = imm; |
| } |
| } |
| def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, |
| iir, opc, "\t$Rd, $Rn, $Rm", |
| [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> { |
| bits<4> Rd; |
| bits<4> Rn; |
| bits<4> Rm; |
| let Inst{11-4} = 0b00000000; |
| let Inst{25} = 0; |
| let isCommutable = Commutable; |
| let Inst{3-0} = Rm; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = Rn; |
| } |
| def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, |
| iis, opc, "\t$Rd, $Rn, $shift", |
| [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> { |
| bits<4> Rd; |
| bits<4> Rn; |
| bits<12> shift; |
| let Inst{25} = 0; |
| let Inst{11-0} = shift; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = Rn; |
| } |
| } |
| |
| /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the |
| /// instruction modifies the CPSR register. |
| let Defs = [CPSR] in { |
| multiclass AI1_bin_s_irs<bits<4> opcod, string opc, |
| InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, |
| PatFrag opnode, bit Commutable = 0> { |
| def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, |
| iii, opc, "\t$Rd, $Rn, $imm", |
| [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> { |
| bits<4> Rd; |
| bits<4> Rn; |
| bits<12> imm; |
| let Inst{25} = 1; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = Rn; |
| let Inst{11-0} = imm; |
| let Inst{20} = 1; |
| } |
| def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, |
| iir, opc, "\t$Rd, $Rn, $Rm", |
| [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> { |
| bits<4> Rd; |
| bits<4> Rn; |
| bits<4> Rm; |
| let Inst{11-4} = 0b00000000; |
| let Inst{25} = 0; |
| let isCommutable = Commutable; |
| let Inst{3-0} = Rm; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = Rn; |
| let Inst{20} = 1; |
| } |
| def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, |
| iis, opc, "\t$Rd, $Rn, $shift", |
| [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> { |
| bits<4> Rd; |
| bits<4> Rn; |
| bits<12> shift; |
| let Inst{25} = 0; |
| let Inst{11-0} = shift; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = Rn; |
| let Inst{20} = 1; |
| } |
| } |
| } |
| |
| /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test |
| /// patterns. Similar to AsI1_bin_irs except the instruction does not produce |
| /// a explicit result, only implicitly set CPSR. |
| let isCompare = 1, Defs = [CPSR] in { |
| multiclass AI1_cmp_irs<bits<4> opcod, string opc, |
| InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, |
| PatFrag opnode, bit Commutable = 0> { |
| def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii, |
| opc, "\t$Rn, $imm", |
| [(opnode GPR:$Rn, so_imm:$imm)]> { |
| bits<4> Rn; |
| bits<12> imm; |
| let Inst{25} = 1; |
| let Inst{15-12} = 0b0000; |
| let Inst{19-16} = Rn; |
| let Inst{11-0} = imm; |
| let Inst{20} = 1; |
| let Inst{20} = 1; |
| } |
| def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, |
| opc, "\t$Rn, $Rm", |
| [(opnode GPR:$Rn, GPR:$Rm)]> { |
| bits<4> Rn; |
| bits<4> Rm; |
| let Inst{11-4} = 0b00000000; |
| let Inst{25} = 0; |
| let isCommutable = Commutable; |
| let Inst{3-0} = Rm; |
| let Inst{15-12} = 0b0000; |
| let Inst{19-16} = Rn; |
| let Inst{20} = 1; |
| } |
| def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis, |
| opc, "\t$Rn, $shift", |
| [(opnode GPR:$Rn, so_reg:$shift)]> { |
| bits<4> Rn; |
| bits<12> shift; |
| let Inst{25} = 0; |
| let Inst{11-0} = shift; |
| let Inst{15-12} = 0b0000; |
| let Inst{19-16} = Rn; |
| let Inst{20} = 1; |
| } |
| } |
| } |
| |
| /// AI_ext_rrot - A unary operation with two forms: one whose operand is a |
| /// register and one whose operand is a register rotated by 8/16/24. |
| /// FIXME: Remove the 'r' variant. Its rot_imm is zero. |
| multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> { |
| def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm), |
| IIC_iEXTr, opc, "\t$Rd, $Rm", |
| [(set GPR:$Rd, (opnode GPR:$Rm))]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{11-10} = 0b00; |
| let Inst{19-16} = 0b1111; |
| } |
| def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot), |
| IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot", |
| [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>, |
| Requires<[IsARM, HasV6]> { |
| bits<2> rot; |
| let Inst{11-10} = rot; |
| let Inst{19-16} = 0b1111; |
| } |
| } |
| |
| multiclass AI_ext_rrot_np<bits<8> opcod, string opc> { |
| def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm), |
| IIC_iEXTr, opc, "\t$Rd, $Rm", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{11-10} = 0b00; |
| let Inst{19-16} = 0b1111; |
| } |
| def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot), |
| IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV6]> { |
| bits<2> rot; |
| let Inst{11-10} = rot; |
| let Inst{19-16} = 0b1111; |
| } |
| } |
| |
| /// AI_exta_rrot - A binary operation with two forms: one whose operand is a |
| /// register and one whose operand is a register rotated by 8/16/24. |
| multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> { |
| def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), |
| IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm", |
| [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{11-10} = 0b00; |
| } |
| def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, |
| rot_imm:$rot), |
| IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot", |
| [(set GPR:$Rd, (opnode GPR:$Rn, |
| (rotr GPR:$Rm, rot_imm:$rot)))]>, |
| Requires<[IsARM, HasV6]> { |
| bits<4> Rn; |
| bits<2> rot; |
| let Inst{19-16} = Rn; |
| let Inst{11-10} = rot; |
| } |
| } |
| |
| // For disassembly only. |
| multiclass AI_exta_rrot_np<bits<8> opcod, string opc> { |
| def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), |
| IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{11-10} = 0b00; |
| } |
| def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, |
| rot_imm:$rot), |
| IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV6]> { |
| bits<4> Rn; |
| bits<2> rot; |
| let Inst{19-16} = Rn; |
| let Inst{11-10} = rot; |
| } |
| } |
| |
| /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. |
| let Uses = [CPSR] in { |
| multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, |
| bit Commutable = 0> { |
| def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), |
| DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", |
| [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>, |
| Requires<[IsARM]> { |
| bits<4> Rd; |
| bits<4> Rn; |
| bits<12> imm; |
| let Inst{25} = 1; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = Rn; |
| let Inst{11-0} = imm; |
| } |
| def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), |
| DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", |
| [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, |
| Requires<[IsARM]> { |
| bits<4> Rd; |
| bits<4> Rn; |
| bits<4> Rm; |
| let Inst{11-4} = 0b00000000; |
| let Inst{25} = 0; |
| let isCommutable = Commutable; |
| let Inst{3-0} = Rm; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = Rn; |
| } |
| def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), |
| DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", |
| [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>, |
| Requires<[IsARM]> { |
| bits<4> Rd; |
| bits<4> Rn; |
| bits<12> shift; |
| let Inst{25} = 0; |
| let Inst{11-0} = shift; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = Rn; |
| } |
| } |
| // Carry setting variants |
| let Defs = [CPSR] in { |
| multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode, |
| bit Commutable = 0> { |
| def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), |
| DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"), |
| [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>, |
| Requires<[IsARM]> { |
| bits<4> Rd; |
| bits<4> Rn; |
| bits<12> imm; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = Rn; |
| let Inst{11-0} = imm; |
| let Inst{20} = 1; |
| let Inst{25} = 1; |
| } |
| def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), |
| DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"), |
| [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, |
| Requires<[IsARM]> { |
| bits<4> Rd; |
| bits<4> Rn; |
| bits<4> Rm; |
| let Inst{11-4} = 0b00000000; |
| let isCommutable = Commutable; |
| let Inst{3-0} = Rm; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = Rn; |
| let Inst{20} = 1; |
| let Inst{25} = 0; |
| } |
| def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), |
| DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"), |
| [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>, |
| Requires<[IsARM]> { |
| bits<4> Rd; |
| bits<4> Rn; |
| bits<12> shift; |
| let Inst{11-0} = shift; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = Rn; |
| let Inst{20} = 1; |
| let Inst{25} = 0; |
| } |
| } |
| } |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // Instructions |
| //===----------------------------------------------------------------------===// |
| |
| //===----------------------------------------------------------------------===// |
| // Miscellaneous Instructions. |
| // |
| |
| /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in |
| /// the function. The first operand is the ID# for this instruction, the second |
| /// is the index into the MachineConstantPool that this is, the third is the |
| /// size in bytes of this constant pool entry. |
| let neverHasSideEffects = 1, isNotDuplicable = 1 in |
| def CONSTPOOL_ENTRY : |
| PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, |
| i32imm:$size), NoItinerary, "", []>; |
| |
| // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE |
| // from removing one half of the matched pairs. That breaks PEI, which assumes |
| // these will always be in pairs, and asserts if it finds otherwise. Better way? |
| let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { |
| def ADJCALLSTACKUP : |
| PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, "", |
| [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; |
| |
| def ADJCALLSTACKDOWN : |
| PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, "", |
| [(ARMcallseq_start timm:$amt)]>; |
| } |
| |
| def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV6T2]> { |
| let Inst{27-16} = 0b001100100000; |
| let Inst{15-8} = 0b11110000; |
| let Inst{7-0} = 0b00000000; |
| } |
| |
| def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV6T2]> { |
| let Inst{27-16} = 0b001100100000; |
| let Inst{15-8} = 0b11110000; |
| let Inst{7-0} = 0b00000001; |
| } |
| |
| def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV6T2]> { |
| let Inst{27-16} = 0b001100100000; |
| let Inst{15-8} = 0b11110000; |
| let Inst{7-0} = 0b00000010; |
| } |
| |
| def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV6T2]> { |
| let Inst{27-16} = 0b001100100000; |
| let Inst{15-8} = 0b11110000; |
| let Inst{7-0} = 0b00000011; |
| } |
| |
| def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel", |
| "\t$dst, $a, $b", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV6]> { |
| bits<4> Rd; |
| bits<4> Rn; |
| bits<4> Rm; |
| let Inst{3-0} = Rm; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = Rn; |
| let Inst{27-20} = 0b01101000; |
| let Inst{7-4} = 0b1011; |
| let Inst{11-8} = 0b1111; |
| } |
| |
| def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV6T2]> { |
| let Inst{27-16} = 0b001100100000; |
| let Inst{15-8} = 0b11110000; |
| let Inst{7-0} = 0b00000100; |
| } |
| |
| // The i32imm operand $val can be used by a debugger to store more information |
| // about the breakpoint. |
| def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM]> { |
| bits<16> val; |
| let Inst{3-0} = val{3-0}; |
| let Inst{19-8} = val{15-4}; |
| let Inst{27-20} = 0b00010010; |
| let Inst{7-4} = 0b0111; |
| } |
| |
| // Change Processor State is a system instruction -- for disassembly only. |
| // The singleton $opt operand contains the following information: |
| // opt{4-0} = mode from Inst{4-0} |
| // opt{5} = changemode from Inst{17} |
| // opt{8-6} = AIF from Inst{8-6} |
| // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable |
| // FIXME: Integrated assembler will need these split out. |
| def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM]> { |
| let Inst{31-28} = 0b1111; |
| let Inst{27-20} = 0b00010000; |
| let Inst{16} = 0; |
| let Inst{5} = 0; |
| } |
| |
| // Preload signals the memory system of possible future data/instruction access. |
| // These are for disassembly only. |
| // |
| // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. |
| // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. |
| multiclass APreLoad<bit data, bit read, string opc> { |
| |
| def i : AXI<(outs), (ins GPR:$base, neg_zero:$imm), MiscFrm, NoItinerary, |
| !strconcat(opc, "\t[$base, $imm]"), []> { |
| let Inst{31-26} = 0b111101; |
| let Inst{25} = 0; // 0 for immediate form |
| let Inst{24} = data; |
| let Inst{22} = read; |
| let Inst{21-20} = 0b01; |
| } |
| |
| def r : AXI<(outs), (ins addrmode2:$addr), MiscFrm, NoItinerary, |
| !strconcat(opc, "\t$addr"), []> { |
| let Inst{31-26} = 0b111101; |
| let Inst{25} = 1; // 1 for register form |
| let Inst{24} = data; |
| let Inst{22} = read; |
| let Inst{21-20} = 0b01; |
| let Inst{4} = 0; |
| } |
| } |
| |
| defm PLD : APreLoad<1, 1, "pld">; |
| defm PLDW : APreLoad<1, 0, "pldw">; |
| defm PLI : APreLoad<0, 1, "pli">; |
| |
| def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary, |
| "setend\t$end", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM]> { |
| bits<1> end; |
| let Inst{31-10} = 0b1111000100000001000000; |
| let Inst{9} = end; |
| let Inst{8-0} = 0; |
| } |
| |
| def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV7]> { |
| let Inst{27-16} = 0b001100100000; |
| let Inst{7-4} = 0b1111; |
| } |
| |
| // A5.4 Permanently UNDEFINED instructions. |
| let isBarrier = 1, isTerminator = 1 in |
| def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, |
| "trap", [(trap)]>, |
| Requires<[IsARM]> { |
| let Inst{27-25} = 0b011; |
| let Inst{24-20} = 0b11111; |
| let Inst{7-5} = 0b111; |
| let Inst{4} = 0b1; |
| } |
| |
| // Address computation and loads and stores in PIC mode. |
| let isNotDuplicable = 1 in { |
| def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), |
| Pseudo, IIC_iALUr, "", |
| [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; |
| |
| let AddedComplexity = 10 in { |
| def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), |
| Pseudo, IIC_iLoad_r, "", |
| [(set GPR:$dst, (load addrmodepc:$addr))]>; |
| |
| def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), |
| Pseudo, IIC_iLoad_bh_r, "", |
| [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; |
| |
| def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), |
| Pseudo, IIC_iLoad_bh_r, "", |
| [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; |
| |
| def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), |
| Pseudo, IIC_iLoad_bh_r, "", |
| [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; |
| |
| def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), |
| Pseudo, IIC_iLoad_bh_r, "", |
| [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; |
| } |
| let AddedComplexity = 10 in { |
| def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), |
| Pseudo, IIC_iStore_r, "", |
| [(store GPR:$src, addrmodepc:$addr)]>; |
| |
| def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), |
| Pseudo, IIC_iStore_bh_r, "", |
| [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; |
| |
| def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), |
| Pseudo, IIC_iStore_bh_r, "", |
| [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; |
| } |
| } // isNotDuplicable = 1 |
| |
| |
| // LEApcrel - Load a pc-relative address into a register without offending the |
| // assembler. |
| let neverHasSideEffects = 1 in { |
| let isReMaterializable = 1 in |
| def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), |
| Pseudo, IIC_iALUi, |
| "adr$p\t$dst, #$label", []>; |
| |
| } // neverHasSideEffects |
| def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), |
| (ins i32imm:$label, nohash_imm:$id, pred:$p), |
| Pseudo, IIC_iALUi, |
| "adr$p\t$dst, #${label}_${id}", []> { |
| let Inst{25} = 1; |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // Control Flow Instructions. |
| // |
| |
| let isReturn = 1, isTerminator = 1, isBarrier = 1 in { |
| // ARMV4T and above |
| def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, |
| "bx", "\tlr", [(ARMretflag)]>, |
| Requires<[IsARM, HasV4T]> { |
| let Inst{3-0} = 0b1110; |
| let Inst{7-4} = 0b0001; |
| let Inst{19-8} = 0b111111111111; |
| let Inst{27-20} = 0b00010010; |
| } |
| |
| // ARMV4 only |
| def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, |
| "mov", "\tpc, lr", [(ARMretflag)]>, |
| Requires<[IsARM, NoV4T]> { |
| let Inst{11-0} = 0b000000001110; |
| let Inst{15-12} = 0b1111; |
| let Inst{19-16} = 0b0000; |
| let Inst{27-20} = 0b00011010; |
| } |
| } |
| |
| // Indirect branches |
| let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { |
| // ARMV4T and above |
| def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", |
| [(brind GPR:$dst)]>, |
| Requires<[IsARM, HasV4T]> { |
| bits<4> dst; |
| let Inst{7-4} = 0b0001; |
| let Inst{19-8} = 0b111111111111; |
| let Inst{27-20} = 0b00010010; |
| let Inst{31-28} = 0b1110; |
| let Inst{3-0} = dst; |
| } |
| |
| // ARMV4 only |
| def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst", |
| [(brind GPR:$dst)]>, |
| Requires<[IsARM, NoV4T]> { |
| bits<4> dst; |
| let Inst{11-4} = 0b00000000; |
| let Inst{15-12} = 0b1111; |
| let Inst{19-16} = 0b0000; |
| let Inst{27-20} = 0b00011010; |
| let Inst{31-28} = 0b1110; |
| let Inst{3-0} = dst; |
| } |
| } |
| |
| // FIXME: remove when we have a way to marking a MI with these properties. |
| // FIXME: Should pc be an implicit operand like PICADD, etc? |
| let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, |
| hasExtraDefRegAllocReq = 1 in |
| def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, |
| reglist:$dsts, variable_ops), |
| IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr, |
| "ldm${addr:submode}${p}\t$addr!, $dsts", |
| "$addr.addr = $wb", []>; |
| |
| // On non-Darwin platforms R9 is callee-saved. |
| let isCall = 1, |
| Defs = [R0, R1, R2, R3, R12, LR, |
| D0, D1, D2, D3, D4, D5, D6, D7, |
| D16, D17, D18, D19, D20, D21, D22, D23, |
| D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { |
| def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), |
| IIC_Br, "bl\t$func", |
| [(ARMcall tglobaladdr:$func)]>, |
| Requires<[IsARM, IsNotDarwin]> { |
| let Inst{31-28} = 0b1110; |
| } |
| |
| def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), |
| IIC_Br, "bl", "\t$func", |
| [(ARMcall_pred tglobaladdr:$func)]>, |
| Requires<[IsARM, IsNotDarwin]>; |
| |
| // ARMv5T and above |
| def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, |
| IIC_Br, "blx\t$func", |
| [(ARMcall GPR:$func)]>, |
| Requires<[IsARM, HasV5T, IsNotDarwin]> { |
| bits<4> func; |
| let Inst{7-4} = 0b0011; |
| let Inst{19-8} = 0b111111111111; |
| let Inst{27-20} = 0b00010010; |
| let Inst{3-0} = func; |
| } |
| |
| // ARMv4T |
| // Note: Restrict $func to the tGPR regclass to prevent it being in LR. |
| def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops), |
| IIC_Br, "mov\tlr, pc\n\tbx\t$func", |
| [(ARMcall_nolink tGPR:$func)]>, |
| Requires<[IsARM, HasV4T, IsNotDarwin]> { |
| let Inst{7-4} = 0b0001; |
| let Inst{19-8} = 0b111111111111; |
| let Inst{27-20} = 0b00010010; |
| } |
| |
| // ARMv4 |
| def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops), |
| IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func", |
| [(ARMcall_nolink tGPR:$func)]>, |
| Requires<[IsARM, NoV4T, IsNotDarwin]> { |
| let Inst{11-4} = 0b00000000; |
| let Inst{15-12} = 0b1111; |
| let Inst{19-16} = 0b0000; |
| let Inst{27-20} = 0b00011010; |
| } |
| } |
| |
| // On Darwin R9 is call-clobbered. |
| let isCall = 1, |
| Defs = [R0, R1, R2, R3, R9, R12, LR, |
| D0, D1, D2, D3, D4, D5, D6, D7, |
| D16, D17, D18, D19, D20, D21, D22, D23, |
| D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { |
| def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), |
| IIC_Br, "bl\t$func", |
| [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> { |
| let Inst{31-28} = 0b1110; |
| } |
| |
| def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), |
| IIC_Br, "bl", "\t$func", |
| [(ARMcall_pred tglobaladdr:$func)]>, |
| Requires<[IsARM, IsDarwin]>; |
| |
| // ARMv5T and above |
| def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, |
| IIC_Br, "blx\t$func", |
| [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> { |
| let Inst{7-4} = 0b0011; |
| let Inst{19-8} = 0b111111111111; |
| let Inst{27-20} = 0b00010010; |
| } |
| |
| // ARMv4T |
| // Note: Restrict $func to the tGPR regclass to prevent it being in LR. |
| def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops), |
| IIC_Br, "mov\tlr, pc\n\tbx\t$func", |
| [(ARMcall_nolink tGPR:$func)]>, |
| Requires<[IsARM, HasV4T, IsDarwin]> { |
| let Inst{7-4} = 0b0001; |
| let Inst{19-8} = 0b111111111111; |
| let Inst{27-20} = 0b00010010; |
| } |
| |
| // ARMv4 |
| def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops), |
| IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func", |
| [(ARMcall_nolink tGPR:$func)]>, |
| Requires<[IsARM, NoV4T, IsDarwin]> { |
| let Inst{11-4} = 0b00000000; |
| let Inst{15-12} = 0b1111; |
| let Inst{19-16} = 0b0000; |
| let Inst{27-20} = 0b00011010; |
| } |
| } |
| |
| // Tail calls. |
| |
| let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { |
| // Darwin versions. |
| let Defs = [R0, R1, R2, R3, R9, R12, |
| D0, D1, D2, D3, D4, D5, D6, D7, |
| D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, |
| D27, D28, D29, D30, D31, PC], |
| Uses = [SP] in { |
| def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops), |
| Pseudo, IIC_Br, |
| "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>; |
| |
| def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops), |
| Pseudo, IIC_Br, |
| "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>; |
| |
| def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops), |
| IIC_Br, "b\t$dst @ TAILCALL", |
| []>, Requires<[IsDarwin]>; |
| |
| def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops), |
| IIC_Br, "b.w\t$dst @ TAILCALL", |
| []>, Requires<[IsDarwin]>; |
| |
| def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops), |
| BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL", |
| []>, Requires<[IsDarwin]> { |
| let Inst{7-4} = 0b0001; |
| let Inst{19-8} = 0b111111111111; |
| let Inst{27-20} = 0b00010010; |
| let Inst{31-28} = 0b1110; |
| } |
| } |
| |
| // Non-Darwin versions (the difference is R9). |
| let Defs = [R0, R1, R2, R3, R12, |
| D0, D1, D2, D3, D4, D5, D6, D7, |
| D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, |
| D27, D28, D29, D30, D31, PC], |
| Uses = [SP] in { |
| def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops), |
| Pseudo, IIC_Br, |
| "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>; |
| |
| def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops), |
| Pseudo, IIC_Br, |
| "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>; |
| |
| def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops), |
| IIC_Br, "b\t$dst @ TAILCALL", |
| []>, Requires<[IsARM, IsNotDarwin]>; |
| |
| def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops), |
| IIC_Br, "b.w\t$dst @ TAILCALL", |
| []>, Requires<[IsThumb, IsNotDarwin]>; |
| |
| def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops), |
| BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL", |
| []>, Requires<[IsNotDarwin]> { |
| let Inst{7-4} = 0b0001; |
| let Inst{19-8} = 0b111111111111; |
| let Inst{27-20} = 0b00010010; |
| let Inst{31-28} = 0b1110; |
| } |
| } |
| } |
| |
| let isBranch = 1, isTerminator = 1 in { |
| // B is "predicable" since it can be xformed into a Bcc. |
| let isBarrier = 1 in { |
| let isPredicable = 1 in |
| def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br, |
| "b\t$target", [(br bb:$target)]>; |
| |
| let isNotDuplicable = 1, isIndirectBranch = 1 in { |
| def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), |
| IIC_Br, "mov\tpc, $target$jt", |
| [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> { |
| let Inst{11-4} = 0b00000000; |
| let Inst{15-12} = 0b1111; |
| let Inst{20} = 0; // S Bit |
| let Inst{24-21} = 0b1101; |
| let Inst{27-25} = 0b000; |
| } |
| def BR_JTm : JTI<(outs), |
| (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id), |
| IIC_Br, "ldr\tpc, $target$jt", |
| [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, |
| imm:$id)]> { |
| let Inst{15-12} = 0b1111; |
| let Inst{20} = 1; // L bit |
| let Inst{21} = 0; // W bit |
| let Inst{22} = 0; // B bit |
| let Inst{24} = 1; // P bit |
| let Inst{27-25} = 0b011; |
| } |
| def BR_JTadd : JTI<(outs), |
| (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id), |
| IIC_Br, "add\tpc, $target, $idx$jt", |
| [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, |
| imm:$id)]> { |
| let Inst{15-12} = 0b1111; |
| let Inst{20} = 0; // S bit |
| let Inst{24-21} = 0b0100; |
| let Inst{27-25} = 0b000; |
| } |
| } // isNotDuplicable = 1, isIndirectBranch = 1 |
| } // isBarrier = 1 |
| |
| // FIXME: should be able to write a pattern for ARMBrcond, but can't use |
| // a two-value operand where a dag node expects two operands. :( |
| def Bcc : ABI<0b1010, (outs), (ins brtarget:$target), |
| IIC_Br, "b", "\t$target", |
| [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; |
| } |
| |
| // Branch and Exchange Jazelle -- for disassembly only |
| def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{23-20} = 0b0010; |
| //let Inst{19-8} = 0xfff; |
| let Inst{7-4} = 0b0010; |
| } |
| |
| // Secure Monitor Call is a system instruction -- for disassembly only |
| def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{23-20} = 0b0110; |
| let Inst{7-4} = 0b0111; |
| } |
| |
| // Supervisor Call (Software Interrupt) -- for disassembly only |
| let isCall = 1 in { |
| def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", |
| [/* For disassembly only; pattern left blank */]>; |
| } |
| |
| // Store Return State is a system instruction -- for disassembly only |
| def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode), |
| NoItinerary, "srs${addr:submode}\tsp!, $mode", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{31-28} = 0b1111; |
| let Inst{22-20} = 0b110; // W = 1 |
| } |
| |
| def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode), |
| NoItinerary, "srs${addr:submode}\tsp, $mode", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{31-28} = 0b1111; |
| let Inst{22-20} = 0b100; // W = 0 |
| } |
| |
| // Return From Exception is a system instruction -- for disassembly only |
| def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base), |
| NoItinerary, "rfe${addr:submode}\t$base!", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{31-28} = 0b1111; |
| let Inst{22-20} = 0b011; // W = 1 |
| } |
| |
| def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base), |
| NoItinerary, "rfe${addr:submode}\t$base", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{31-28} = 0b1111; |
| let Inst{22-20} = 0b001; // W = 0 |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // Load / store Instructions. |
| // |
| |
| // Load |
| let canFoldAsLoad = 1, isReMaterializable = 1 in |
| def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoad_r, |
| "ldr", "\t$dst, $addr", |
| [(set GPR:$dst, (load addrmode2:$addr))]>; |
| |
| // Special LDR for loads from non-pc-relative constpools. |
| let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1, |
| isReMaterializable = 1 in |
| def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoad_r, |
| "ldr", "\t$dst, $addr", []>; |
| |
| // Loads with zero extension |
| def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, |
| IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr", |
| [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; |
| |
| def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, |
| IIC_iLoad_bh_r, "ldrb", "\t$dst, $addr", |
| [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; |
| |
| // Loads with sign extension |
| def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, |
| IIC_iLoad_bh_r, "ldrsh", "\t$dst, $addr", |
| [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; |
| |
| def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, |
| IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr", |
| [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; |
| |
| let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { |
| // Load doubleword |
| def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm, |
| IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr", |
| []>, Requires<[IsARM, HasV5TE]>; |
| |
| // Indexed loads |
| def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb), |
| (ins addrmode2:$addr), LdFrm, IIC_iLoad_ru, |
| "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>; |
| |
| def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), |
| (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru, |
| "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>; |
| |
| def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb), |
| (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru, |
| "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>; |
| |
| def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), |
| (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, |
| "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>; |
| |
| def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb), |
| (ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru, |
| "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>; |
| |
| def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), |
| (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru, |
| "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>; |
| |
| def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb), |
| (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru, |
| "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>; |
| |
| def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), |
| (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, |
| "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>; |
| |
| def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb), |
| (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru, |
| "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>; |
| |
| def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), |
| (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru, |
| "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>; |
| |
| // For disassembly only |
| def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb), |
| (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_d_ru, |
| "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>, |
| Requires<[IsARM, HasV5TE]>; |
| |
| // For disassembly only |
| def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb), |
| (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_d_ru, |
| "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>, |
| Requires<[IsARM, HasV5TE]>; |
| |
| } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 |
| |
| // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only. |
| |
| def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), |
| (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru, |
| "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> { |
| let Inst{21} = 1; // overwrite |
| } |
| |
| def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), |
| (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru, |
| "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> { |
| let Inst{21} = 1; // overwrite |
| } |
| |
| def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), |
| (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, |
| "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> { |
| let Inst{21} = 1; // overwrite |
| } |
| |
| def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), |
| (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, |
| "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> { |
| let Inst{21} = 1; // overwrite |
| } |
| |
| def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), |
| (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, |
| "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> { |
| let Inst{21} = 1; // overwrite |
| } |
| |
| // Store |
| def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStore_r, |
| "str", "\t$src, $addr", |
| [(store GPR:$src, addrmode2:$addr)]>; |
| |
| // Stores with truncate |
| def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, |
| IIC_iStore_bh_r, "strh", "\t$src, $addr", |
| [(truncstorei16 GPR:$src, addrmode3:$addr)]>; |
| |
| def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, |
| IIC_iStore_bh_r, "strb", "\t$src, $addr", |
| [(truncstorei8 GPR:$src, addrmode2:$addr)]>; |
| |
| // Store doubleword |
| let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in |
| def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr), |
| StMiscFrm, IIC_iStore_d_r, |
| "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>; |
| |
| // Indexed stores |
| def STR_PRE : AI2stwpr<(outs GPR:$base_wb), |
| (ins GPR:$src, GPR:$base, am2offset:$offset), |
| StFrm, IIC_iStore_ru, |
| "str", "\t$src, [$base, $offset]!", "$base = $base_wb", |
| [(set GPR:$base_wb, |
| (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; |
| |
| def STR_POST : AI2stwpo<(outs GPR:$base_wb), |
| (ins GPR:$src, GPR:$base,am2offset:$offset), |
| StFrm, IIC_iStore_ru, |
| "str", "\t$src, [$base], $offset", "$base = $base_wb", |
| [(set GPR:$base_wb, |
| (post_store GPR:$src, GPR:$base, am2offset:$offset))]>; |
| |
| def STRH_PRE : AI3sthpr<(outs GPR:$base_wb), |
| (ins GPR:$src, GPR:$base,am3offset:$offset), |
| StMiscFrm, IIC_iStore_ru, |
| "strh", "\t$src, [$base, $offset]!", "$base = $base_wb", |
| [(set GPR:$base_wb, |
| (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; |
| |
| def STRH_POST: AI3sthpo<(outs GPR:$base_wb), |
| (ins GPR:$src, GPR:$base,am3offset:$offset), |
| StMiscFrm, IIC_iStore_bh_ru, |
| "strh", "\t$src, [$base], $offset", "$base = $base_wb", |
| [(set GPR:$base_wb, (post_truncsti16 GPR:$src, |
| GPR:$base, am3offset:$offset))]>; |
| |
| def STRB_PRE : AI2stbpr<(outs GPR:$base_wb), |
| (ins GPR:$src, GPR:$base,am2offset:$offset), |
| StFrm, IIC_iStore_bh_ru, |
| "strb", "\t$src, [$base, $offset]!", "$base = $base_wb", |
| [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, |
| GPR:$base, am2offset:$offset))]>; |
| |
| def STRB_POST: AI2stbpo<(outs GPR:$base_wb), |
| (ins GPR:$src, GPR:$base,am2offset:$offset), |
| StFrm, IIC_iStore_bh_ru, |
| "strb", "\t$src, [$base], $offset", "$base = $base_wb", |
| [(set GPR:$base_wb, (post_truncsti8 GPR:$src, |
| GPR:$base, am2offset:$offset))]>; |
| |
| // For disassembly only |
| def STRD_PRE : AI3stdpr<(outs GPR:$base_wb), |
| (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset), |
| StMiscFrm, IIC_iStore_d_ru, |
| "strd", "\t$src1, $src2, [$base, $offset]!", |
| "$base = $base_wb", []>; |
| |
| // For disassembly only |
| def STRD_POST: AI3stdpo<(outs GPR:$base_wb), |
| (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset), |
| StMiscFrm, IIC_iStore_d_ru, |
| "strd", "\t$src1, $src2, [$base], $offset", |
| "$base = $base_wb", []>; |
| |
| // STRT, STRBT, and STRHT are for disassembly only. |
| |
| def STRT : AI2stwpo<(outs GPR:$base_wb), |
| (ins GPR:$src, GPR:$base,am2offset:$offset), |
| StFrm, IIC_iStore_ru, |
| "strt", "\t$src, [$base], $offset", "$base = $base_wb", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{21} = 1; // overwrite |
| } |
| |
| def STRBT : AI2stbpo<(outs GPR:$base_wb), |
| (ins GPR:$src, GPR:$base,am2offset:$offset), |
| StFrm, IIC_iStore_bh_ru, |
| "strbt", "\t$src, [$base], $offset", "$base = $base_wb", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{21} = 1; // overwrite |
| } |
| |
| def STRHT: AI3sthpo<(outs GPR:$base_wb), |
| (ins GPR:$src, GPR:$base,am3offset:$offset), |
| StMiscFrm, IIC_iStore_bh_ru, |
| "strht", "\t$src, [$base], $offset", "$base = $base_wb", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{21} = 1; // overwrite |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // Load / store multiple Instructions. |
| // |
| |
| let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { |
| def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, |
| reglist:$dsts, variable_ops), |
| IndexModeNone, LdStMulFrm, IIC_iLoad_m, |
| "ldm${addr:submode}${p}\t$addr, $dsts", "", []>; |
| |
| def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, |
| reglist:$dsts, variable_ops), |
| IndexModeUpd, LdStMulFrm, IIC_iLoad_mu, |
| "ldm${addr:submode}${p}\t$addr!, $dsts", |
| "$addr.addr = $wb", []>; |
| } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq |
| |
| let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { |
| def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p, |
| reglist:$srcs, variable_ops), |
| IndexModeNone, LdStMulFrm, IIC_iStore_m, |
| "stm${addr:submode}${p}\t$addr, $srcs", "", []>; |
| |
| def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, |
| reglist:$srcs, variable_ops), |
| IndexModeUpd, LdStMulFrm, IIC_iStore_mu, |
| "stm${addr:submode}${p}\t$addr!, $srcs", |
| "$addr.addr = $wb", []>; |
| } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq |
| |
| //===----------------------------------------------------------------------===// |
| // Move Instructions. |
| // |
| |
| let neverHasSideEffects = 1 in |
| def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, |
| "mov", "\t$Rd, $Rm", []>, UnaryDP { |
| bits<4> Rd; |
| bits<4> Rm; |
| |
| let Inst{11-4} = 0b00000000; |
| let Inst{25} = 0; |
| let Inst{3-0} = Rm; |
| let Inst{15-12} = Rd; |
| } |
| |
| // A version for the smaller set of tail call registers. |
| let neverHasSideEffects = 1 in |
| def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, |
| IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP { |
| bits<4> Rd; |
| bits<4> Rm; |
| |
| let Inst{11-4} = 0b00000000; |
| let Inst{25} = 0; |
| let Inst{3-0} = Rm; |
| let Inst{15-12} = Rd; |
| } |
| |
| def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins so_reg:$src), |
| DPSoRegFrm, IIC_iMOVsr, |
| "mov", "\t$Rd, $src", [(set GPR:$Rd, so_reg:$src)]>, UnaryDP { |
| let Inst{25} = 0; |
| } |
| |
| let isReMaterializable = 1, isAsCheapAsAMove = 1 in |
| def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi, |
| "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP { |
| bits<4> Rd; |
| bits<12> imm; |
| let Inst{25} = 1; |
| let Inst{15-12} = Rd; |
| let Inst{19-16} = 0b0000; |
| let Inst{11-0} = imm; |
| } |
| |
| let isReMaterializable = 1, isAsCheapAsAMove = 1 in |
| def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src), |
| DPFrm, IIC_iMOVi, |
| "movw", "\t$dst, $src", |
| [(set GPR:$dst, imm0_65535:$src)]>, |
| Requires<[IsARM, HasV6T2]>, UnaryDP { |
| let Inst{20} = 0; |
| let Inst{25} = 1; |
| } |
| |
| let Constraints = "$src = $dst" in |
| def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm), |
| DPFrm, IIC_iMOVi, |
| "movt", "\t$dst, $imm", |
| [(set GPR:$dst, |
| (or (and GPR:$src, 0xffff), |
| lo16AllZero:$imm))]>, UnaryDP, |
| Requires<[IsARM, HasV6T2]> { |
| let Inst{20} = 0; |
| let Inst{25} = 1; |
| } |
| |
| def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, |
| Requires<[IsARM, HasV6T2]>; |
| |
| let Uses = [CPSR] in |
| def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi, |
| "mov", "\t$dst, $src, rrx", |
| [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP; |
| |
| // These aren't really mov instructions, but we have to define them this way |
| // due to flag operands. |
| |
| let Defs = [CPSR] in { |
| def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, |
| IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1", |
| [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP; |
| def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, |
| IIC_iMOVsi, "movs", "\t$dst, $src, asr #1", |
| [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP; |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // Extend Instructions. |
| // |
| |
| // Sign extenders |
| |
| defm SXTB : AI_ext_rrot<0b01101010, |
| "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; |
| defm SXTH : AI_ext_rrot<0b01101011, |
| "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; |
| |
| defm SXTAB : AI_exta_rrot<0b01101010, |
| "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; |
| defm SXTAH : AI_exta_rrot<0b01101011, |
| "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; |
| |
| // For disassembly only |
| defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; |
| |
| // For disassembly only |
| defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; |
| |
| // Zero extenders |
| |
| let AddedComplexity = 16 in { |
| defm UXTB : AI_ext_rrot<0b01101110, |
| "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; |
| defm UXTH : AI_ext_rrot<0b01101111, |
| "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; |
| defm UXTB16 : AI_ext_rrot<0b01101100, |
| "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; |
| |
| // FIXME: This pattern incorrectly assumes the shl operator is a rotate. |
| // The transformation should probably be done as a combiner action |
| // instead so we can include a check for masking back in the upper |
| // eight bits of the source into the lower eight bits of the result. |
| //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), |
| // (UXTB16r_rot GPR:$Src, 24)>; |
| def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), |
| (UXTB16r_rot GPR:$Src, 8)>; |
| |
| defm UXTAB : AI_exta_rrot<0b01101110, "uxtab", |
| BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; |
| defm UXTAH : AI_exta_rrot<0b01101111, "uxtah", |
| BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; |
| } |
| |
| // This isn't safe in general, the add is two 16-bit units, not a 32-bit add. |
| // For disassembly only |
| defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; |
| |
| |
| def SBFX : I<(outs GPR:$dst), |
| (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), |
| AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, |
| "sbfx", "\t$dst, $src, $lsb, $width", "", []>, |
| Requires<[IsARM, HasV6T2]> { |
| let Inst{27-21} = 0b0111101; |
| let Inst{6-4} = 0b101; |
| } |
| |
| def UBFX : I<(outs GPR:$dst), |
| (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), |
| AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, |
| "ubfx", "\t$dst, $src, $lsb, $width", "", []>, |
| Requires<[IsARM, HasV6T2]> { |
| let Inst{27-21} = 0b0111111; |
| let Inst{6-4} = 0b101; |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // Arithmetic Instructions. |
| // |
| |
| defm ADD : AsI1_bin_irs<0b0100, "add", |
| IIC_iALUi, IIC_iALUr, IIC_iALUsr, |
| BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; |
| defm SUB : AsI1_bin_irs<0b0010, "sub", |
| IIC_iALUi, IIC_iALUr, IIC_iALUsr, |
| BinOpFrag<(sub node:$LHS, node:$RHS)>>; |
| |
| // ADD and SUB with 's' bit set. |
| defm ADDS : AI1_bin_s_irs<0b0100, "adds", |
| IIC_iALUi, IIC_iALUr, IIC_iALUsr, |
| BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; |
| defm SUBS : AI1_bin_s_irs<0b0010, "subs", |
| IIC_iALUi, IIC_iALUr, IIC_iALUsr, |
| BinOpFrag<(subc node:$LHS, node:$RHS)>>; |
| |
| defm ADC : AI1_adde_sube_irs<0b0101, "adc", |
| BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>; |
| defm SBC : AI1_adde_sube_irs<0b0110, "sbc", |
| BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>; |
| defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs", |
| BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>; |
| defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs", |
| BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>; |
| |
| def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, |
| IIC_iALUi, "rsb", "\t$dst, $a, $b", |
| [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> { |
| let Inst{25} = 1; |
| } |
| |
| // The reg/reg form is only defined for the disassembler; for codegen it is |
| // equivalent to SUBrr. |
| def RSBrr : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, |
| IIC_iALUr, "rsb", "\t$dst, $a, $b", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{25} = 0; |
| let Inst{11-4} = 0b00000000; |
| } |
| |
| def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, |
| IIC_iALUsr, "rsb", "\t$dst, $a, $b", |
| [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> { |
| let Inst{25} = 0; |
| } |
| |
| // RSB with 's' bit set. |
| let Defs = [CPSR] in { |
| def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, |
| IIC_iALUi, "rsbs", "\t$dst, $a, $b", |
| [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> { |
| let Inst{20} = 1; |
| let Inst{25} = 1; |
| } |
| def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, |
| IIC_iALUsr, "rsbs", "\t$dst, $a, $b", |
| [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> { |
| let Inst{20} = 1; |
| let Inst{25} = 0; |
| } |
| } |
| |
| let Uses = [CPSR] in { |
| def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), |
| DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b", |
| [(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>, |
| Requires<[IsARM]> { |
| let Inst{25} = 1; |
| } |
| // The reg/reg form is only defined for the disassembler; for codegen it is |
| // equivalent to SUBrr. |
| def RSCrr : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, GPR:$b), |
| DPFrm, IIC_iALUr, "rsc", "\t$dst, $a, $b", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{25} = 0; |
| let Inst{11-4} = 0b00000000; |
| } |
| def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), |
| DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b", |
| [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>, |
| Requires<[IsARM]> { |
| let Inst{25} = 0; |
| } |
| } |
| |
| // FIXME: Allow these to be predicated. |
| let Defs = [CPSR], Uses = [CPSR] in { |
| def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), |
| DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b", |
| [(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>, |
| Requires<[IsARM]> { |
| let Inst{20} = 1; |
| let Inst{25} = 1; |
| } |
| def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), |
| DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b", |
| [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>, |
| Requires<[IsARM]> { |
| let Inst{20} = 1; |
| let Inst{25} = 0; |
| } |
| } |
| |
| // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. |
| // The assume-no-carry-in form uses the negation of the input since add/sub |
| // assume opposite meanings of the carry flag (i.e., carry == !borrow). |
| // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory |
| // details. |
| def : ARMPat<(add GPR:$src, so_imm_neg:$imm), |
| (SUBri GPR:$src, so_imm_neg:$imm)>; |
| def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), |
| (SUBSri GPR:$src, so_imm_neg:$imm)>; |
| // The with-carry-in form matches bitwise not instead of the negation. |
| // Effectively, the inverse interpretation of the carry flag already accounts |
| // for part of the negation. |
| def : ARMPat<(adde GPR:$src, so_imm_not:$imm), |
| (SBCri GPR:$src, so_imm_not:$imm)>; |
| |
| // Note: These are implemented in C++ code, because they have to generate |
| // ADD/SUBrs instructions, which use a complex pattern that a xform function |
| // cannot produce. |
| // (mul X, 2^n+1) -> (add (X << n), X) |
| // (mul X, 2^n-1) -> (rsb X, (X << n)) |
| |
| // ARM Arithmetic Instruction -- for disassembly only |
| // GPR:$dst = GPR:$a op GPR:$b |
| class AAI<bits<8> op27_20, bits<4> op7_4, string opc, |
| list<dag> pattern = [/* For disassembly only; pattern left blank */]> |
| : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, IIC_iALUr, |
| opc, "\t$dst, $a, $b", pattern> { |
| let Inst{27-20} = op27_20; |
| let Inst{7-4} = op7_4; |
| } |
| |
| // Saturating add/subtract -- for disassembly only |
| |
| def QADD : AAI<0b00010000, 0b0101, "qadd", |
| [(set GPR:$dst, (int_arm_qadd GPR:$a, GPR:$b))]>; |
| def QADD16 : AAI<0b01100010, 0b0001, "qadd16">; |
| def QADD8 : AAI<0b01100010, 0b1001, "qadd8">; |
| def QASX : AAI<0b01100010, 0b0011, "qasx">; |
| def QDADD : AAI<0b00010100, 0b0101, "qdadd">; |
| def QDSUB : AAI<0b00010110, 0b0101, "qdsub">; |
| def QSAX : AAI<0b01100010, 0b0101, "qsax">; |
| def QSUB : AAI<0b00010010, 0b0101, "qsub", |
| [(set GPR:$dst, (int_arm_qsub GPR:$a, GPR:$b))]>; |
| def QSUB16 : AAI<0b01100010, 0b0111, "qsub16">; |
| def QSUB8 : AAI<0b01100010, 0b1111, "qsub8">; |
| def UQADD16 : AAI<0b01100110, 0b0001, "uqadd16">; |
| def UQADD8 : AAI<0b01100110, 0b1001, "uqadd8">; |
| def UQASX : AAI<0b01100110, 0b0011, "uqasx">; |
| def UQSAX : AAI<0b01100110, 0b0101, "uqsax">; |
| def UQSUB16 : AAI<0b01100110, 0b0111, "uqsub16">; |
| def UQSUB8 : AAI<0b01100110, 0b1111, "uqsub8">; |
| |
| // Signed/Unsigned add/subtract -- for disassembly only |
| |
| def SASX : AAI<0b01100001, 0b0011, "sasx">; |
| def SADD16 : AAI<0b01100001, 0b0001, "sadd16">; |
| def SADD8 : AAI<0b01100001, 0b1001, "sadd8">; |
| def SSAX : AAI<0b01100001, 0b0101, "ssax">; |
| def SSUB16 : AAI<0b01100001, 0b0111, "ssub16">; |
| def SSUB8 : AAI<0b01100001, 0b1111, "ssub8">; |
| def UASX : AAI<0b01100101, 0b0011, "uasx">; |
| def UADD16 : AAI<0b01100101, 0b0001, "uadd16">; |
| def UADD8 : AAI<0b01100101, 0b1001, "uadd8">; |
| def USAX : AAI<0b01100101, 0b0101, "usax">; |
| def USUB16 : AAI<0b01100101, 0b0111, "usub16">; |
| def USUB8 : AAI<0b01100101, 0b1111, "usub8">; |
| |
| // Signed/Unsigned halving add/subtract -- for disassembly only |
| |
| def SHASX : AAI<0b01100011, 0b0011, "shasx">; |
| def SHADD16 : AAI<0b01100011, 0b0001, "shadd16">; |
| def SHADD8 : AAI<0b01100011, 0b1001, "shadd8">; |
| def SHSAX : AAI<0b01100011, 0b0101, "shsax">; |
| def SHSUB16 : AAI<0b01100011, 0b0111, "shsub16">; |
| def SHSUB8 : AAI<0b01100011, 0b1111, "shsub8">; |
| def UHASX : AAI<0b01100111, 0b0011, "uhasx">; |
| def UHADD16 : AAI<0b01100111, 0b0001, "uhadd16">; |
| def UHADD8 : AAI<0b01100111, 0b1001, "uhadd8">; |
| def UHSAX : AAI<0b01100111, 0b0101, "uhsax">; |
| def UHSUB16 : AAI<0b01100111, 0b0111, "uhsub16">; |
| def UHSUB8 : AAI<0b01100111, 0b1111, "uhsub8">; |
| |
| // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only |
| |
| def USAD8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), |
| MulFrm /* for convenience */, NoItinerary, "usad8", |
| "\t$dst, $a, $b", []>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{27-20} = 0b01111000; |
| let Inst{15-12} = 0b1111; |
| let Inst{7-4} = 0b0001; |
| } |
| def USADA8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), |
| MulFrm /* for convenience */, NoItinerary, "usada8", |
| "\t$dst, $a, $b, $acc", []>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{27-20} = 0b01111000; |
| let Inst{7-4} = 0b0001; |
| } |
| |
| // Signed/Unsigned saturate -- for disassembly only |
| |
| def SSAT : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, shift_imm:$sh), |
| SatFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a$sh", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{27-21} = 0b0110101; |
| let Inst{5-4} = 0b01; |
| } |
| |
| def SSAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), SatFrm, |
| NoItinerary, "ssat16", "\t$dst, $bit_pos, $a", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{27-20} = 0b01101010; |
| let Inst{7-4} = 0b0011; |
| } |
| |
| def USAT : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, shift_imm:$sh), |
| SatFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a$sh", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{27-21} = 0b0110111; |
| let Inst{5-4} = 0b01; |
| } |
| |
| def USAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), SatFrm, |
| NoItinerary, "usat16", "\t$dst, $bit_pos, $a", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{27-20} = 0b01101110; |
| let Inst{7-4} = 0b0011; |
| } |
| |
| def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>; |
| def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>; |
| |
| //===----------------------------------------------------------------------===// |
| // Bitwise Instructions. |
| // |
| |
| defm AND : AsI1_bin_irs<0b0000, "and", |
| IIC_iBITi, IIC_iBITr, IIC_iBITsr, |
| BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; |
| defm ANDS : AI1_bin_s_irs<0b0000, "and", |
| IIC_iBITi, IIC_iBITr, IIC_iBITsr, |
| BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>; |
| defm ORR : AsI1_bin_irs<0b1100, "orr", |
| IIC_iBITi, IIC_iBITr, IIC_iBITsr, |
| BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; |
| defm EOR : AsI1_bin_irs<0b0001, "eor", |
| IIC_iBITi, IIC_iBITr, IIC_iBITsr, |
| BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; |
| defm BIC : AsI1_bin_irs<0b1110, "bic", |
| IIC_iBITi, IIC_iBITr, IIC_iBITsr, |
| BinOpFrag<(and node:$LHS, (not node:$RHS))>>; |
| |
| def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), |
| AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, |
| "bfc", "\t$dst, $imm", "$src = $dst", |
| [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>, |
| Requires<[IsARM, HasV6T2]> { |
| let Inst{27-21} = 0b0111110; |
| let Inst{6-0} = 0b0011111; |
| } |
| |
| // A8.6.18 BFI - Bitfield insert (Encoding A1) |
| def BFI : I<(outs GPR:$dst), (ins GPR:$src, GPR:$val, bf_inv_mask_imm:$imm), |
| AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, |
| "bfi", "\t$dst, $val, $imm", "$src = $dst", |
| [(set GPR:$dst, (ARMbfi GPR:$src, GPR:$val, |
| bf_inv_mask_imm:$imm))]>, |
| Requires<[IsARM, HasV6T2]> { |
| let Inst{27-21} = 0b0111110; |
| let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 |
| } |
| |
| def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMVNr, |
| "mvn", "\t$dst, $src", |
| [(set GPR:$dst, (not GPR:$src))]>, UnaryDP { |
| let Inst{25} = 0; |
| let Inst{11-4} = 0b00000000; |
| } |
| def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm, |
| IIC_iMVNsr, "mvn", "\t$dst, $src", |
| [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP { |
| let Inst{25} = 0; |
| } |
| let isReMaterializable = 1, isAsCheapAsAMove = 1 in |
| def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm, |
| IIC_iMVNi, "mvn", "\t$dst, $imm", |
| [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP { |
| let Inst{25} = 1; |
| } |
| |
| def : ARMPat<(and GPR:$src, so_imm_not:$imm), |
| (BICri GPR:$src, so_imm_not:$imm)>; |
| |
| //===----------------------------------------------------------------------===// |
| // Multiply Instructions. |
| // |
| |
| let isCommutable = 1 in |
| def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), |
| IIC_iMUL32, "mul", "\t$dst, $a, $b", |
| [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; |
| |
| def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), |
| IIC_iMAC32, "mla", "\t$dst, $a, $b, $c", |
| [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; |
| |
| def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), |
| IIC_iMAC32, "mls", "\t$dst, $a, $b, $c", |
| [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>, |
| Requires<[IsARM, HasV6T2]>; |
| |
| // Extra precision multiplies with low / high results |
| let neverHasSideEffects = 1 in { |
| let isCommutable = 1 in { |
| def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst), |
| (ins GPR:$a, GPR:$b), IIC_iMUL64, |
| "smull", "\t$ldst, $hdst, $a, $b", []>; |
| |
| def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst), |
| (ins GPR:$a, GPR:$b), IIC_iMUL64, |
| "umull", "\t$ldst, $hdst, $a, $b", []>; |
| } |
| |
| // Multiply + accumulate |
| def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst), |
| (ins GPR:$a, GPR:$b), IIC_iMAC64, |
| "smlal", "\t$ldst, $hdst, $a, $b", []>; |
| |
| def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst), |
| (ins GPR:$a, GPR:$b), IIC_iMAC64, |
| "umlal", "\t$ldst, $hdst, $a, $b", []>; |
| |
| def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst), |
| (ins GPR:$a, GPR:$b), IIC_iMAC64, |
| "umaal", "\t$ldst, $hdst, $a, $b", []>, |
| Requires<[IsARM, HasV6]>; |
| } // neverHasSideEffects |
| |
| // Most significant word multiply |
| def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b), |
| IIC_iMUL32, "smmul", "\t$dst, $a, $b", |
| [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{7-4} = 0b0001; |
| let Inst{15-12} = 0b1111; |
| } |
| |
| def SMMULR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b), |
| IIC_iMUL32, "smmulr", "\t$dst, $a, $b", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{7-4} = 0b0011; // R = 1 |
| let Inst{15-12} = 0b1111; |
| } |
| |
| def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), |
| IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c", |
| [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{7-4} = 0b0001; |
| } |
| |
| def SMMLAR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), |
| IIC_iMAC32, "smmlar", "\t$dst, $a, $b, $c", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{7-4} = 0b0011; // R = 1 |
| } |
| |
| def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), |
| IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c", |
| [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{7-4} = 0b1101; |
| } |
| |
| def SMMLSR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), |
| IIC_iMAC32, "smmlsr", "\t$dst, $a, $b, $c", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{7-4} = 0b1111; // R = 1 |
| } |
| |
| multiclass AI_smul<string opc, PatFrag opnode> { |
| def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), |
| IIC_iMUL16, !strconcat(opc, "bb"), "\t$dst, $a, $b", |
| [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), |
| (sext_inreg GPR:$b, i16)))]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 0; |
| let Inst{6} = 0; |
| } |
| |
| def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), |
| IIC_iMUL16, !strconcat(opc, "bt"), "\t$dst, $a, $b", |
| [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), |
| (sra GPR:$b, (i32 16))))]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 0; |
| let Inst{6} = 1; |
| } |
| |
| def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), |
| IIC_iMUL16, !strconcat(opc, "tb"), "\t$dst, $a, $b", |
| [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), |
| (sext_inreg GPR:$b, i16)))]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 1; |
| let Inst{6} = 0; |
| } |
| |
| def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), |
| IIC_iMUL16, !strconcat(opc, "tt"), "\t$dst, $a, $b", |
| [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), |
| (sra GPR:$b, (i32 16))))]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 1; |
| let Inst{6} = 1; |
| } |
| |
| def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), |
| IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b", |
| [(set GPR:$dst, (sra (opnode GPR:$a, |
| (sext_inreg GPR:$b, i16)), (i32 16)))]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 1; |
| let Inst{6} = 0; |
| } |
| |
| def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), |
| IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b", |
| [(set GPR:$dst, (sra (opnode GPR:$a, |
| (sra GPR:$b, (i32 16))), (i32 16)))]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 1; |
| let Inst{6} = 1; |
| } |
| } |
| |
| |
| multiclass AI_smla<string opc, PatFrag opnode> { |
| def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), |
| IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc", |
| [(set GPR:$dst, (add GPR:$acc, |
| (opnode (sext_inreg GPR:$a, i16), |
| (sext_inreg GPR:$b, i16))))]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 0; |
| let Inst{6} = 0; |
| } |
| |
| def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), |
| IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc", |
| [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), |
| (sra GPR:$b, (i32 16)))))]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 0; |
| let Inst{6} = 1; |
| } |
| |
| def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), |
| IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc", |
| [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), |
| (sext_inreg GPR:$b, i16))))]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 1; |
| let Inst{6} = 0; |
| } |
| |
| def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), |
| IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc", |
| [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), |
| (sra GPR:$b, (i32 16)))))]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 1; |
| let Inst{6} = 1; |
| } |
| |
| def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), |
| IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc", |
| [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, |
| (sext_inreg GPR:$b, i16)), (i32 16))))]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 0; |
| let Inst{6} = 0; |
| } |
| |
| def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), |
| IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc", |
| [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, |
| (sra GPR:$b, (i32 16))), (i32 16))))]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 0; |
| let Inst{6} = 1; |
| } |
| } |
| |
| defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; |
| defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; |
| |
| // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only |
| def SMLALBB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b), |
| IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 0; |
| let Inst{6} = 0; |
| } |
| |
| def SMLALBT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b), |
| IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 0; |
| let Inst{6} = 1; |
| } |
| |
| def SMLALTB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b), |
| IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 1; |
| let Inst{6} = 0; |
| } |
| |
| def SMLALTT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b), |
| IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV5TE]> { |
| let Inst{5} = 1; |
| let Inst{6} = 1; |
| } |
| |
| // Helper class for AI_smld -- for disassembly only |
| class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, |
| InstrItinClass itin, string opc, string asm> |
| : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> { |
| let Inst{4} = 1; |
| let Inst{5} = swap; |
| let Inst{6} = sub; |
| let Inst{7} = 0; |
| let Inst{21-20} = 0b00; |
| let Inst{22} = long; |
| let Inst{27-23} = 0b01110; |
| } |
| |
| multiclass AI_smld<bit sub, string opc> { |
| |
| def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), |
| NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b, $acc">; |
| |
| def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), |
| NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b, $acc">; |
| |
| def LD : AMulDualI<1, sub, 0, (outs GPR:$ldst,GPR:$hdst), (ins GPR:$a,GPR:$b), |
| NoItinerary, !strconcat(opc, "ld"), "\t$ldst, $hdst, $a, $b">; |
| |
| def LDX : AMulDualI<1, sub, 1, (outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b), |
| NoItinerary, !strconcat(opc, "ldx"),"\t$ldst, $hdst, $a, $b">; |
| |
| } |
| |
| defm SMLA : AI_smld<0, "smla">; |
| defm SMLS : AI_smld<1, "smls">; |
| |
| multiclass AI_sdml<bit sub, string opc> { |
| |
| def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), |
| NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b"> { |
| let Inst{15-12} = 0b1111; |
| } |
| |
| def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b), |
| NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b"> { |
| let Inst{15-12} = 0b1111; |
| } |
| |
| } |
| |
| defm SMUA : AI_sdml<0, "smua">; |
| defm SMUS : AI_sdml<1, "smus">; |
| |
| //===----------------------------------------------------------------------===// |
| // Misc. Arithmetic Instructions. |
| // |
| |
| def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, |
| "clz", "\t$dst, $src", |
| [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> { |
| let Inst{7-4} = 0b0001; |
| let Inst{11-8} = 0b1111; |
| let Inst{19-16} = 0b1111; |
| } |
| |
| def RBIT : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, |
| "rbit", "\t$dst, $src", |
| [(set GPR:$dst, (ARMrbit GPR:$src))]>, |
| Requires<[IsARM, HasV6T2]> { |
| let Inst{7-4} = 0b0011; |
| let Inst{11-8} = 0b1111; |
| let Inst{19-16} = 0b1111; |
| } |
| |
| def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, |
| "rev", "\t$dst, $src", |
| [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> { |
| let Inst{7-4} = 0b0011; |
| let Inst{11-8} = 0b1111; |
| let Inst{19-16} = 0b1111; |
| } |
| |
| def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, |
| "rev16", "\t$dst, $src", |
| [(set GPR:$dst, |
| (or (and (srl GPR:$src, (i32 8)), 0xFF), |
| (or (and (shl GPR:$src, (i32 8)), 0xFF00), |
| (or (and (srl GPR:$src, (i32 8)), 0xFF0000), |
| (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{7-4} = 0b1011; |
| let Inst{11-8} = 0b1111; |
| let Inst{19-16} = 0b1111; |
| } |
| |
| def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, |
| "revsh", "\t$dst, $src", |
| [(set GPR:$dst, |
| (sext_inreg |
| (or (srl (and GPR:$src, 0xFF00), (i32 8)), |
| (shl GPR:$src, (i32 8))), i16))]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{7-4} = 0b1011; |
| let Inst{11-8} = 0b1111; |
| let Inst{19-16} = 0b1111; |
| } |
| |
| def lsl_shift_imm : SDNodeXForm<imm, [{ |
| unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue()); |
| return CurDAG->getTargetConstant(Sh, MVT::i32); |
| }]>; |
| |
| def lsl_amt : PatLeaf<(i32 imm), [{ |
| return (N->getZExtValue() < 32); |
| }], lsl_shift_imm>; |
| |
| def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst), |
| (ins GPR:$src1, GPR:$src2, shift_imm:$sh), |
| IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2$sh", |
| [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), |
| (and (shl GPR:$src2, lsl_amt:$sh), |
| 0xFFFF0000)))]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{6-4} = 0b001; |
| } |
| |
| // Alternate cases for PKHBT where identities eliminate some nodes. |
| def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), |
| (PKHBT GPR:$src1, GPR:$src2, 0)>; |
| def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$sh)), |
| (PKHBT GPR:$src1, GPR:$src2, (lsl_shift_imm imm16_31:$sh))>; |
| |
| def asr_shift_imm : SDNodeXForm<imm, [{ |
| unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue()); |
| return CurDAG->getTargetConstant(Sh, MVT::i32); |
| }]>; |
| |
| def asr_amt : PatLeaf<(i32 imm), [{ |
| return (N->getZExtValue() <= 32); |
| }], asr_shift_imm>; |
| |
| // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and |
| // will match the pattern below. |
| def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst), |
| (ins GPR:$src1, GPR:$src2, shift_imm:$sh), |
| IIC_iBITsi, "pkhtb", "\t$dst, $src1, $src2$sh", |
| [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), |
| (and (sra GPR:$src2, asr_amt:$sh), |
| 0xFFFF)))]>, |
| Requires<[IsARM, HasV6]> { |
| let Inst{6-4} = 0b101; |
| } |
| |
| // Alternate cases for PKHTB where identities eliminate some nodes. Note that |
| // a shift amount of 0 is *not legal* here, it is PKHBT instead. |
| def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)), |
| (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>; |
| def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), |
| (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)), |
| (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>; |
| |
| //===----------------------------------------------------------------------===// |
| // Comparison Instructions... |
| // |
| |
| defm CMP : AI1_cmp_irs<0b1010, "cmp", |
| IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, |
| BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; |
| |
| // FIXME: We have to be careful when using the CMN instruction and comparison |
| // with 0. One would expect these two pieces of code should give identical |
| // results: |
| // |
| // rsbs r1, r1, 0 |
| // cmp r0, r1 |
| // mov r0, #0 |
| // it ls |
| // mov r0, #1 |
| // |
| // and: |
| // |
| // cmn r0, r1 |
| // mov r0, #0 |
| // it ls |
| // mov r0, #1 |
| // |
| // However, the CMN gives the *opposite* result when r1 is 0. This is because |
| // the carry flag is set in the CMP case but not in the CMN case. In short, the |
| // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the |
| // value of r0 and the carry bit (because the "carry bit" parameter to |
| // AddWithCarry is defined as 1 in this case, the carry flag will always be set |
| // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is |
| // never a "carry" when this AddWithCarry is performed (because the "carry bit" |
| // parameter to AddWithCarry is defined as 0). |
| // |
| // When x is 0 and unsigned: |
| // |
| // x = 0 |
| // ~x = 0xFFFF FFFF |
| // ~x + 1 = 0x1 0000 0000 |
| // (-x = 0) != (0x1 0000 0000 = ~x + 1) |
| // |
| // Therefore, we should disable CMN when comparing against zero, until we can |
| // limit when the CMN instruction is used (when we know that the RHS is not 0 or |
| // when it's a comparison which doesn't look at the 'carry' flag). |
| // |
| // (See the ARM docs for the "AddWithCarry" pseudo-code.) |
| // |
| // This is related to <rdar://problem/7569620>. |
| // |
| //defm CMN : AI1_cmp_irs<0b1011, "cmn", |
| // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; |
| |
| // Note that TST/TEQ don't set all the same flags that CMP does! |
| defm TST : AI1_cmp_irs<0b1000, "tst", |
| IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, |
| BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>; |
| defm TEQ : AI1_cmp_irs<0b1001, "teq", |
| IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, |
| BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>; |
| |
| defm CMPz : AI1_cmp_irs<0b1010, "cmp", |
| IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, |
| BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>; |
| defm CMNz : AI1_cmp_irs<0b1011, "cmn", |
| IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, |
| BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>; |
| |
| //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), |
| // (CMNri GPR:$src, so_imm_neg:$imm)>; |
| |
| def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm), |
| (CMNzri GPR:$src, so_imm_neg:$imm)>; |
| |
| // Pseudo i64 compares for some floating point compares. |
| let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, |
| Defs = [CPSR] in { |
| def BCCi64 : PseudoInst<(outs), |
| (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), |
| IIC_Br, "", |
| [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>; |
| |
| def BCCZi64 : PseudoInst<(outs), |
| (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, "", |
| [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>; |
| } // usesCustomInserter |
| |
| |
| // Conditional moves |
| // FIXME: should be able to write a pattern for ARMcmov, but can't use |
| // a two-value operand where a dag node expects two operands. :( |
| // FIXME: These should all be pseudo-instructions that get expanded to |
| // the normal MOV instructions. That would fix the dependency on |
| // special casing them in tblgen. |
| let neverHasSideEffects = 1 in { |
| def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm, |
| IIC_iCMOVr, "mov", "\t$Rd, $Rm", |
| [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>, |
| RegConstraint<"$false = $Rd">, UnaryDP { |
| bits<4> Rd; |
| bits<4> Rm; |
| |
| let Inst{11-4} = 0b00000000; |
| let Inst{25} = 0; |
| let Inst{3-0} = Rm; |
| let Inst{15-12} = Rd; |
| let Inst{11-4} = 0b00000000; |
| let Inst{25} = 0; |
| } |
| |
| def MOVCCs : AI1<0b1101, (outs GPR:$dst), |
| (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr, |
| "mov", "\t$dst, $true", |
| [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>, |
| RegConstraint<"$false = $dst">, UnaryDP { |
| let Inst{25} = 0; |
| } |
| |
| def MOVCCi16 : AI1<0b1000, (outs GPR:$dst), (ins GPR:$false, i32imm:$src), |
| DPFrm, IIC_iMOVi, |
| "movw", "\t$dst, $src", |
| []>, |
| RegConstraint<"$false = $dst">, Requires<[IsARM, HasV6T2]>, |
| UnaryDP { |
| let Inst{20} = 0; |
| let Inst{25} = 1; |
| } |
| |
| def MOVCCi : AI1<0b1101, (outs GPR:$dst), |
| (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi, |
| "mov", "\t$dst, $true", |
| [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>, |
| RegConstraint<"$false = $dst">, UnaryDP { |
| let Inst{25} = 1; |
| } |
| } // neverHasSideEffects |
| |
| //===----------------------------------------------------------------------===// |
| // Atomic operations intrinsics |
| // |
| |
| // memory barriers protect the atomic sequences |
| let hasSideEffects = 1 in { |
| def DMBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dmb", "", |
| [(ARMMemBarrier)]>, Requires<[IsARM, HasDB]> { |
| let Inst{31-4} = 0xf57ff05; |
| // FIXME: add support for options other than a full system DMB |
| // See DMB disassembly-only variants below. |
| let Inst{3-0} = 0b1111; |
| } |
| |
| def DSBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dsb", "", |
| [(ARMSyncBarrier)]>, Requires<[IsARM, HasDB]> { |
| let Inst{31-4} = 0xf57ff04; |
| // FIXME: add support for options other than a full system DSB |
| // See DSB disassembly-only variants below. |
| let Inst{3-0} = 0b1111; |
| } |
| |
| def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary, |
| "mcr", "\tp15, 0, $zero, c7, c10, 5", |
| [(ARMMemBarrierMCR GPR:$zero)]>, |
| Requires<[IsARM, HasV6]> { |
| // FIXME: add support for options other than a full system DMB |
| // FIXME: add encoding |
| } |
| |
| def DSB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary, |
| "mcr", "\tp15, 0, $zero, c7, c10, 4", |
| [(ARMSyncBarrierMCR GPR:$zero)]>, |
| Requires<[IsARM, HasV6]> { |
| // FIXME: add support for options other than a full system DSB |
| // FIXME: add encoding |
| } |
| } |
| |
| // Memory Barrier Operations Variants -- for disassembly only |
| |
| def memb_opt : Operand<i32> { |
| let PrintMethod = "printMemBOption"; |
| } |
| |
| class AMBI<bits<4> op7_4, string opc> |
| : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, opc, "\t$opt", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasDB]> { |
| let Inst{31-8} = 0xf57ff0; |
| let Inst{7-4} = op7_4; |
| } |
| |
| // These DMB variants are for disassembly only. |
| def DMBvar : AMBI<0b0101, "dmb">; |
| |
| // These DSB variants are for disassembly only. |
| def DSBvar : AMBI<0b0100, "dsb">; |
| |
| // ISB has only full system option -- for disassembly only |
| def ISBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>, |
| Requires<[IsARM, HasDB]> { |
| let Inst{31-4} = 0xf57ff06; |
| let Inst{3-0} = 0b1111; |
| } |
| |
| let usesCustomInserter = 1 in { |
| let Uses = [CPSR] in { |
| def ATOMIC_LOAD_ADD_I8 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_SUB_I8 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_AND_I8 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_OR_I8 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_XOR_I8 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_NAND_I8 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_ADD_I16 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_SUB_I16 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_AND_I16 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_OR_I16 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_XOR_I16 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_NAND_I16 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_ADD_I32 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_SUB_I32 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_AND_I32 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_OR_I32 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_XOR_I32 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>; |
| def ATOMIC_LOAD_NAND_I32 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", |
| [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>; |
| |
| def ATOMIC_SWAP_I8 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "", |
| [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>; |
| def ATOMIC_SWAP_I16 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "", |
| [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>; |
| def ATOMIC_SWAP_I32 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "", |
| [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>; |
| |
| def ATOMIC_CMP_SWAP_I8 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "", |
| [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>; |
| def ATOMIC_CMP_SWAP_I16 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "", |
| [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>; |
| def ATOMIC_CMP_SWAP_I32 : PseudoInst< |
| (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "", |
| [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>; |
| } |
| } |
| |
| let mayLoad = 1 in { |
| def LDREXB : AIldrex<0b10, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary, |
| "ldrexb", "\t$dest, [$ptr]", |
| []>; |
| def LDREXH : AIldrex<0b11, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary, |
| "ldrexh", "\t$dest, [$ptr]", |
| []>; |
| def LDREX : AIldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary, |
| "ldrex", "\t$dest, [$ptr]", |
| []>; |
| def LDREXD : AIldrex<0b01, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr), |
| NoItinerary, |
| "ldrexd", "\t$dest, $dest2, [$ptr]", |
| []>; |
| } |
| |
| let mayStore = 1, Constraints = "@earlyclobber $success" in { |
| def STREXB : AIstrex<0b10, (outs GPR:$success), (ins GPR:$src, GPR:$ptr), |
| NoItinerary, |
| "strexb", "\t$success, $src, [$ptr]", |
| []>; |
| def STREXH : AIstrex<0b11, (outs GPR:$success), (ins GPR:$src, GPR:$ptr), |
| NoItinerary, |
| "strexh", "\t$success, $src, [$ptr]", |
| []>; |
| def STREX : AIstrex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr), |
| NoItinerary, |
| "strex", "\t$success, $src, [$ptr]", |
| []>; |
| def STREXD : AIstrex<0b01, (outs GPR:$success), |
| (ins GPR:$src, GPR:$src2, GPR:$ptr), |
| NoItinerary, |
| "strexd", "\t$success, $src, $src2, [$ptr]", |
| []>; |
| } |
| |
| // Clear-Exclusive is for disassembly only. |
| def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", |
| [/* For disassembly only; pattern left blank */]>, |
| Requires<[IsARM, HasV7]> { |
| let Inst{31-20} = 0xf57; |
| let Inst{7-4} = 0b0001; |
| } |
| |
| // SWP/SWPB are deprecated in V6/V7 and for disassembly only. |
| let mayLoad = 1 in { |
| def SWP : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary, |
| "swp", "\t$dst, $src, [$ptr]", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{27-23} = 0b00010; |
| let Inst{22} = 0; // B = 0 |
| let Inst{21-20} = 0b00; |
| let Inst{7-4} = 0b1001; |
| } |
| |
| def SWPB : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary, |
| "swpb", "\t$dst, $src, [$ptr]", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{27-23} = 0b00010; |
| let Inst{22} = 1; // B = 1 |
| let Inst{21-20} = 0b00; |
| let Inst{7-4} = 0b1001; |
| } |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // TLS Instructions |
| // |
| |
| // __aeabi_read_tp preserves the registers r1-r3. |
| let isCall = 1, |
| Defs = [R0, R12, LR, CPSR] in { |
| def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br, |
| "bl\t__aeabi_read_tp", |
| [(set R0, ARMthread_pointer)]>; |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // SJLJ Exception handling intrinsics |
| // eh_sjlj_setjmp() is an instruction sequence to store the return |
| // address and save #0 in R0 for the non-longjmp case. |
| // Since by its nature we may be coming from some other function to get |
| // here, and we're using the stack frame for the containing function to |
| // save/restore registers, we can't keep anything live in regs across |
| // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon |
| // when we get here from a longjmp(). We force everthing out of registers |
| // except for our own input by listing the relevant registers in Defs. By |
| // doing so, we also cause the prologue/epilogue code to actively preserve |
| // all of the callee-saved resgisters, which is exactly what we want. |
| // A constant value is passed in $val, and we use the location as a scratch. |
| let Defs = |
| [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0, |
| D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, |
| D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, |
| D31 ], hasSideEffects = 1, isBarrier = 1 in { |
| def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val), |
| AddrModeNone, SizeSpecial, IndexModeNone, |
| Pseudo, NoItinerary, "", "", |
| [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, |
| Requires<[IsARM, HasVFP2]>; |
| } |
| |
| let Defs = |
| [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ], |
| hasSideEffects = 1, isBarrier = 1 in { |
| def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val), |
| AddrModeNone, SizeSpecial, IndexModeNone, |
| Pseudo, NoItinerary, "", "", |
| [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, |
| Requires<[IsARM, NoVFP]>; |
| } |
| |
| // FIXME: Non-Darwin version(s) |
| let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, |
| Defs = [ R7, LR, SP ] in { |
| def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), |
| AddrModeNone, SizeSpecial, IndexModeNone, |
| Pseudo, NoItinerary, "", "", |
| [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, |
| Requires<[IsARM, IsDarwin]>; |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // Non-Instruction Patterns |
| // |
| |
| // Large immediate handling. |
| |
| // Two piece so_imms. |
| // FIXME: Expand this in ARMExpandPseudoInsts. |
| // FIXME: Remove this when we can do generalized remat. |
| let isReMaterializable = 1 in |
| def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), |
| Pseudo, IIC_iMOVix2, |
| "mov", "\t$dst, $src", |
| [(set GPR:$dst, so_imm2part:$src)]>, |
| Requires<[IsARM, NoV6T2]>; |
| |
| def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS), |
| (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)), |
| (so_imm2part_2 imm:$RHS))>; |
| def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS), |
| (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)), |
| (so_imm2part_2 imm:$RHS))>; |
| def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS), |
| (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)), |
| (so_imm2part_2 imm:$RHS))>; |
| def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS), |
| (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)), |
| (so_neg_imm2part_2 imm:$RHS))>; |
| |
| // 32-bit immediate using movw + movt. |
| // This is a single pseudo instruction, the benefit is that it can be remat'd |
| // as a single unit instead of having to handle reg inputs. |
| // FIXME: Remove this when we can do generalized remat. |
| let isReMaterializable = 1 in |
| def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, "", |
| [(set GPR:$dst, (i32 imm:$src))]>, |
| Requires<[IsARM, HasV6T2]>; |
| |
| // ConstantPool, GlobalAddress, and JumpTable |
| def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>, |
| Requires<[IsARM, DontUseMovt]>; |
| def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; |
| def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, |
| Requires<[IsARM, UseMovt]>; |
| def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), |
| (LEApcrelJT tjumptable:$dst, imm:$id)>; |
| |
| // TODO: add,sub,and, 3-instr forms? |
| |
| // Tail calls |
| def : ARMPat<(ARMtcret tcGPR:$dst), |
| (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>; |
| |
| def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)), |
| (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>; |
| |
| def : ARMPat<(ARMtcret (i32 texternalsym:$dst)), |
| (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>; |
| |
| def : ARMPat<(ARMtcret tcGPR:$dst), |
| (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>; |
| |
| def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)), |
| (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>; |
| |
| def : ARMPat<(ARMtcret (i32 texternalsym:$dst)), |
| (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>; |
| |
| // Direct calls |
| def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>, |
| Requires<[IsARM, IsNotDarwin]>; |
| def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>, |
| Requires<[IsARM, IsDarwin]>; |
| |
| // zextload i1 -> zextload i8 |
| def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; |
| |
| // extload -> zextload |
| def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; |
| def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>; |
| def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; |
| |
| def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; |
| def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; |
| |
| // smul* and smla* |
| def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), |
| (sra (shl GPR:$b, (i32 16)), (i32 16))), |
| (SMULBB GPR:$a, GPR:$b)>; |
| def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), |
| (SMULBB GPR:$a, GPR:$b)>; |
| def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), |
| (sra GPR:$b, (i32 16))), |
| (SMULBT GPR:$a, GPR:$b)>; |
| def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), |
| (SMULBT GPR:$a, GPR:$b)>; |
| def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), |
| (sra (shl GPR:$b, (i32 16)), (i32 16))), |
| (SMULTB GPR:$a, GPR:$b)>; |
| def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), |
| (SMULTB GPR:$a, GPR:$b)>; |
| def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), |
| (i32 16)), |
| (SMULWB GPR:$a, GPR:$b)>; |
| def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)), |
| (SMULWB GPR:$a, GPR:$b)>; |
| |
| def : ARMV5TEPat<(add GPR:$acc, |
| (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), |
| (sra (shl GPR:$b, (i32 16)), (i32 16)))), |
| (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; |
| def : ARMV5TEPat<(add GPR:$acc, |
| (mul sext_16_node:$a, sext_16_node:$b)), |
| (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; |
| def : ARMV5TEPat<(add GPR:$acc, |
| (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), |
| (sra GPR:$b, (i32 16)))), |
| (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; |
| def : ARMV5TEPat<(add GPR:$acc, |
| (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), |
| (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; |
| def : ARMV5TEPat<(add GPR:$acc, |
| (mul (sra GPR:$a, (i32 16)), |
| (sra (shl GPR:$b, (i32 16)), (i32 16)))), |
| (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; |
| def : ARMV5TEPat<(add GPR:$acc, |
| (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), |
| (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; |
| def : ARMV5TEPat<(add GPR:$acc, |
| (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), |
| (i32 16))), |
| (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; |
| def : ARMV5TEPat<(add GPR:$acc, |
| (sra (mul GPR:$a, sext_16_node:$b), (i32 16))), |
| (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; |
| |
| //===----------------------------------------------------------------------===// |
| // Thumb Support |
| // |
| |
| include "ARMInstrThumb.td" |
| |
| //===----------------------------------------------------------------------===// |
| // Thumb2 Support |
| // |
| |
| include "ARMInstrThumb2.td" |
| |
| //===----------------------------------------------------------------------===// |
| // Floating Point Support |
| // |
| |
| include "ARMInstrVFP.td" |
| |
| //===----------------------------------------------------------------------===// |
| // Advanced SIMD (NEON) Support |
| // |
| |
| include "ARMInstrNEON.td" |
| |
| //===----------------------------------------------------------------------===// |
| // Coprocessor Instructions. For disassembly only. |
| // |
| |
| def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, |
| nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), |
| NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{4} = 0; |
| } |
| |
| def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, |
| nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), |
| NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{31-28} = 0b1111; |
| let Inst{4} = 0; |
| } |
| |
| class ACI<dag oops, dag iops, string opc, string asm> |
| : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary, |
| opc, asm, "", [/* For disassembly only; pattern left blank */]> { |
| let Inst{27-25} = 0b110; |
| } |
| |
| multiclass LdStCop<bits<4> op31_28, bit load, string opc> { |
| |
| def _OFFSET : ACI<(outs), |
| (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), |
| opc, "\tp$cop, cr$CRd, $addr"> { |
| let Inst{31-28} = op31_28; |
| let Inst{24} = 1; // P = 1 |
| let Inst{21} = 0; // W = 0 |
| let Inst{22} = 0; // D = 0 |
| let Inst{20} = load; |
| } |
| |
| def _PRE : ACI<(outs), |
| (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), |
| opc, "\tp$cop, cr$CRd, $addr!"> { |
| let Inst{31-28} = op31_28; |
| let Inst{24} = 1; // P = 1 |
| let Inst{21} = 1; // W = 1 |
| let Inst{22} = 0; // D = 0 |
| let Inst{20} = load; |
| } |
| |
| def _POST : ACI<(outs), |
| (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset), |
| opc, "\tp$cop, cr$CRd, [$base], $offset"> { |
| let Inst{31-28} = op31_28; |
| let Inst{24} = 0; // P = 0 |
| let Inst{21} = 1; // W = 1 |
| let Inst{22} = 0; // D = 0 |
| let Inst{20} = load; |
| } |
| |
| def _OPTION : ACI<(outs), |
| (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option), |
| opc, "\tp$cop, cr$CRd, [$base], $option"> { |
| let Inst{31-28} = op31_28; |
| let Inst{24} = 0; // P = 0 |
| let Inst{23} = 1; // U = 1 |
| let Inst{21} = 0; // W = 0 |
| let Inst{22} = 0; // D = 0 |
| let Inst{20} = load; |
| } |
| |
| def L_OFFSET : ACI<(outs), |
| (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), |
| !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> { |
| let Inst{31-28} = op31_28; |
| let Inst{24} = 1; // P = 1 |
| let Inst{21} = 0; // W = 0 |
| let Inst{22} = 1; // D = 1 |
| let Inst{20} = load; |
| } |
| |
| def L_PRE : ACI<(outs), |
| (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), |
| !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> { |
| let Inst{31-28} = op31_28; |
| let Inst{24} = 1; // P = 1 |
| let Inst{21} = 1; // W = 1 |
| let Inst{22} = 1; // D = 1 |
| let Inst{20} = load; |
| } |
| |
| def L_POST : ACI<(outs), |
| (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset), |
| !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> { |
| let Inst{31-28} = op31_28; |
| let Inst{24} = 0; // P = 0 |
| let Inst{21} = 1; // W = 1 |
| let Inst{22} = 1; // D = 1 |
| let Inst{20} = load; |
| } |
| |
| def L_OPTION : ACI<(outs), |
| (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option), |
| !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> { |
| let Inst{31-28} = op31_28; |
| let Inst{24} = 0; // P = 0 |
| let Inst{23} = 1; // U = 1 |
| let Inst{21} = 0; // W = 0 |
| let Inst{22} = 1; // D = 1 |
| let Inst{20} = load; |
| } |
| } |
| |
| defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">; |
| defm LDC2 : LdStCop<0b1111, 1, "ldc2">; |
| defm STC : LdStCop<{?,?,?,?}, 0, "stc">; |
| defm STC2 : LdStCop<0b1111, 0, "stc2">; |
| |
| def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, |
| GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), |
| NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{20} = 0; |
| let Inst{4} = 1; |
| } |
| |
| def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, |
| GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), |
| NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{31-28} = 0b1111; |
| let Inst{20} = 0; |
| let Inst{4} = 1; |
| } |
| |
| def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, |
| GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), |
| NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{20} = 1; |
| let Inst{4} = 1; |
| } |
| |
| def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, |
| GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), |
| NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{31-28} = 0b1111; |
| let Inst{20} = 1; |
| let Inst{4} = 1; |
| } |
| |
| def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, |
| GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), |
| NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{23-20} = 0b0100; |
| } |
| |
| def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, |
| GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), |
| NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{31-28} = 0b1111; |
| let Inst{23-20} = 0b0100; |
| } |
| |
| def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, |
| GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), |
| NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{23-20} = 0b0101; |
| } |
| |
| def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, |
| GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), |
| NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{31-28} = 0b1111; |
| let Inst{23-20} = 0b0101; |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // Move between special register and ARM core register -- for disassembly only |
| // |
| |
| def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{23-20} = 0b0000; |
| let Inst{7-4} = 0b0000; |
| } |
| |
| def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{23-20} = 0b0100; |
| let Inst{7-4} = 0b0000; |
| } |
| |
| def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, |
| "msr", "\tcpsr$mask, $src", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{23-20} = 0b0010; |
| let Inst{7-4} = 0b0000; |
| } |
| |
| def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary, |
| "msr", "\tcpsr$mask, $a", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{23-20} = 0b0010; |
| let Inst{7-4} = 0b0000; |
| } |
| |
| def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, |
| "msr", "\tspsr$mask, $src", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{23-20} = 0b0110; |
| let Inst{7-4} = 0b0000; |
| } |
| |
| def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary, |
| "msr", "\tspsr$mask, $a", |
| [/* For disassembly only; pattern left blank */]> { |
| let Inst{23-20} = 0b0110; |
| let Inst{7-4} = 0b0000; |
| } |