commit c23197a26f34f559ea9797de51e187087c039c42
author Torok Edwin <edwintorok@gmail.com> Tue Jul 14 16:55:14 2009 +0000
committer Torok Edwin <edwintorok@gmail.com> Tue Jul 14 16:55:14 2009 +0000
tree bf497ec9a02cd2fc0b64e3e58eff037a719a854d
parent 1f316e321a8f2fa0e193c5444584a67a8aabe9a8

llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelDAGToDAG.cpp

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 8aa627f..296a4d3 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1462,7 +1462,7 @@
       bool isSigned = Opcode == ISD::SMUL_LOHI;
       if (!isSigned)
         switch (NVT.getSimpleVT()) {
-        default: LLVM_UNREACHABLE("Unsupported VT!");
+        default: llvm_unreachable("Unsupported VT!");
         case MVT::i8:  Opc = X86::MUL8r;  MOpc = X86::MUL8m;  break;
         case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
         case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
@@ -1470,7 +1470,7 @@
         }
       else
         switch (NVT.getSimpleVT()) {
-        default: LLVM_UNREACHABLE("Unsupported VT!");
+        default: llvm_unreachable("Unsupported VT!");
         case MVT::i8:  Opc = X86::IMUL8r;  MOpc = X86::IMUL8m;  break;
         case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
         case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
@@ -1479,7 +1479,7 @@
 
       unsigned LoReg, HiReg;
       switch (NVT.getSimpleVT()) {
-      default: LLVM_UNREACHABLE("Unsupported VT!");
+      default: llvm_unreachable("Unsupported VT!");
       case MVT::i8:  LoReg = X86::AL;  HiReg = X86::AH;  break;
       case MVT::i16: LoReg = X86::AX;  HiReg = X86::DX;  break;
       case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
@@ -1568,7 +1568,7 @@
       bool isSigned = Opcode == ISD::SDIVREM;
       if (!isSigned)
         switch (NVT.getSimpleVT()) {
-        default: LLVM_UNREACHABLE("Unsupported VT!");
+        default: llvm_unreachable("Unsupported VT!");
         case MVT::i8:  Opc = X86::DIV8r;  MOpc = X86::DIV8m;  break;
         case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
         case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
@@ -1576,7 +1576,7 @@
         }
       else
         switch (NVT.getSimpleVT()) {
-        default: LLVM_UNREACHABLE("Unsupported VT!");
+        default: llvm_unreachable("Unsupported VT!");
         case MVT::i8:  Opc = X86::IDIV8r;  MOpc = X86::IDIV8m;  break;
         case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
         case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
@@ -1586,7 +1586,7 @@
       unsigned LoReg, HiReg;
       unsigned ClrOpcode, SExtOpcode;
       switch (NVT.getSimpleVT()) {
-      default: LLVM_UNREACHABLE("Unsupported VT!");
+      default: llvm_unreachable("Unsupported VT!");
       case MVT::i8:
         LoReg = X86::AL;  HiReg = X86::AH;
         ClrOpcode  = 0;