commit d790cada339d7af81650084b9bb6b2ad65566fbb
author Andrew Trick <atrick@apple.com> Wed Mar 07 23:00:59 2012 +0000
committer Andrew Trick <atrick@apple.com> Wed Mar 07 23:00:59 2012 +0000
tree 748ecb4d8f4cdc0d7caa6deccb5dedd6332bb666
parent 035ec40eaf1dcd8f4809fb183098259f2dec75b9

misched prep: Comment the ScheduleDAGInstrs interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152259 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/ScheduleDAGInstrs.cpp

diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index c4addee..d2351a3 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -38,8 +38,9 @@
                                      bool IsPostRAFlag,
                                      LiveIntervals *lis)
   : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
-    InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag),
-    LIS(lis), UnitLatencies(false), LoopRegs(MLI, MDT), FirstDbgValue(0) {
+    InstrItins(mf.getTarget().getInstrItineraryData()), LIS(lis),
+    IsPostRA(IsPostRAFlag), UnitLatencies(false), LoopRegs(MLI, MDT),
+    FirstDbgValue(0) {
   assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
   DbgValues.clear();
   assert(!(IsPostRA && MRI.getNumVirtRegs()) &&