Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 929740d..0180069 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -106,14 +106,14 @@
}
/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
-/// MVTs that represent all the individual underlying
+/// EVTs that represent all the individual underlying
/// non-aggregate types that comprise it.
///
/// If Offsets is non-null, it points to a vector to be filled in
/// with the in-memory offsets of each of the individual values.
///
static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
- SmallVectorImpl<MVT> &ValueVTs,
+ SmallVectorImpl<EVT> &ValueVTs,
SmallVectorImpl<uint64_t> *Offsets = 0,
uint64_t StartingOffset = 0) {
// Given a struct type, recursively traverse the elements.
@@ -139,7 +139,7 @@
// Interpret void as zero return values.
if (Ty == Type::VoidTy)
return;
- // Base case: we can get an MVT for this LLVM IR type.
+ // Base case: we can get an EVT for this LLVM IR type.
ValueVTs.push_back(TLI.getValueType(Ty));
if (Offsets)
Offsets->push_back(StartingOffset);
@@ -163,7 +163,7 @@
/// ValueVTs - The value types of the values, which may not be legal, and
/// may need be promoted or synthesized from one or more registers.
///
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
/// RegVTs - The value types of the registers. This is the same size as
/// ValueVTs and it records, for each value, what the type of the assigned
@@ -174,7 +174,7 @@
/// getRegisterType member function, however when with physical registers
/// it is necessary to have a separate record of the types.
///
- SmallVector<MVT, 4> RegVTs;
+ SmallVector<EVT, 4> RegVTs;
/// Regs - This list holds the registers assigned to the values.
/// Each legal or promoted value requires one register, and each
@@ -186,21 +186,21 @@
RegsForValue(const TargetLowering &tli,
const SmallVector<unsigned, 4> ®s,
- MVT regvt, MVT valuevt)
+ EVT regvt, EVT valuevt)
: TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
RegsForValue(const TargetLowering &tli,
const SmallVector<unsigned, 4> ®s,
- const SmallVector<MVT, 4> ®vts,
- const SmallVector<MVT, 4> &valuevts)
+ const SmallVector<EVT, 4> ®vts,
+ const SmallVector<EVT, 4> &valuevts)
: TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
RegsForValue(const TargetLowering &tli,
unsigned Reg, const Type *Ty) : TLI(&tli) {
ComputeValueVTs(tli, Ty, ValueVTs);
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
- MVT ValueVT = ValueVTs[Value];
+ EVT ValueVT = ValueVTs[Value];
unsigned NumRegs = TLI->getNumRegisters(ValueVT);
- MVT RegisterVT = TLI->getRegisterType(ValueVT);
+ EVT RegisterVT = TLI->getRegisterType(ValueVT);
for (unsigned i = 0; i != NumRegs; ++i)
Regs.push_back(Reg + i);
RegVTs.push_back(RegisterVT);
@@ -354,10 +354,10 @@
unsigned PHIReg = ValueMap[PN];
assert(PHIReg && "PHI node does not have an assigned virtual register!");
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, PN->getType(), ValueVTs);
for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
- MVT VT = ValueVTs[vti];
+ EVT VT = ValueVTs[vti];
unsigned NumRegisters = TLI.getNumRegisters(VT);
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
for (unsigned i = 0; i != NumRegisters; ++i)
@@ -368,7 +368,7 @@
}
}
-unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
+unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
}
@@ -380,13 +380,13 @@
/// will assign registers for each member or element.
///
unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, V->getType(), ValueVTs);
unsigned FirstReg = 0;
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
- MVT ValueVT = ValueVTs[Value];
- MVT RegisterVT = TLI.getRegisterType(ValueVT);
+ EVT ValueVT = ValueVTs[Value];
+ EVT RegisterVT = TLI.getRegisterType(ValueVT);
unsigned NumRegs = TLI.getNumRegisters(ValueVT);
for (unsigned i = 0; i != NumRegs; ++i) {
@@ -404,7 +404,7 @@
/// (ISD::AssertSext).
static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
const SDValue *Parts,
- unsigned NumParts, MVT PartVT, MVT ValueVT,
+ unsigned NumParts, EVT PartVT, EVT ValueVT,
ISD::NodeType AssertOp = ISD::DELETED_NODE) {
assert(NumParts > 0 && "No parts to assemble!");
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
@@ -420,11 +420,11 @@
unsigned RoundParts = NumParts & (NumParts - 1) ?
1 << Log2_32(NumParts) : NumParts;
unsigned RoundBits = PartBits * RoundParts;
- MVT RoundVT = RoundBits == ValueBits ?
- ValueVT : MVT::getIntegerVT(RoundBits);
+ EVT RoundVT = RoundBits == ValueBits ?
+ ValueVT : EVT::getIntegerVT(RoundBits);
SDValue Lo, Hi;
- MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
+ EVT HalfVT = EVT::getIntegerVT(RoundBits/2);
if (RoundParts > 2) {
Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
@@ -441,7 +441,7 @@
if (RoundParts < NumParts) {
// Assemble the trailing non-power-of-2 part.
unsigned OddParts = NumParts - RoundParts;
- MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
+ EVT OddVT = EVT::getIntegerVT(OddParts * PartBits);
Hi = getCopyFromParts(DAG, dl,
Parts+RoundParts, OddParts, PartVT, OddVT);
@@ -449,7 +449,7 @@
Lo = Val;
if (TLI.isBigEndian())
std::swap(Lo, Hi);
- MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
+ EVT TotalVT = EVT::getIntegerVT(NumParts * PartBits);
Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
DAG.getConstant(Lo.getValueType().getSizeInBits(),
@@ -459,7 +459,7 @@
}
} else if (ValueVT.isVector()) {
// Handle a multi-element vector.
- MVT IntermediateVT, RegisterVT;
+ EVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
unsigned NumRegs =
TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
@@ -496,11 +496,11 @@
ValueVT, &Ops[0], NumIntermediates);
} else if (PartVT.isFloatingPoint()) {
// FP split into multiple FP parts (for ppcf128)
- assert(ValueVT == MVT(MVT::ppcf128) && PartVT == MVT(MVT::f64) &&
+ assert(ValueVT == EVT(EVT::ppcf128) && PartVT == EVT(EVT::f64) &&
"Unexpected split");
SDValue Lo, Hi;
- Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT(MVT::f64), Parts[0]);
- Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT(MVT::f64), Parts[1]);
+ Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[0]);
+ Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[1]);
if (TLI.isBigEndian())
std::swap(Lo, Hi);
Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
@@ -508,7 +508,7 @@
// FP split into integer parts (soft fp)
assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
!PartVT.isVector() && "Unexpected split");
- MVT IntVT = MVT::getIntegerVT(ValueVT.getSizeInBits());
+ EVT IntVT = EVT::getIntegerVT(ValueVT.getSizeInBits());
Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
}
}
@@ -565,11 +565,11 @@
/// split into legal parts. If the parts contain more bits than Val, then, for
/// integers, ExtendKind can be used to specify how to generate the extra bits.
static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
- SDValue *Parts, unsigned NumParts, MVT PartVT,
+ SDValue *Parts, unsigned NumParts, EVT PartVT,
ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- MVT PtrVT = TLI.getPointerTy();
- MVT ValueVT = Val.getValueType();
+ EVT PtrVT = TLI.getPointerTy();
+ EVT ValueVT = Val.getValueType();
unsigned PartBits = PartVT.getSizeInBits();
unsigned OrigNumParts = NumParts;
assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
@@ -590,7 +590,7 @@
assert(NumParts == 1 && "Do not know what to promote to!");
Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
} else if (PartVT.isInteger() && ValueVT.isInteger()) {
- ValueVT = MVT::getIntegerVT(NumParts * PartBits);
+ ValueVT = EVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
} else {
llvm_unreachable("Unknown mismatch!");
@@ -602,7 +602,7 @@
} else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
// If the parts cover less bits than value has, truncate the value.
if (PartVT.isInteger() && ValueVT.isInteger()) {
- ValueVT = MVT::getIntegerVT(NumParts * PartBits);
+ ValueVT = EVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
} else {
llvm_unreachable("Unknown mismatch!");
@@ -636,19 +636,19 @@
// The odd parts were reversed by getCopyToParts - unreverse them.
std::reverse(Parts + RoundParts, Parts + NumParts);
NumParts = RoundParts;
- ValueVT = MVT::getIntegerVT(NumParts * PartBits);
+ ValueVT = EVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
}
// The number of parts is a power of 2. Repeatedly bisect the value using
// EXTRACT_ELEMENT.
Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::getIntegerVT(ValueVT.getSizeInBits()),
+ EVT::getIntegerVT(ValueVT.getSizeInBits()),
Val);
for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
for (unsigned i = 0; i < NumParts; i += StepSize) {
unsigned ThisBits = StepSize * PartBits / 2;
- MVT ThisVT = MVT::getIntegerVT (ThisBits);
+ EVT ThisVT = EVT::getIntegerVT (ThisBits);
SDValue &Part0 = Parts[i];
SDValue &Part1 = Parts[i+StepSize/2];
@@ -694,7 +694,7 @@
}
// Handle a multi-element vector.
- MVT IntermediateVT, RegisterVT;
+ EVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
unsigned NumRegs = TLI
.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
@@ -774,7 +774,7 @@
}
// Otherwise, we have to make a token factor node.
- SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
+ SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
&PendingLoads[0], PendingLoads.size());
PendingLoads.clear();
DAG.setRoot(Root);
@@ -804,7 +804,7 @@
PendingExports.push_back(Root);
}
- Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
+ Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
&PendingExports[0],
PendingExports.size());
PendingExports.clear();
@@ -833,7 +833,7 @@
if (N.getNode()) return N;
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
- MVT VT = TLI.getValueType(V->getType(), true);
+ EVT VT = TLI.getValueType(V->getType(), true);
if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
return N = DAG.getConstant(*CI, VT);
@@ -873,14 +873,14 @@
assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
"Unknown struct or array constant!");
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, C->getType(), ValueVTs);
unsigned NumElts = ValueVTs.size();
if (NumElts == 0)
return SDValue(); // empty struct
SmallVector<SDValue, 4> Constants(NumElts);
for (unsigned i = 0; i != NumElts; ++i) {
- MVT EltVT = ValueVTs[i];
+ EVT EltVT = ValueVTs[i];
if (isa<UndefValue>(C))
Constants[i] = DAG.getUNDEF(EltVT);
else if (EltVT.isFloatingPoint())
@@ -902,7 +902,7 @@
Ops.push_back(getValue(CP->getOperand(i)));
} else {
assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
- MVT EltVT = TLI.getValueType(VecTy->getElementType());
+ EVT EltVT = TLI.getValueType(VecTy->getElementType());
SDValue Op;
if (EltVT.isFloatingPoint())
@@ -939,14 +939,14 @@
SDValue Chain = getControlRoot();
SmallVector<ISD::OutputArg, 8> Outs;
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
if (NumValues == 0) continue;
SDValue RetOp = getValue(I.getOperand(i));
for (unsigned j = 0, f = NumValues; j != f; ++j) {
- MVT VT = ValueVTs[j];
+ EVT VT = ValueVTs[j];
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
@@ -961,13 +961,13 @@
// conventions. The frontend should mark functions whose return values
// require promoting with signext or zeroext attributes.
if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
- MVT MinVT = TLI.getRegisterType(MVT::i32);
+ EVT MinVT = TLI.getRegisterType(EVT::i32);
if (VT.bitsLT(MinVT))
VT = MinVT;
}
unsigned NumParts = TLI.getNumRegisters(VT);
- MVT PartVT = TLI.getRegisterType(VT);
+ EVT PartVT = TLI.getRegisterType(VT);
SmallVector<SDValue, 4> Parts(NumParts);
getCopyToParts(DAG, getCurDebugLoc(),
SDValue(RetOp.getNode(), RetOp.getResNo() + j),
@@ -995,7 +995,7 @@
Outs, getCurDebugLoc(), DAG);
// Verify that the target's LowerReturn behaved as expected.
- assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
+ assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
"LowerReturn didn't return a valid chain!");
// Update the DAG with the new chain value resulting from return lowering.
@@ -1250,7 +1250,7 @@
// If this is not a fall-through branch, emit the branch.
if (Succ0MBB != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- MVT::Other, getControlRoot(),
+ EVT::Other, getControlRoot(),
DAG.getBasicBlock(Succ0MBB)));
return;
}
@@ -1334,7 +1334,7 @@
SDValue True = DAG.getConstant(1, CondLHS.getValueType());
Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
} else
- Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
+ Cond = DAG.getSetCC(dl, EVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
} else {
assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
@@ -1342,15 +1342,15 @@
const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
SDValue CmpOp = getValue(CB.CmpMHS);
- MVT VT = CmpOp.getValueType();
+ EVT VT = CmpOp.getValueType();
if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
- Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
+ Cond = DAG.getSetCC(dl, EVT::i1, CmpOp, DAG.getConstant(High, VT),
ISD::SETLE);
} else {
SDValue SUB = DAG.getNode(ISD::SUB, dl,
VT, CmpOp, DAG.getConstant(Low, VT));
- Cond = DAG.getSetCC(dl, MVT::i1, SUB,
+ Cond = DAG.getSetCC(dl, EVT::i1, SUB,
DAG.getConstant(High-Low, VT), ISD::SETULE);
}
}
@@ -1374,7 +1374,7 @@
Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
}
SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
- MVT::Other, getControlRoot(), Cond,
+ EVT::Other, getControlRoot(), Cond,
DAG.getBasicBlock(CB.TrueBB));
// If the branch was constant folded, fix up the CFG.
@@ -1389,7 +1389,7 @@
if (CB.FalseBB == NextBlock)
DAG.setRoot(BrCond);
else
- DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
+ DAG.setRoot(DAG.getNode(ISD::BR, dl, EVT::Other, BrCond,
DAG.getBasicBlock(CB.FalseBB)));
}
}
@@ -1398,12 +1398,12 @@
void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
// Emit the code for the jump table
assert(JT.Reg != -1U && "Should lower JT Header first!");
- MVT PTy = TLI.getPointerTy();
+ EVT PTy = TLI.getPointerTy();
SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
JT.Reg, PTy);
SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
- MVT::Other, Index.getValue(1),
+ EVT::Other, Index.getValue(1),
Table, Index));
}
@@ -1415,7 +1415,7 @@
// conditional branch to default mbb if the result is greater than the
// difference between smallest and largest cases.
SDValue SwitchOp = getValue(JTH.SValue);
- MVT VT = SwitchOp.getValueType();
+ EVT VT = SwitchOp.getValueType();
SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
DAG.getConstant(JTH.First, VT));
@@ -1452,13 +1452,13 @@
NextBlock = BBI;
SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- MVT::Other, CopyTo, CMP,
+ EVT::Other, CopyTo, CMP,
DAG.getBasicBlock(JT.Default));
if (JT.MBB == NextBlock)
DAG.setRoot(BrCond);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrCond,
DAG.getBasicBlock(JT.MBB)));
}
@@ -1467,7 +1467,7 @@
void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
// Subtract the minimum value
SDValue SwitchOp = getValue(B.SValue);
- MVT VT = SwitchOp.getValueType();
+ EVT VT = SwitchOp.getValueType();
SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
DAG.getConstant(B.First, VT));
@@ -1502,13 +1502,13 @@
CurMBB->addSuccessor(MBB);
SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- MVT::Other, CopyTo, RangeCmp,
+ EVT::Other, CopyTo, RangeCmp,
DAG.getBasicBlock(B.Default));
if (MBB == NextBlock)
DAG.setRoot(BrRange);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, CopyTo,
DAG.getBasicBlock(MBB)));
}
@@ -1537,7 +1537,7 @@
CurMBB->addSuccessor(NextMBB);
SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- MVT::Other, getControlRoot(),
+ EVT::Other, getControlRoot(),
AndCmp, DAG.getBasicBlock(B.TargetBB));
// Set NextBlock to be the MBB immediately after the current one, if any.
@@ -1550,7 +1550,7 @@
if (NextMBB == NextBlock)
DAG.setRoot(BrAnd);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrAnd,
DAG.getBasicBlock(NextMBB)));
}
@@ -1575,7 +1575,7 @@
// Drop into normal successor.
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- MVT::Other, getControlRoot(),
+ EVT::Other, getControlRoot(),
DAG.getBasicBlock(Return)));
}
@@ -1669,8 +1669,8 @@
static inline bool areJTsAllowed(const TargetLowering &TLI) {
return !DisableJumpTables &&
- (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
- TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
+ (TLI.isOperationLegalOrCustom(ISD::BR_JT, EVT::Other) ||
+ TLI.isOperationLegalOrCustom(ISD::BRIND, EVT::Other));
}
static APInt ComputeRange(const APInt &First, const APInt &Last) {
@@ -1911,7 +1911,7 @@
CaseRecVector& WorkList,
Value* SV,
MachineBasicBlock* Default){
- MVT PTy = TLI.getPointerTy();
+ EVT PTy = TLI.getPointerTy();
unsigned IntPtrBits = PTy.getSizeInBits();
Case& FrontCase = *CR.Range.first;
@@ -2096,7 +2096,7 @@
CurMBB->addSuccessor(Default);
if (Default != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- MVT::Other, getControlRoot(),
+ EVT::Other, getControlRoot(),
DAG.getBasicBlock(Default)));
return;
}
@@ -2188,8 +2188,8 @@
if (!isa<VectorType>(I.getType()) &&
Op2.getValueType() != TLI.getShiftAmountTy()) {
// If the operand is smaller than the shift count type, promote it.
- MVT PTy = TLI.getPointerTy();
- MVT STy = TLI.getShiftAmountTy();
+ EVT PTy = TLI.getPointerTy();
+ EVT STy = TLI.getShiftAmountTy();
if (STy.bitsGT(Op2.getValueType()))
Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
TLI.getShiftAmountTy(), Op2);
@@ -2226,7 +2226,7 @@
SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Opcode = getICmpCondCode(predicate);
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
}
@@ -2239,12 +2239,12 @@
SDValue Op1 = getValue(I.getOperand(0));
SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Condition = getFCmpCondCode(predicate);
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
}
void SelectionDAGLowering::visitSelect(User &I) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I.getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
if (NumValues != 0) {
@@ -2269,7 +2269,7 @@
void SelectionDAGLowering::visitTrunc(User &I) {
// TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
}
@@ -2277,7 +2277,7 @@
// ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
// ZExt also can't be a cast to bool for same reason. So, nothing much to do
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
}
@@ -2285,14 +2285,14 @@
// SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
// SExt also can't be a cast to bool for same reason. So, nothing much to do
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitFPTrunc(User &I) {
// FPTrunc is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
DestVT, N, DAG.getIntPtrConstant(0)));
}
@@ -2300,35 +2300,35 @@
void SelectionDAGLowering::visitFPExt(User &I){
// FPTrunc is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitFPToUI(User &I) {
// FPToUI is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitFPToSI(User &I) {
// FPToSI is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitUIToFP(User &I) {
// UIToFP is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitSIToFP(User &I){
// SIToFP is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
}
@@ -2336,8 +2336,8 @@
// What to do depends on the size of the integer and the size of the pointer.
// We can either truncate, zero extend, or no-op, accordingly.
SDValue N = getValue(I.getOperand(0));
- MVT SrcVT = N.getValueType();
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT SrcVT = N.getValueType();
+ EVT DestVT = TLI.getValueType(I.getType());
SDValue Result;
if (DestVT.bitsLT(SrcVT))
Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
@@ -2351,8 +2351,8 @@
// What to do depends on the size of the integer and the size of the pointer.
// We can either truncate, zero extend, or no-op, accordingly.
SDValue N = getValue(I.getOperand(0));
- MVT SrcVT = N.getValueType();
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT SrcVT = N.getValueType();
+ EVT DestVT = TLI.getValueType(I.getType());
if (DestVT.bitsLT(SrcVT))
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
else
@@ -2363,7 +2363,7 @@
void SelectionDAGLowering::visitBitCast(User &I) {
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
// BitCast assures us that source and destination are the same size so this
// is either a BIT_CONVERT or a no-op.
@@ -2424,8 +2424,8 @@
Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
}
- MVT VT = TLI.getValueType(I.getType());
- MVT SrcVT = Src1.getValueType();
+ EVT VT = TLI.getValueType(I.getType());
+ EVT SrcVT = Src1.getValueType();
unsigned SrcNumElts = SrcVT.getVectorNumElements();
if (SrcNumElts == MaskNumElts) {
@@ -2559,8 +2559,8 @@
// We can't use either concat vectors or extract subvectors so fall back to
// replacing the shuffle with extract and build vector.
// to insert and build vector.
- MVT EltVT = VT.getVectorElementType();
- MVT PtrVT = TLI.getPointerTy();
+ EVT EltVT = VT.getVectorElementType();
+ EVT PtrVT = TLI.getPointerTy();
SmallVector<SDValue,8> Ops;
for (unsigned i = 0; i != MaskNumElts; ++i) {
if (Mask[i] < 0) {
@@ -2591,9 +2591,9 @@
unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
I.idx_begin(), I.idx_end());
- SmallVector<MVT, 4> AggValueVTs;
+ SmallVector<EVT, 4> AggValueVTs;
ComputeValueVTs(TLI, AggTy, AggValueVTs);
- SmallVector<MVT, 4> ValValueVTs;
+ SmallVector<EVT, 4> ValValueVTs;
ComputeValueVTs(TLI, ValTy, ValValueVTs);
unsigned NumAggValues = AggValueVTs.size();
@@ -2630,7 +2630,7 @@
unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
I.idx_begin(), I.idx_end());
- SmallVector<MVT, 4> ValValueVTs;
+ SmallVector<EVT, 4> ValValueVTs;
ComputeValueVTs(TLI, ValTy, ValValueVTs);
unsigned NumValValues = ValValueVTs.size();
@@ -2675,12 +2675,12 @@
uint64_t Offs =
TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
SDValue OffsVal;
- MVT PTy = TLI.getPointerTy();
+ EVT PTy = TLI.getPointerTy();
unsigned PtrBits = PTy.getSizeInBits();
if (PtrBits < 64) {
OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
TLI.getPointerTy(),
- DAG.getConstant(Offs, MVT::i64));
+ DAG.getConstant(Offs, EVT::i64));
} else
OffsVal = DAG.getIntPtrConstant(Offs);
N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
@@ -2743,7 +2743,7 @@
- MVT IntPtr = TLI.getPointerTy();
+ EVT IntPtr = TLI.getPointerTy();
if (IntPtr.bitsLT(AllocSize.getValueType()))
AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
IntPtr, AllocSize);
@@ -2770,7 +2770,7 @@
DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
- SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
+ SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), EVT::Other);
SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
VTs, Ops, 3);
setValue(&I, DSA);
@@ -2789,7 +2789,7 @@
bool isVolatile = I.isVolatile();
unsigned Alignment = I.getAlignment();
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
SmallVector<uint64_t, 4> Offsets;
ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
unsigned NumValues = ValueVTs.size();
@@ -2812,7 +2812,7 @@
SmallVector<SDValue, 4> Values(NumValues);
SmallVector<SDValue, 4> Chains(NumValues);
- MVT PtrVT = Ptr.getValueType();
+ EVT PtrVT = Ptr.getValueType();
for (unsigned i = 0; i != NumValues; ++i) {
SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
DAG.getNode(ISD::ADD, getCurDebugLoc(),
@@ -2826,7 +2826,7 @@
if (!ConstantMemory) {
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
- MVT::Other,
+ EVT::Other,
&Chains[0], NumValues);
if (isVolatile)
DAG.setRoot(Chain);
@@ -2844,7 +2844,7 @@
Value *SrcV = I.getOperand(0);
Value *PtrV = I.getOperand(1);
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
SmallVector<uint64_t, 4> Offsets;
ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
unsigned NumValues = ValueVTs.size();
@@ -2859,7 +2859,7 @@
SDValue Root = getRoot();
SmallVector<SDValue, 4> Chains(NumValues);
- MVT PtrVT = Ptr.getValueType();
+ EVT PtrVT = Ptr.getValueType();
bool isVolatile = I.isVolatile();
unsigned Alignment = I.getAlignment();
for (unsigned i = 0; i != NumValues; ++i)
@@ -2872,7 +2872,7 @@
isVolatile, Alignment);
DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
- MVT::Other, &Chains[0], NumValues));
+ EVT::Other, &Chains[0], NumValues));
}
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
@@ -2909,7 +2909,7 @@
Ops.push_back(Op);
}
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I.getType(), ValueVTs);
#ifndef NDEBUG
for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
@@ -2918,7 +2918,7 @@
}
#endif // NDEBUG
if (HasChain)
- ValueVTs.push_back(MVT::Other);
+ ValueVTs.push_back(EVT::Other);
SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
@@ -2951,7 +2951,7 @@
}
if (I.getType() != Type::VoidTy) {
if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
- MVT VT = TLI.getValueType(PTy);
+ EVT VT = TLI.getValueType(PTy);
Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
}
setValue(&I, Result);
@@ -3033,11 +3033,11 @@
/// where Op is the hexidecimal representation of floating point value.
static SDValue
GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
- SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
- DAG.getConstant(0x007fffff, MVT::i32));
- SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
- DAG.getConstant(0x3f800000, MVT::i32));
- return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
+ SDValue t1 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
+ DAG.getConstant(0x007fffff, EVT::i32));
+ SDValue t2 = DAG.getNode(ISD::OR, dl, EVT::i32, t1,
+ DAG.getConstant(0x3f800000, EVT::i32));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t2);
}
/// GetExponent - Get the exponent:
@@ -3048,19 +3048,19 @@
static SDValue
GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
DebugLoc dl) {
- SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
- DAG.getConstant(0x7f800000, MVT::i32));
- SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
+ SDValue t0 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
+ DAG.getConstant(0x7f800000, EVT::i32));
+ SDValue t1 = DAG.getNode(ISD::SRL, dl, EVT::i32, t0,
DAG.getConstant(23, TLI.getPointerTy()));
- SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
- DAG.getConstant(127, MVT::i32));
- return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
+ SDValue t2 = DAG.getNode(ISD::SUB, dl, EVT::i32, t1,
+ DAG.getConstant(127, EVT::i32));
+ return DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, t2);
}
/// getF32Constant - Get 32-bit floating point constant.
static SDValue
getF32Constant(SelectionDAG &DAG, unsigned Flt) {
- return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
+ return DAG.getConstantFP(APFloat(APInt(32, Flt)), EVT::f32);
}
/// Inlined utility function to implement binary input atomic intrinsics for
@@ -3087,7 +3087,7 @@
SDValue Op1 = getValue(I.getOperand(1));
SDValue Op2 = getValue(I.getOperand(2));
- SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
+ SDVTList VTs = DAG.getVTList(Op1.getValueType(), EVT::i1);
SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
setValue(&I, Result);
@@ -3101,7 +3101,7 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
@@ -3110,16 +3110,16 @@
//
// #define LOG2OFe 1.4426950f
// IntegerPartOfX = ((int32_t)(X * LOG2OFe));
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
getF32Constant(DAG, 0x3fb8aa3b));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
// FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
@@ -3130,20 +3130,20 @@
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
+ SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t5);
// Add the exponent into the result in integer domain.
- SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
+ SDValue t6 = DAG.getNode(ISD::ADD, dl, EVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t6);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3153,23 +3153,23 @@
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// 0.000107046256 error, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
+ SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t7);
// Add the exponent into the result in integer domain.
- SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
+ SDValue t8 = DAG.getNode(ISD::ADD, dl, EVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t8);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3182,33 +3182,33 @@
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
//
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::i32, t13);
+ EVT::i32, t13);
// Add the exponent into the result in integer domain.
- SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
+ SDValue t14 = DAG.getNode(ISD::ADD, dl, EVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t14);
}
} else {
// No special expansion.
@@ -3227,14 +3227,14 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
// Scale the exponent by log(2) [0.69314718f].
SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
- SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
+ SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
getF32Constant(DAG, 0x3f317218));
// Get the significand and build it into a floating-point number with
@@ -3249,16 +3249,16 @@
// (1.4034025f - 0.23903021f * x) * x;
//
// error 0.0034276066, which is better than 8 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbe74c456));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3fb3a2b1));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f949a29));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, LogOfMantissa);
+ EVT::f32, LogOfExponent, LogOfMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3269,22 +3269,22 @@
// (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
//
// error 0.000061011436, which is 14 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbd67b6d6));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3ee4f4b8));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3fbc278b));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x40348e95));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3fdef31a));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, LogOfMantissa);
+ EVT::f32, LogOfExponent, LogOfMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3297,28 +3297,28 @@
// (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
//
// error 0.0000023660568, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbc91e5ac));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3e4350aa));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f60d3e3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x4011cdf0));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
getF32Constant(DAG, 0x406cfd1c));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x408797cb));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
getF32Constant(DAG, 0x4006dcab));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, LogOfMantissa);
+ EVT::f32, LogOfExponent, LogOfMantissa);
}
} else {
// No special expansion.
@@ -3337,10 +3337,10 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
// Get the exponent.
SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
@@ -3357,16 +3357,16 @@
// Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
//
// error 0.0049451742, which is more than 7 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbeb08fe0));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x40019463));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3fd6633d));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log2ofMantissa);
+ EVT::f32, LogOfExponent, Log2ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3377,22 +3377,22 @@
// (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
//
// error 0.0000876136000, which is better than 13 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbda7262e));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3f25280b));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x4007b923));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x40823e2f));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
getF32Constant(DAG, 0x4020d29c));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log2ofMantissa);
+ EVT::f32, LogOfExponent, Log2ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3406,28 +3406,28 @@
// 0.25691327e-1f * x) * x) * x) * x) * x) * x;
//
// error 0.0000018516, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbcd2769e));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3e8ce0b9));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3fa22ae7));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x40525723));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
getF32Constant(DAG, 0x40aaf200));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x40c39dad));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
getF32Constant(DAG, 0x4042902c));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log2ofMantissa);
+ EVT::f32, LogOfExponent, Log2ofMantissa);
}
} else {
// No special expansion.
@@ -3446,14 +3446,14 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
// Scale the exponent by log10(2) [0.30102999f].
SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
- SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
+ SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
getF32Constant(DAG, 0x3e9a209a));
// Get the significand and build it into a floating-point number with
@@ -3468,16 +3468,16 @@
// (0.60948995f - 0.10380950f * x) * x;
//
// error 0.0014886165, which is 6 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbdd49a13));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3f1c0789));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f011300));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log10ofMantissa);
+ EVT::f32, LogOfExponent, Log10ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3487,19 +3487,19 @@
// (-0.31664806f + 0.47637168e-1f * x) * x) * x;
//
// error 0.00019228036, which is better than 12 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3d431f31));
- SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3ea21fb2));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f6ae232));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f25f7c3));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log10ofMantissa);
+ EVT::f32, LogOfExponent, Log10ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3511,25 +3511,25 @@
// (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
//
// error 0.0000037995730, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3c5d51ce));
- SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3e00685a));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3efb6798));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f88d192));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3fc4316c));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t8,
getF32Constant(DAG, 0x3f57ce70));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log10ofMantissa);
+ EVT::f32, LogOfExponent, Log10ofMantissa);
}
} else {
// No special expansion.
@@ -3548,18 +3548,18 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Op);
// FractionalPartOfX = x - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, Op, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
@@ -3570,19 +3570,19 @@
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
+ SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3592,22 +3592,22 @@
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// error 0.000107046256, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
+ SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3619,31 +3619,31 @@
// (0.961591928e-2f +
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
- SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
+ SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
}
} else {
// No special expansion.
@@ -3664,8 +3664,8 @@
DebugLoc dl = getCurDebugLoc();
bool IsExp10 = false;
- if (getValue(Val).getValueType() == MVT::f32 &&
- getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
+ if (getValue(Val).getValueType() == EVT::f32 &&
+ getValue(I.getOperand(2)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
@@ -3683,16 +3683,16 @@
//
// #define LOG2OF10 3.3219281f
// IntegerPartOfX = (int32_t)(x * LOG2OF10);
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
getF32Constant(DAG, 0x40549a78));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
// FractionalPartOfX = x - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
@@ -3703,19 +3703,19 @@
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
+ SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3725,22 +3725,22 @@
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// error 0.000107046256, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
+ SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3752,31 +3752,31 @@
// (0.961591928e-2f +
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
- SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
+ SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
}
} else {
// No special expansion.
@@ -3973,14 +3973,14 @@
return 0;
Value *Variable = DI.getVariable();
- DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
+ DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, EVT::Other, getRoot(),
getValue(DI.getAddress()), getValue(Variable)));
return 0;
}
case Intrinsic::eh_exception: {
// Insert the EXCEPTIONADDR instruction.
assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
- SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
+ SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), EVT::Other);
SDValue Ops[1];
Ops[0] = DAG.getRoot();
SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
@@ -3992,8 +3992,8 @@
case Intrinsic::eh_selector_i32:
case Intrinsic::eh_selector_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
- MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
- MVT::i32 : MVT::i64);
+ EVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
+ EVT::i32 : EVT::i64);
if (MMI) {
if (CurMBB->isLandingPad())
@@ -4008,7 +4008,7 @@
}
// Insert the EHSELECTION instruction.
- SDVTList VTs = DAG.getVTList(VT, MVT::Other);
+ SDVTList VTs = DAG.getVTList(VT, EVT::Other);
SDValue Ops[2];
Ops[0] = getValue(I.getOperand(1));
Ops[1] = getRoot();
@@ -4025,8 +4025,8 @@
case Intrinsic::eh_typeid_for_i32:
case Intrinsic::eh_typeid_for_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
- MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
- MVT::i32 : MVT::i64);
+ EVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
+ EVT::i32 : EVT::i64);
if (MMI) {
// Find the type id for the given typeinfo.
@@ -4047,7 +4047,7 @@
if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
MMI->setCallsEHReturn(true);
DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
- MVT::Other,
+ EVT::Other,
getControlRoot(),
getValue(I.getOperand(1)),
getValue(I.getOperand(2))));
@@ -4064,7 +4064,7 @@
return 0;
case Intrinsic::eh_dwarf_cfa: {
- MVT VT = getValue(I.getOperand(1)).getValueType();
+ EVT VT = getValue(I.getOperand(1)).getValueType();
SDValue CfaArg;
if (VT.bitsGT(TLI.getPointerTy()))
CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
@@ -4109,7 +4109,7 @@
case Intrinsic::convertus: Code = ISD::CVT_US; break;
case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
}
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
Value* Op1 = I.getOperand(1);
setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
DAG.getValueType(DestVT),
@@ -4161,13 +4161,13 @@
return 0;
case Intrinsic::pcmarker: {
SDValue Tmp = getValue(I.getOperand(1));
- DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
+ DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, EVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::readcyclecounter: {
SDValue Op = getRoot();
SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
- DAG.getVTList(MVT::i64, MVT::Other),
+ DAG.getVTList(EVT::i64, EVT::Other),
&Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
@@ -4180,21 +4180,21 @@
return 0;
case Intrinsic::cttz: {
SDValue Arg = getValue(I.getOperand(1));
- MVT Ty = Arg.getValueType();
+ EVT Ty = Arg.getValueType();
SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
setValue(&I, result);
return 0;
}
case Intrinsic::ctlz: {
SDValue Arg = getValue(I.getOperand(1));
- MVT Ty = Arg.getValueType();
+ EVT Ty = Arg.getValueType();
SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
setValue(&I, result);
return 0;
}
case Intrinsic::ctpop: {
SDValue Arg = getValue(I.getOperand(1));
- MVT Ty = Arg.getValueType();
+ EVT Ty = Arg.getValueType();
SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
setValue(&I, result);
return 0;
@@ -4202,21 +4202,21 @@
case Intrinsic::stacksave: {
SDValue Op = getRoot();
SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
- DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
+ DAG.getVTList(TLI.getPointerTy(), EVT::Other), &Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
return 0;
}
case Intrinsic::stackrestore: {
SDValue Tmp = getValue(I.getOperand(1));
- DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
+ DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, EVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::stackprotector: {
// Emit code into the DAG to store the stack guard onto the stack.
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
- MVT PtrTy = TLI.getPointerTy();
+ EVT PtrTy = TLI.getPointerTy();
SDValue Src = getValue(I.getOperand(1)); // The guard's value.
AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
@@ -4250,7 +4250,7 @@
Ops[5] = DAG.getSrcValue(F);
SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
- DAG.getVTList(TLI.getPointerTy(), MVT::Other),
+ DAG.getVTList(TLI.getPointerTy(), EVT::Other),
Ops, 6);
setValue(&I, Tmp);
@@ -4274,12 +4274,12 @@
return 0;
case Intrinsic::flt_rounds: {
- setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
+ setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, EVT::i32));
return 0;
}
case Intrinsic::trap: {
- DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
+ DAG.setRoot(DAG.getNode(ISD::TRAP, dl,EVT::Other, getRoot()));
return 0;
}
@@ -4302,7 +4302,7 @@
Ops[1] = getValue(I.getOperand(1));
Ops[2] = getValue(I.getOperand(2));
Ops[3] = getValue(I.getOperand(3));
- DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
+ DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, EVT::Other, &Ops[0], 4));
return 0;
}
@@ -4312,7 +4312,7 @@
for (int x = 1; x < 6; ++x)
Ops[x] = getValue(I.getOperand(x));
- DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
+ DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, EVT::Other, &Ops[0], 6));
return 0;
}
case Intrinsic::atomic_cmp_swap: {
@@ -4599,9 +4599,9 @@
SmallVector<SDValue, 8> Parts;
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
// Copy the legal parts from the registers.
- MVT ValueVT = ValueVTs[Value];
+ EVT ValueVT = ValueVTs[Value];
unsigned NumRegs = TLI->getNumRegisters(ValueVT);
- MVT RegisterVT = RegVTs[Value];
+ EVT RegisterVT = RegVTs[Value];
Parts.resize(NumRegs);
for (unsigned i = 0; i != NumRegs; ++i) {
@@ -4630,25 +4630,25 @@
// FIXME: We capture more information than the dag can represent. For
// now, just use the tightest assertzext/assertsext possible.
bool isSExt = true;
- MVT FromVT(MVT::Other);
+ EVT FromVT(EVT::Other);
if (NumSignBits == RegSize)
- isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
+ isSExt = true, FromVT = EVT::i1; // ASSERT SEXT 1
else if (NumZeroBits >= RegSize-1)
- isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
+ isSExt = false, FromVT = EVT::i1; // ASSERT ZEXT 1
else if (NumSignBits > RegSize-8)
- isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
+ isSExt = true, FromVT = EVT::i8; // ASSERT SEXT 8
else if (NumZeroBits >= RegSize-8)
- isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
+ isSExt = false, FromVT = EVT::i8; // ASSERT ZEXT 8
else if (NumSignBits > RegSize-16)
- isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
+ isSExt = true, FromVT = EVT::i16; // ASSERT SEXT 16
else if (NumZeroBits >= RegSize-16)
- isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
+ isSExt = false, FromVT = EVT::i16; // ASSERT ZEXT 16
else if (NumSignBits > RegSize-32)
- isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
+ isSExt = true, FromVT = EVT::i32; // ASSERT SEXT 32
else if (NumZeroBits >= RegSize-32)
- isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
+ isSExt = false, FromVT = EVT::i32; // ASSERT ZEXT 32
- if (FromVT != MVT::Other) {
+ if (FromVT != EVT::Other) {
P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
RegisterVT, P, DAG.getValueType(FromVT));
@@ -4680,9 +4680,9 @@
unsigned NumRegs = Regs.size();
SmallVector<SDValue, 8> Parts(NumRegs);
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
- MVT ValueVT = ValueVTs[Value];
+ EVT ValueVT = ValueVTs[Value];
unsigned NumParts = TLI->getNumRegisters(ValueVT);
- MVT RegisterVT = RegVTs[Value];
+ EVT RegisterVT = RegVTs[Value];
getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
&Parts[Part], NumParts, RegisterVT);
@@ -4715,7 +4715,7 @@
// = op c3, ..., f2
Chain = Chains[NumRegs-1];
else
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Chains[0], NumRegs);
}
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
@@ -4725,7 +4725,7 @@
bool HasMatching,unsigned MatchingIdx,
SelectionDAG &DAG,
std::vector<SDValue> &Ops) const {
- MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
+ EVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
unsigned Flag = Code | (Regs.size() << 3);
if (HasMatching)
@@ -4733,7 +4733,7 @@
Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
- MVT RegisterVT = RegVTs[Value];
+ EVT RegisterVT = RegVTs[Value];
for (unsigned i = 0; i != NumRegs; ++i) {
assert(Reg < Regs.size() && "Mismatch in # registers expected");
Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
@@ -4748,11 +4748,11 @@
isAllocatableRegister(unsigned Reg, MachineFunction &MF,
const TargetLowering &TLI,
const TargetRegisterInfo *TRI) {
- MVT FoundVT = MVT::Other;
+ EVT FoundVT = EVT::Other;
const TargetRegisterClass *FoundRC = 0;
for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
E = TRI->regclass_end(); RCI != E; ++RCI) {
- MVT ThisVT = MVT::Other;
+ EVT ThisVT = EVT::Other;
const TargetRegisterClass *RC = *RCI;
// If none of the the value types for this register class are valid, we
@@ -4763,14 +4763,14 @@
// If we have already found this register in a different register class,
// choose the one with the largest VT specified. For example, on
// PowerPC, we favor f64 register classes over f32.
- if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
+ if (FoundVT == EVT::Other || FoundVT.bitsLT(*I)) {
ThisVT = *I;
break;
}
}
}
- if (ThisVT == MVT::Other) continue;
+ if (ThisVT == EVT::Other) continue;
// NOTE: This isn't ideal. In particular, this might allocate the
// frame pointer in functions that need it (due to them not being taken
@@ -4825,12 +4825,12 @@
}
}
- /// getCallOperandValMVT - Return the MVT of the Value* that this operand
+ /// getCallOperandValEVT - Return the EVT of the Value* that this operand
/// corresponds to. If there is no Value* for this operand, it returns
- /// MVT::Other.
- MVT getCallOperandValMVT(const TargetLowering &TLI,
+ /// EVT::Other.
+ EVT getCallOperandValEVT(const TargetLowering &TLI,
const TargetData *TD) const {
- if (CallOperandVal == 0) return MVT::Other;
+ if (CallOperandVal == 0) return EVT::Other;
if (isa<BasicBlock>(CallOperandVal))
return TLI.getPointerTy();
@@ -4923,16 +4923,16 @@
OpInfo.ConstraintVT);
unsigned NumRegs = 1;
- if (OpInfo.ConstraintVT != MVT::Other) {
+ if (OpInfo.ConstraintVT != EVT::Other) {
// If this is a FP input in an integer register (or visa versa) insert a bit
// cast of the input value. More generally, handle any case where the input
// value disagrees with the register class we plan to stick this in.
if (OpInfo.Type == InlineAsm::isInput &&
PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
- // Try to convert to the first MVT that the reg class contains. If the
+ // Try to convert to the first EVT that the reg class contains. If the
// types are identical size, use a bitcast to convert (e.g. two differing
// vector types).
- MVT RegVT = *PhysReg.second->vt_begin();
+ EVT RegVT = *PhysReg.second->vt_begin();
if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
RegVT, OpInfo.CallOperand);
@@ -4942,7 +4942,7 @@
// bitcast to the corresponding integer type. This turns an f64 value
// into i64, which can be passed with two i32 values on a 32-bit
// machine.
- RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
+ RegVT = EVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
RegVT, OpInfo.CallOperand);
OpInfo.ConstraintVT = RegVT;
@@ -4952,14 +4952,14 @@
NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
}
- MVT RegVT;
- MVT ValueVT = OpInfo.ConstraintVT;
+ EVT RegVT;
+ EVT ValueVT = OpInfo.ConstraintVT;
// If this is a constraint for a specific physical register, like {r17},
// assign it now.
if (unsigned AssignedReg = PhysReg.first) {
const TargetRegisterClass *RC = PhysReg.second;
- if (OpInfo.ConstraintVT == MVT::Other)
+ if (OpInfo.ConstraintVT == EVT::Other)
ValueVT = *RC->vt_begin();
// Get the actual register value type. This is important, because the user
@@ -4993,7 +4993,7 @@
// for this reference.
if (const TargetRegisterClass *RC = PhysReg.second) {
RegVT = *RC->vt_begin();
- if (OpInfo.ConstraintVT == MVT::Other)
+ if (OpInfo.ConstraintVT == EVT::Other)
ValueVT = RegVT;
// Create the appropriate number of virtual registers.
@@ -5107,7 +5107,7 @@
ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
- MVT OpVT = MVT::Other;
+ EVT OpVT = EVT::Other;
// Compute the value type for each operand.
switch (OpInfo.Type) {
@@ -5149,7 +5149,7 @@
OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
}
- OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
+ OpVT = OpInfo.getCallOperandValEVT(TLI, TD);
}
OpInfo.ConstraintVT = OpVT;
@@ -5243,7 +5243,7 @@
std::vector<SDValue> AsmNodeOperands;
AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
AsmNodeOperands.push_back(
- DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
+ DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), EVT::Other));
// Loop over all of the inputs, copying the operand values into the
@@ -5336,7 +5336,7 @@
RegsForValue MatchedRegs;
MatchedRegs.TLI = &TLI;
MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
- MVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
+ EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
MatchedRegs.RegVTs.push_back(RegVT);
MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
@@ -5431,7 +5431,7 @@
if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
- DAG.getVTList(MVT::Other, MVT::Flag),
+ DAG.getVTList(EVT::Other, EVT::Flag),
&AsmNodeOperands[0], AsmNodeOperands.size());
Flag = Chain.getValue(1);
@@ -5443,7 +5443,7 @@
// FIXME: Why don't we do this for inline asms with MRVs?
if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
- MVT ResultType = TLI.getValueType(CS.getType());
+ EVT ResultType = TLI.getValueType(CS.getType());
// If any of the results of the inline asm is a vector, it may have the
// wrong width/num elts. This can happen for register classes that can
@@ -5492,7 +5492,7 @@
getValue(StoresToEmit[i].second),
StoresToEmit[i].second, 0));
if (!OutChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
&OutChains[0], OutChains.size());
DAG.setRoot(Chain);
}
@@ -5509,13 +5509,13 @@
uint64_t ElementSize = TD->getTypeAllocSize(I.getType()->getElementType());
if (ElementSize != 1) {
// Src is always 32-bits, make sure the constant fits.
- assert(Src.getValueType() == MVT::i32);
+ assert(Src.getValueType() == EVT::i32);
ElementSize = (uint32_t)ElementSize;
Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
Src, DAG.getConstant(ElementSize, Src.getValueType()));
}
- MVT IntPtr = TLI.getPointerTy();
+ EVT IntPtr = TLI.getPointerTy();
if (IntPtr.bitsLT(Src.getValueType()))
Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
@@ -5548,7 +5548,7 @@
Entry.Node = getValue(I.getOperand(0));
Entry.Ty = TLI.getTargetData()->getIntPtrType();
Args.push_back(Entry);
- MVT IntPtr = TLI.getPointerTy();
+ EVT IntPtr = TLI.getPointerTy();
bool isTailCall = PerformTailCallOpt &&
isInTailCallPosition(&I, Attribute::None, TLI);
std::pair<SDValue,SDValue> Result =
@@ -5563,7 +5563,7 @@
void SelectionDAGLowering::visitVAStart(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
- MVT::Other, getRoot(),
+ EVT::Other, getRoot(),
getValue(I.getOperand(1)),
DAG.getSrcValue(I.getOperand(1))));
}
@@ -5578,14 +5578,14 @@
void SelectionDAGLowering::visitVAEnd(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
- MVT::Other, getRoot(),
+ EVT::Other, getRoot(),
getValue(I.getOperand(1)),
DAG.getSrcValue(I.getOperand(1))));
}
void SelectionDAGLowering::visitVACopy(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
- MVT::Other, getRoot(),
+ EVT::Other, getRoot(),
getValue(I.getOperand(1)),
getValue(I.getOperand(2)),
DAG.getSrcValue(I.getOperand(1)),
@@ -5611,12 +5611,12 @@
// Handle all of the outgoing arguments.
SmallVector<ISD::OutputArg, 32> Outs;
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
for (unsigned Value = 0, NumValues = ValueVTs.size();
Value != NumValues; ++Value) {
- MVT VT = ValueVTs[Value];
- const Type *ArgTy = VT.getTypeForMVT();
+ EVT VT = ValueVTs[Value];
+ const Type *ArgTy = VT.getTypeForEVT();
SDValue Op = SDValue(Args[i].Node.getNode(),
Args[i].Node.getResNo() + Value);
ISD::ArgFlagsTy Flags;
@@ -5648,7 +5648,7 @@
Flags.setNest();
Flags.setOrigAlign(OriginalAlignment);
- MVT PartVT = getRegisterType(VT);
+ EVT PartVT = getRegisterType(VT);
unsigned NumParts = getNumRegisters(VT);
SmallVector<SDValue, 4> Parts(NumParts);
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
@@ -5675,11 +5675,11 @@
// Handle the incoming return values from the call.
SmallVector<ISD::InputArg, 32> Ins;
- SmallVector<MVT, 4> RetTys;
+ SmallVector<EVT, 4> RetTys;
ComputeValueVTs(*this, RetTy, RetTys);
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
- MVT VT = RetTys[I];
- MVT RegisterVT = getRegisterType(VT);
+ EVT VT = RetTys[I];
+ EVT RegisterVT = getRegisterType(VT);
unsigned NumRegs = getNumRegisters(VT);
for (unsigned i = 0; i != NumRegs; ++i) {
ISD::InputArg MyFlags;
@@ -5706,7 +5706,7 @@
Outs, Ins, dl, DAG, InVals);
// Verify that the target's LowerCall behaved as expected.
- assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
+ assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
"LowerCall didn't return a valid chain!");
assert((!isTailCall || InVals.empty()) &&
"LowerCall emitted a return value for a tail call!");
@@ -5738,8 +5738,8 @@
SmallVector<SDValue, 4> ReturnValues;
unsigned CurReg = 0;
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
- MVT VT = RetTys[I];
- MVT RegisterVT = getRegisterType(VT);
+ EVT VT = RetTys[I];
+ EVT RegisterVT = getRegisterType(VT);
unsigned NumRegs = getNumRegisters(VT);
SDValue ReturnValue =
@@ -5805,13 +5805,13 @@
unsigned Idx = 1;
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
I != E; ++I, ++Idx) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I->getType(), ValueVTs);
bool isArgValueUsed = !I->use_empty();
for (unsigned Value = 0, NumValues = ValueVTs.size();
Value != NumValues; ++Value) {
- MVT VT = ValueVTs[Value];
- const Type *ArgTy = VT.getTypeForMVT();
+ EVT VT = ValueVTs[Value];
+ const Type *ArgTy = VT.getTypeForEVT();
ISD::ArgFlagsTy Flags;
unsigned OriginalAlignment =
TD->getABITypeAlignment(ArgTy);
@@ -5841,7 +5841,7 @@
Flags.setNest();
Flags.setOrigAlign(OriginalAlignment);
- MVT RegisterVT = TLI.getRegisterType(VT);
+ EVT RegisterVT = TLI.getRegisterType(VT);
unsigned NumRegs = TLI.getNumRegisters(VT);
for (unsigned i = 0; i != NumRegs; ++i) {
ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
@@ -5862,7 +5862,7 @@
dl, DAG, InVals);
// Verify that the target's LowerFormalArguments behaved as expected.
- assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
+ assert(NewRoot.getNode() && NewRoot.getValueType() == EVT::Other &&
"LowerFormalArguments didn't return a valid chain!");
assert(InVals.size() == Ins.size() &&
"LowerFormalArguments didn't emit the correct number of values!");
@@ -5882,12 +5882,12 @@
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
++I, ++Idx) {
SmallVector<SDValue, 4> ArgValues;
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I->getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
for (unsigned Value = 0; Value != NumValues; ++Value) {
- MVT VT = ValueVTs[Value];
- MVT PartVT = TLI.getRegisterType(VT);
+ EVT VT = ValueVTs[Value];
+ EVT PartVT = TLI.getRegisterType(VT);
unsigned NumParts = TLI.getNumRegisters(VT);
if (!I->use_empty()) {
@@ -5975,10 +5975,10 @@
// Remember that this register needs to added to the machine PHI node as
// the input for this MBB.
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, PN->getType(), ValueVTs);
for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
- MVT VT = ValueVTs[vti];
+ EVT VT = ValueVTs[vti];
unsigned NumRegisters = TLI.getNumRegisters(VT);
for (unsigned i = 0, e = NumRegisters; i != e; ++i)
SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
@@ -6029,10 +6029,10 @@
// own moves. Second, this check is necessary becuase FastISel doesn't
// use CreateRegForValue to create registers, so it always creates
// exactly one register for each non-void instruction.
- MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
- if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
- // Promote MVT::i1.
- if (VT == MVT::i1)
+ EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
+ if (VT == EVT::Other || !TLI.isTypeLegal(VT)) {
+ // Promote EVT::i1.
+ if (VT == EVT::i1)
VT = TLI.getTypeToTransformTo(VT);
else {
SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);