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Jia Liu31d157a2012-02-18 12:03:15 +00001//===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
Tony Linthicumb4b54152011-12-12 21:14:40 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Hexagon uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef Hexagon_ISELLOWERING_H
16#define Hexagon_ISELLOWERING_H
17
Craig Topper79aa3412012-03-17 18:46:09 +000018#include "Hexagon.h"
Tony Linthicumb4b54152011-12-12 21:14:40 +000019#include "llvm/CodeGen/CallingConvLower.h"
Chandler Carruth0b8c9a82013-01-02 11:36:10 +000020#include "llvm/IR/CallingConv.h"
Chandler Carrutha1514e22012-12-04 07:12:27 +000021#include "llvm/Target/TargetLowering.h"
Tony Linthicumb4b54152011-12-12 21:14:40 +000022
23namespace llvm {
24 namespace HexagonISD {
25 enum {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
27
28 CONST32,
29 CONST32_GP, // For marking data present in GP.
Sirish Pande7517bbc2012-05-10 20:20:25 +000030 FCONST32,
Tony Linthicumb4b54152011-12-12 21:14:40 +000031 SETCC,
32 ADJDYNALLOC,
33 ARGEXTEND,
34
35 CMPICC, // Compare two GPR operands, set icc.
36 CMPFCC, // Compare two FP operands, set fcc.
37 BRICC, // Branch to dest on icc condition
38 BRFCC, // Branch to dest on fcc condition
39 SELECT_ICC, // Select between two values using the current ICC flags.
40 SELECT_FCC, // Select between two values using the current FCC flags.
41
42 Hi, Lo, // Hi/Lo operations, typically on a global address.
43
44 FTOI, // FP to Int within a FP register.
45 ITOF, // Int to FP within a FP register.
46
47 CALL, // A call instruction.
48 RET_FLAG, // Return with a flag operand.
49 BR_JT, // Jump table.
50 BARRIER, // Memory barrier.
51 WrapperJT,
Sirish Pande7517bbc2012-05-10 20:20:25 +000052 WrapperCP,
Jyotsna Verma4b3aafb2012-12-04 18:05:01 +000053 WrapperCombineII,
54 WrapperCombineRR,
55 WrapperPackhl,
56 WrapperSplatB,
57 WrapperSplatH,
58 WrapperShuffEB,
59 WrapperShuffEH,
60 WrapperShuffOB,
61 WrapperShuffOH,
Tony Linthicumb4b54152011-12-12 21:14:40 +000062 TC_RETURN
63 };
64 }
65
66 class HexagonTargetLowering : public TargetLowering {
67 int VarArgsFrameOffset; // Frame offset to start of varargs area.
68
69 bool CanReturnSmallStruct(const Function* CalleeFn,
70 unsigned& RetSize) const;
71
72 public:
73 HexagonTargetMachine &TM;
74 explicit HexagonTargetLowering(HexagonTargetMachine &targetmachine);
75
76 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
77 /// for tail call optimization. Targets which want to do tail call
78 /// optimization should implement this function.
79 bool
80 IsEligibleForTailCallOptimization(SDValue Callee,
81 CallingConv::ID CalleeCC,
82 bool isVarArg,
83 bool isCalleeStructRet,
84 bool isCallerStructRet,
85 const
86 SmallVectorImpl<ISD::OutputArg> &Outs,
87 const SmallVectorImpl<SDValue> &OutVals,
88 const SmallVectorImpl<ISD::InputArg> &Ins,
89 SelectionDAG& DAG) const;
90
91 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
92 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
93
94 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
95
96 virtual const char *getTargetNodeName(unsigned Opcode) const;
97 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
98 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
99 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
100 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerFormalArguments(SDValue Chain,
102 CallingConv::ID CallConv, bool isVarArg,
103 const SmallVectorImpl<ISD::InputArg> &Ins,
104 DebugLoc dl, SelectionDAG &DAG,
105 SmallVectorImpl<SDValue> &InVals) const;
106 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
107
Justin Holewinskid2ea0e12012-05-25 16:35:28 +0000108 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
Tony Linthicumb4b54152011-12-12 21:14:40 +0000109 SmallVectorImpl<SDValue> &InVals) const;
110
111 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
112 CallingConv::ID CallConv, bool isVarArg,
113 const SmallVectorImpl<ISD::InputArg> &Ins,
114 DebugLoc dl, SelectionDAG &DAG,
115 SmallVectorImpl<SDValue> &InVals,
116 const SmallVectorImpl<SDValue> &OutVals,
117 SDValue Callee) const;
118
119 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
122 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
123 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
124
125 SDValue LowerReturn(SDValue Chain,
126 CallingConv::ID CallConv, bool isVarArg,
127 const SmallVectorImpl<ISD::OutputArg> &Outs,
128 const SmallVectorImpl<SDValue> &OutVals,
129 DebugLoc dl, SelectionDAG &DAG) const;
130
131 virtual MachineBasicBlock
132 *EmitInstrWithCustomInserter(MachineInstr *MI,
133 MachineBasicBlock *BB) const;
134
135 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
Sirish Pande7517bbc2012-05-10 20:20:25 +0000136 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000137 virtual EVT getSetCCResultType(EVT VT) const {
138 return MVT::i1;
139 }
140
141 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
142 SDValue &Base, SDValue &Offset,
143 ISD::MemIndexedMode &AM,
144 SelectionDAG &DAG) const;
145
146 std::pair<unsigned, const TargetRegisterClass*>
147 getRegForInlineAsmConstraint(const std::string &Constraint,
148 EVT VT) const;
149
150 // Intrinsics
151 virtual SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op,
152 SelectionDAG &DAG) const;
153 /// isLegalAddressingMode - Return true if the addressing mode represented
154 /// by AM is legal for this target, for a load/store of the specified type.
155 /// The type may be VoidTy, in which case only return true if the addressing
156 /// mode is legal for a load/store of any legal type.
157 /// TODO: Handle pre/postinc as well.
158 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
Sirish Pande7517bbc2012-05-10 20:20:25 +0000159 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000160
161 /// isLegalICmpImmediate - Return true if the specified immediate is legal
162 /// icmp immediate, that is the target has icmp instructions which can
163 /// compare a register against the immediate without having to materialize
164 /// the immediate into a register.
165 virtual bool isLegalICmpImmediate(int64_t Imm) const;
166 };
167} // end namespace llvm
168
169#endif // Hexagon_ISELLOWERING_H