| Akira Hatanaka | 0bc1adb | 2012-07-31 21:49:49 +0000 | [diff] [blame^] | 1 | //===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the Mips32/64 implementation of the TargetInstrInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef MIPSSEINSTRUCTIONINFO_H |
| 15 | #define MIPSSEINSTRUCTIONINFO_H |
| 16 | |
| 17 | #include "MipsInstrInfo.h" |
| 18 | #include "MipsAnalyzeImmediate.h" |
| 19 | |
| 20 | namespace llvm { |
| 21 | |
| 22 | class MipsSEInstrInfo : public MipsInstrInfo { |
| 23 | bool IsN64; |
| 24 | public: |
| 25 | explicit MipsSEInstrInfo(MipsTargetMachine &TM); |
| 26 | |
| 27 | /// isLoadFromStackSlot - If the specified machine instruction is a direct |
| 28 | /// load from a stack slot, return the virtual or physical register number of |
| 29 | /// the destination along with the FrameIndex of the loaded stack slot. If |
| 30 | /// not, return 0. This predicate must return 0 if the instruction has |
| 31 | /// any side effects other than loading from the stack slot. |
| 32 | virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, |
| 33 | int &FrameIndex) const; |
| 34 | |
| 35 | /// isStoreToStackSlot - If the specified machine instruction is a direct |
| 36 | /// store to a stack slot, return the virtual or physical register number of |
| 37 | /// the source reg along with the FrameIndex of the loaded stack slot. If |
| 38 | /// not, return 0. This predicate must return 0 if the instruction has |
| 39 | /// any side effects other than storing to the stack slot. |
| 40 | virtual unsigned isStoreToStackSlot(const MachineInstr *MI, |
| 41 | int &FrameIndex) const; |
| 42 | |
| 43 | virtual void copyPhysReg(MachineBasicBlock &MBB, |
| 44 | MachineBasicBlock::iterator MI, DebugLoc DL, |
| 45 | unsigned DestReg, unsigned SrcReg, |
| 46 | bool KillSrc) const; |
| 47 | |
| 48 | virtual void storeRegToStackSlot(MachineBasicBlock &MBB, |
| 49 | MachineBasicBlock::iterator MBBI, |
| 50 | unsigned SrcReg, bool isKill, int FrameIndex, |
| 51 | const TargetRegisterClass *RC, |
| 52 | const TargetRegisterInfo *TRI) const; |
| 53 | |
| 54 | virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, |
| 55 | MachineBasicBlock::iterator MBBI, |
| 56 | unsigned DestReg, int FrameIndex, |
| 57 | const TargetRegisterClass *RC, |
| 58 | const TargetRegisterInfo *TRI) const; |
| 59 | |
| 60 | virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; |
| 61 | |
| 62 | virtual unsigned GetOppositeBranchOpc(unsigned Opc) const; |
| 63 | |
| 64 | private: |
| 65 | virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const; |
| 66 | |
| 67 | void ExpandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 68 | unsigned Opc) const; |
| 69 | void ExpandExtractElementF64(MachineBasicBlock &MBB, |
| 70 | MachineBasicBlock::iterator I) const; |
| 71 | void ExpandBuildPairF64(MachineBasicBlock &MBB, |
| 72 | MachineBasicBlock::iterator I) const; |
| 73 | }; |
| 74 | |
| 75 | } |
| 76 | |
| 77 | #endif |