| Evan Cheng | 0d68fde | 2009-07-21 18:54:14 +0000 | [diff] [blame^] | 1 | //===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines the itinerary class data for the ARM v7 processors. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | def V7Itineraries : ProcessorItineraries<[ |
| 15 | InstrItinData<IIC_iALU , [InstrStage<1, [FU_iALU]>]>, |
| 16 | InstrItinData<IIC_iLoad , [InstrStage<2, [FU_iLdSt]>]>, |
| 17 | InstrItinData<IIC_iStore , [InstrStage<1, [FU_iLdSt]>]>, |
| 18 | InstrItinData<IIC_fpALU , [InstrStage<6, [FU_FpALU]>]>, |
| 19 | InstrItinData<IIC_fpLoad , [InstrStage<2, [FU_FpLdSt]>]>, |
| 20 | InstrItinData<IIC_fpStore , [InstrStage<1, [FU_FpLdSt]>]>, |
| 21 | InstrItinData<IIC_Br , [InstrStage<3, [FU_Br]>]> |
| 22 | ]>; |
| 23 | |
| 24 | |
| 25 | def CortexA8Itineraries : ProcessorItineraries<[ |
| 26 | InstrItinData<IIC_iALU , [InstrStage<1, [FU_iALU]>]>, |
| 27 | InstrItinData<IIC_iLoad , [InstrStage<2, [FU_iLdSt]>]>, |
| 28 | InstrItinData<IIC_iStore , [InstrStage<1, [FU_iLdSt]>]>, |
| 29 | InstrItinData<IIC_fpALU , [InstrStage<6, [FU_FpALU]>]>, |
| 30 | InstrItinData<IIC_fpLoad , [InstrStage<2, [FU_FpLdSt]>]>, |
| 31 | InstrItinData<IIC_fpStore , [InstrStage<1, [FU_FpLdSt]>]>, |
| 32 | InstrItinData<IIC_Br , [InstrStage<3, [FU_Br]>]> |
| 33 | ]>; |