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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 16803097fbefa313fdadc3adede659bd0e52cec1 / . / lib / Target / PowerPC / PPCSchedule440.td
blob: cd0fb70a24bddb2828ec79cf03ddd683ffc9b318 [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- PPCSchedule440.td - PPC 440 Scheduling Definitions -*- tablegen -*-===//
2//
Hal Finkelb31d3d22011-10-17 04:03:55 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]7//
Hal Finkelb31d3d22011-10-17 04:03:55 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9
10// Primary reference:
Hal Finkele9e57912011-10-17 18:10:08 +0000[diff] [blame]11// PowerPC 440x6 Embedded Processor Core User's Manual.
Hal Finkelb31d3d22011-10-17 04:03:55 +0000[diff] [blame]12// IBM (as updated in) 2010.
13
14// The basic PPC 440 does not include a floating-point unit; the pipeline
15// timings here are constructed to match the FP2 unit shipped with the
16// PPC-440- and PPC-450-based Blue Gene (L and P) supercomputers.
17// References:
18// S. Chatterjee, et al. Design and exploitation of a high-performance
19// SIMD floating-point unit for Blue Gene/L.
20// IBM J. Res. & Dev. 49 (2/3) March/May 2005.
21// also:
22// Carlos Sosa and Brant Knudson. IBM System Blue Gene Solution:
23// Blue Gene/P Application Development.
24// IBM (as updated in) 2009.
25
26//===----------------------------------------------------------------------===//
27// Functional units on the PowerPC 440/450 chip sets
28//
29def IFTH1 : FuncUnit; // Fetch unit 1
30def IFTH2 : FuncUnit; // Fetch unit 2
31def PDCD1 : FuncUnit; // Decode unit 1
32def PDCD2 : FuncUnit; // Decode unit 2
33def DISS1 : FuncUnit; // Issue unit 1
34def DISS2 : FuncUnit; // Issue unit 2
35def LRACC : FuncUnit; // Register access and dispatch for
36 // the simple integer (J-pipe) and
37 // load/store (L-pipe) pipelines
38def IRACC : FuncUnit; // Register access and dispatch for
39 // the complex integer (I-pipe) pipeline
40def FRACC : FuncUnit; // Register access and dispatch for
41 // the floating-point execution (F-pipe) pipeline
42def IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline
43def IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline
44def IWB : FuncUnit; // Write-back unit for the I pipeline
45def JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline
46def JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline
47def JWB : FuncUnit; // Write-back unit for the J pipeline
48def AGEN : FuncUnit; // Address generation for the L pipeline
49def CRD : FuncUnit; // D-cache access for the L pipeline
50def LWB : FuncUnit; // Write-back unit for the L pipeline
51def FEXE1 : FuncUnit; // Execution stage 1 for the F pipeline
52def FEXE2 : FuncUnit; // Execution stage 2 for the F pipeline
53def FEXE3 : FuncUnit; // Execution stage 3 for the F pipeline
54def FEXE4 : FuncUnit; // Execution stage 4 for the F pipeline
55def FEXE5 : FuncUnit; // Execution stage 5 for the F pipeline
56def FEXE6 : FuncUnit; // Execution stage 6 for the F pipeline
57def FWB : FuncUnit; // Write-back unit for the F pipeline
58
59def LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used
60 // to make sure that no lwarx/stwcx.
61 // instructions are issued while another
62 // lwarx/stwcx. is in the L pipe.
63
64def GPR_Bypass : Bypass; // The bypass for general-purpose regs.
65def FPR_Bypass : Bypass; // The bypass for floating-point regs.
66
67// Notes:
68// Instructions are held in the FRACC, LRACC and IRACC pipeline
69// stages until their source operands become ready. Exceptions:
70// - Store instructions will hold in the AGEN stage
71// - The integer multiply-accumulate instruction will hold in
72// the IEXE1 stage
73//
74// For most I-pipe operations, the result is available at the end of
75// the IEXE1 stage. Operations such as multiply and divide must
76// continue to execute in IEXE2 and IWB. Divide resides in IWB for
77// 33 cycles (multiply also calculates its result in IWB). For all
78// J-pipe instructions, the result is available
79// at the end of the JEXE1 stage. Loads have a 3-cycle latency
80// (data is not available until after the LWB stage).
81//
82// The L1 cache hit latency is four cycles for floating point loads
83// and three cycles for integer loads.
84//
85// The stwcx. instruction requires both the LRACC and the IRACC
86// dispatch stages. It must be issued from DISS0.
87//
88// All lwarx/stwcx. instructions hold in LRACC if another
89// uncommitted lwarx/stwcx. is in AGEN, CRD, or LWB.
90//
91// msync (a.k.a. sync) and mbar will hold in LWB until all load/store
92// resources are empty. AGEN and CRD are held empty until the msync/mbar
93// commits.
94//
95// Most floating-point instructions, computational and move,
96// have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that
97// update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
98// loads take 4 cycles (for L1 hit).
99
100//
101// This file defines the itinerary class data for the PPC 440 processor.
102//
103//===----------------------------------------------------------------------===//
104
105
106def PPC440Itineraries : ProcessorItineraries<
107 [IFTH1, IFTH2, PDCD1, PDCD2, DISS1, DISS2, FRACC,
108 IRACC, IEXE1, IEXE2, IWB, LRACC, JEXE1, JEXE2, JWB, AGEN, CRD, LWB,
109 FEXE1, FEXE2, FEXE3, FEXE4, FEXE5, FEXE6, FWB, LWARX_Hold],
110 [GPR_Bypass, FPR_Bypass], [
Hal Finkel16803092012-06-12 19:01:24 +0000[diff] [blame^]111 InstrItinData<IntSimple , [InstrStage<1, [IFTH1, IFTH2]>,
112 InstrStage<1, [PDCD1, PDCD2]>,
113 InstrStage<1, [DISS1, DISS2]>,
114 InstrStage<1, [IRACC, LRACC]>,
115 InstrStage<1, [IEXE1, JEXE1]>,
116 InstrStage<1, [IEXE2, JEXE2]>,
117 InstrStage<1, [IWB, JWB]>],
118 [6, 4, 4],
119 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb31d3d22011-10-17 04:03:55 +0000[diff] [blame]120 InstrItinData<IntGeneral , [InstrStage<1, [IFTH1, IFTH2]>,
121 InstrStage<1, [PDCD1, PDCD2]>,
122 InstrStage<1, [DISS1, DISS2]>,
123 InstrStage<1, [IRACC, LRACC]>,
124 InstrStage<1, [IEXE1, JEXE1]>,
125 InstrStage<1, [IEXE2, JEXE2]>,
126 InstrStage<1, [IWB, JWB]>],
127 [6, 4, 4],
128 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
129 InstrItinData<IntCompare , [InstrStage<1, [IFTH1, IFTH2]>,
130 InstrStage<1, [PDCD1, PDCD2]>,
131 InstrStage<1, [DISS1, DISS2]>,
132 InstrStage<1, [IRACC, LRACC]>,
133 InstrStage<1, [IEXE1, JEXE1]>,
134 InstrStage<1, [IEXE2, JEXE2]>,
135 InstrStage<1, [IWB, JWB]>],
136 [6, 4, 4],
137 [NoBypass, GPR_Bypass, GPR_Bypass]>,
138 InstrItinData<IntDivW , [InstrStage<1, [IFTH1, IFTH2]>,
139 InstrStage<1, [PDCD1, PDCD2]>,
140 InstrStage<1, [DISS1, DISS2]>,
141 InstrStage<1, [IRACC]>,
142 InstrStage<1, [IEXE1]>,
143 InstrStage<1, [IEXE2]>,
144 InstrStage<33, [IWB]>],
145 [40, 4, 4],
146 [NoBypass, GPR_Bypass, GPR_Bypass]>,
147 InstrItinData<IntMFFS , [InstrStage<1, [IFTH1, IFTH2]>,
148 InstrStage<1, [PDCD1, PDCD2]>,
149 InstrStage<1, [DISS1, DISS2]>,
150 InstrStage<1, [IRACC]>,
151 InstrStage<1, [IEXE1]>,
152 InstrStage<1, [IEXE2]>,
153 InstrStage<1, [IWB]>],
154 [7, 4, 4],
155 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
156 InstrItinData<IntMTFSB0 , [InstrStage<1, [IFTH1, IFTH2]>,
157 InstrStage<1, [PDCD1, PDCD2]>,
158 InstrStage<1, [DISS1, DISS2]>,
159 InstrStage<1, [IRACC]>,
160 InstrStage<1, [IEXE1]>,
161 InstrStage<1, [IEXE2]>,
162 InstrStage<1, [IWB]>],
163 [7, 4, 4],
164 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
165 InstrItinData<IntMulHW , [InstrStage<1, [IFTH1, IFTH2]>,
166 InstrStage<1, [PDCD1, PDCD2]>,
167 InstrStage<1, [DISS1, DISS2]>,
168 InstrStage<1, [IRACC]>,
169 InstrStage<1, [IEXE1]>,
170 InstrStage<1, [IEXE2]>,
171 InstrStage<1, [IWB]>],
172 [8, 4, 4],
173 [NoBypass, GPR_Bypass, GPR_Bypass]>,
174 InstrItinData<IntMulHWU , [InstrStage<1, [IFTH1, IFTH2]>,
175 InstrStage<1, [PDCD1, PDCD2]>,
176 InstrStage<1, [DISS1, DISS2]>,
177 InstrStage<1, [IRACC]>,
178 InstrStage<1, [IEXE1]>,
179 InstrStage<1, [IEXE2]>,
180 InstrStage<1, [IWB]>],
181 [8, 4, 4],
182 [NoBypass, GPR_Bypass, GPR_Bypass]>,
183 InstrItinData<IntMulLI , [InstrStage<1, [IFTH1, IFTH2]>,
184 InstrStage<1, [PDCD1, PDCD2]>,
185 InstrStage<1, [DISS1, DISS2]>,
186 InstrStage<1, [IRACC]>,
187 InstrStage<1, [IEXE1]>,
188 InstrStage<1, [IEXE2]>,
189 InstrStage<1, [IWB]>],
190 [8, 4, 4],
191 [NoBypass, GPR_Bypass, GPR_Bypass]>,
192 InstrItinData<IntRotate , [InstrStage<1, [IFTH1, IFTH2]>,
193 InstrStage<1, [PDCD1, PDCD2]>,
194 InstrStage<1, [DISS1, DISS2]>,
195 InstrStage<1, [IRACC, LRACC]>,
196 InstrStage<1, [IEXE1, JEXE1]>,
197 InstrStage<1, [IEXE2, JEXE2]>,
198 InstrStage<1, [IWB, JWB]>],
199 [6, 4, 4],
200 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
201 InstrItinData<IntShift , [InstrStage<1, [IFTH1, IFTH2]>,
202 InstrStage<1, [PDCD1, PDCD2]>,
203 InstrStage<1, [DISS1, DISS2]>,
204 InstrStage<1, [IRACC, LRACC]>,
205 InstrStage<1, [IEXE1, JEXE1]>,
206 InstrStage<1, [IEXE2, JEXE2]>,
207 InstrStage<1, [IWB, JWB]>],
208 [6, 4, 4],
209 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
210 InstrItinData<IntTrapW , [InstrStage<1, [IFTH1, IFTH2]>,
211 InstrStage<1, [PDCD1, PDCD2]>,
212 InstrStage<1, [DISS1, DISS2]>,
213 InstrStage<1, [IRACC]>,
214 InstrStage<1, [IEXE1]>,
215 InstrStage<1, [IEXE2]>,
216 InstrStage<1, [IWB]>],
217 [6, 4],
218 [GPR_Bypass, GPR_Bypass]>,
219 InstrItinData<BrB , [InstrStage<1, [IFTH1, IFTH2]>,
220 InstrStage<1, [PDCD1, PDCD2]>,
221 InstrStage<1, [DISS1, DISS2]>,
222 InstrStage<1, [IRACC]>,
223 InstrStage<1, [IEXE1]>,
224 InstrStage<1, [IEXE2]>,
225 InstrStage<1, [IWB]>],
226 [8, 4],
227 [NoBypass, GPR_Bypass]>,
228 InstrItinData<BrCR , [InstrStage<1, [IFTH1, IFTH2]>,
229 InstrStage<1, [PDCD1, PDCD2]>,
230 InstrStage<1, [DISS1, DISS2]>,
231 InstrStage<1, [IRACC]>,
232 InstrStage<1, [IEXE1]>,
233 InstrStage<1, [IEXE2]>,
234 InstrStage<1, [IWB]>],
235 [8, 4, 4],
236 [NoBypass, GPR_Bypass, GPR_Bypass]>,
237 InstrItinData<BrMCR , [InstrStage<1, [IFTH1, IFTH2]>,
238 InstrStage<1, [PDCD1, PDCD2]>,
239 InstrStage<1, [DISS1, DISS2]>,
240 InstrStage<1, [IRACC]>,
241 InstrStage<1, [IEXE1]>,
242 InstrStage<1, [IEXE2]>,
243 InstrStage<1, [IWB]>],
244 [8, 4, 4],
245 [NoBypass, GPR_Bypass, GPR_Bypass]>,
246 InstrItinData<BrMCRX , [InstrStage<1, [IFTH1, IFTH2]>,
247 InstrStage<1, [PDCD1, PDCD2]>,
248 InstrStage<1, [DISS1, DISS2]>,
249 InstrStage<1, [IRACC]>,
250 InstrStage<1, [IEXE1]>,
251 InstrStage<1, [IEXE2]>,
252 InstrStage<1, [IWB]>],
253 [8, 4, 4],
254 [NoBypass, GPR_Bypass, GPR_Bypass]>,
255 InstrItinData<LdStDCBA , [InstrStage<1, [IFTH1, IFTH2]>,
256 InstrStage<1, [PDCD1, PDCD2]>,
257 InstrStage<1, [DISS1, DISS2]>,
258 InstrStage<1, [LRACC]>,
259 InstrStage<1, [AGEN]>,
260 InstrStage<1, [CRD]>,
261 InstrStage<1, [LWB]>],
262 [8, 5],
263 [NoBypass, GPR_Bypass]>,
264 InstrItinData<LdStDCBF , [InstrStage<1, [IFTH1, IFTH2]>,
265 InstrStage<1, [PDCD1, PDCD2]>,
266 InstrStage<1, [DISS1, DISS2]>,
267 InstrStage<1, [LRACC]>,
268 InstrStage<1, [AGEN]>,
269 InstrStage<1, [CRD]>,
270 InstrStage<1, [LWB]>],
271 [8, 5],
272 [NoBypass, GPR_Bypass]>,
273 InstrItinData<LdStDCBI , [InstrStage<1, [IFTH1, IFTH2]>,
274 InstrStage<1, [PDCD1, PDCD2]>,
275 InstrStage<1, [DISS1, DISS2]>,
276 InstrStage<1, [LRACC]>,
277 InstrStage<1, [AGEN]>,
278 InstrStage<1, [CRD]>,
279 InstrStage<1, [LWB]>],
280 [8, 5],
281 [NoBypass, GPR_Bypass]>,
Hal Finkel20b529b2012-04-01 04:44:16 +0000[diff] [blame]282 InstrItinData<LdStLoad , [InstrStage<1, [IFTH1, IFTH2]>,
Hal Finkelb31d3d22011-10-17 04:03:55 +0000[diff] [blame]283 InstrStage<1, [PDCD1, PDCD2]>,
284 InstrStage<1, [DISS1, DISS2]>,
285 InstrStage<1, [LRACC]>,
286 InstrStage<1, [AGEN]>,
287 InstrStage<1, [CRD]>,
288 InstrStage<2, [LWB]>],
Hal Finkel20b529b2012-04-01 04:44:16 +0000[diff] [blame]289 [9, 5],
290 [GPR_Bypass, GPR_Bypass]>,
291 InstrItinData<LdStStore , [InstrStage<1, [IFTH1, IFTH2]>,
292 InstrStage<1, [PDCD1, PDCD2]>,
293 InstrStage<1, [DISS1, DISS2]>,
294 InstrStage<1, [LRACC]>,
295 InstrStage<1, [AGEN]>,
296 InstrStage<1, [CRD]>,
297 InstrStage<2, [LWB]>],
298 [8, 5],
Hal Finkelb31d3d22011-10-17 04:03:55 +0000[diff] [blame]299 [NoBypass, GPR_Bypass]>,
300 InstrItinData<LdStICBI , [InstrStage<1, [IFTH1, IFTH2]>,
301 InstrStage<1, [PDCD1, PDCD2]>,
302 InstrStage<1, [DISS1, DISS2]>,
303 InstrStage<1, [LRACC]>,
304 InstrStage<1, [AGEN]>,
305 InstrStage<1, [CRD]>,
306 InstrStage<1, [LWB]>],
307 [8, 5],
308 [NoBypass, GPR_Bypass]>,
309 InstrItinData<LdStUX , [InstrStage<1, [IFTH1, IFTH2]>,
310 InstrStage<1, [PDCD1, PDCD2]>,
311 InstrStage<1, [DISS1, DISS2]>,
312 InstrStage<1, [LRACC]>,
313 InstrStage<1, [AGEN]>,
314 InstrStage<1, [CRD]>,
315 InstrStage<1, [LWB]>],
316 [8, 5, 5],
317 [NoBypass, GPR_Bypass, GPR_Bypass]>,
318 InstrItinData<LdStLFD , [InstrStage<1, [IFTH1, IFTH2]>,
319 InstrStage<1, [PDCD1, PDCD2]>,
320 InstrStage<1, [DISS1, DISS2]>,
321 InstrStage<1, [LRACC]>,
322 InstrStage<1, [AGEN]>,
323 InstrStage<1, [CRD]>,
324 InstrStage<2, [LWB]>],
325 [9, 5, 5],
326 [NoBypass, GPR_Bypass, GPR_Bypass]>,
327 InstrItinData<LdStLFDU , [InstrStage<1, [IFTH1, IFTH2]>,
328 InstrStage<1, [PDCD1, PDCD2]>,
329 InstrStage<1, [DISS1, DISS2]>,
330 InstrStage<1, [LRACC]>,
331 InstrStage<1, [AGEN]>,
332 InstrStage<1, [CRD]>,
333 InstrStage<1, [LWB]>],
334 [9, 5, 5],
335 [NoBypass, GPR_Bypass, GPR_Bypass]>,
336 InstrItinData<LdStLHA , [InstrStage<1, [IFTH1, IFTH2]>,
337 InstrStage<1, [PDCD1, PDCD2]>,
338 InstrStage<1, [DISS1, DISS2]>,
339 InstrStage<1, [LRACC]>,
340 InstrStage<1, [AGEN]>,
341 InstrStage<1, [CRD]>,
342 InstrStage<1, [LWB]>],
343 [8, 5],
344 [NoBypass, GPR_Bypass]>,
345 InstrItinData<LdStLMW , [InstrStage<1, [IFTH1, IFTH2]>,
346 InstrStage<1, [PDCD1, PDCD2]>,
347 InstrStage<1, [DISS1, DISS2]>,
348 InstrStage<1, [LRACC]>,
349 InstrStage<1, [AGEN]>,
350 InstrStage<1, [CRD]>,
351 InstrStage<1, [LWB]>],
352 [8, 5],
353 [NoBypass, GPR_Bypass]>,
354 InstrItinData<LdStLWARX , [InstrStage<1, [IFTH1, IFTH2]>,
355 InstrStage<1, [PDCD1, PDCD2]>,
356 InstrStage<1, [DISS1]>,
357 InstrStage<1, [IRACC], 0>,
358 InstrStage<4, [LWARX_Hold], 0>,
359 InstrStage<1, [LRACC]>,
360 InstrStage<1, [AGEN]>,
361 InstrStage<1, [CRD]>,
362 InstrStage<1, [LWB]>],
363 [8, 5],
364 [NoBypass, GPR_Bypass]>,
Hal Finkel20b529b2012-04-01 04:44:16 +0000[diff] [blame]365 InstrItinData<LdStSTD , [InstrStage<1, [IFTH1, IFTH2]>,
366 InstrStage<1, [PDCD1, PDCD2]>,
367 InstrStage<1, [DISS1, DISS2]>,
368 InstrStage<1, [LRACC]>,
369 InstrStage<1, [AGEN]>,
370 InstrStage<1, [CRD]>,
371 InstrStage<2, [LWB]>],
372 [8, 5],
373 [NoBypass, GPR_Bypass]>,
374 InstrItinData<LdStSTDCX , [InstrStage<1, [IFTH1, IFTH2]>,
375 InstrStage<1, [PDCD1, PDCD2]>,
376 InstrStage<1, [DISS1]>,
377 InstrStage<1, [IRACC], 0>,
378 InstrStage<4, [LWARX_Hold], 0>,
379 InstrStage<1, [LRACC]>,
380 InstrStage<1, [AGEN]>,
381 InstrStage<1, [CRD]>,
382 InstrStage<1, [LWB]>],
383 [8, 5],
384 [NoBypass, GPR_Bypass]>,
Hal Finkelb31d3d22011-10-17 04:03:55 +0000[diff] [blame]385 InstrItinData<LdStSTWCX , [InstrStage<1, [IFTH1, IFTH2]>,
386 InstrStage<1, [PDCD1, PDCD2]>,
387 InstrStage<1, [DISS1]>,
388 InstrStage<1, [IRACC], 0>,
389 InstrStage<4, [LWARX_Hold], 0>,
390 InstrStage<1, [LRACC]>,
391 InstrStage<1, [AGEN]>,
392 InstrStage<1, [CRD]>,
393 InstrStage<1, [LWB]>],
394 [8, 5],
395 [NoBypass, GPR_Bypass]>,
396 InstrItinData<LdStSync , [InstrStage<1, [IFTH1, IFTH2]>,
397 InstrStage<1, [PDCD1, PDCD2]>,
398 InstrStage<1, [DISS1, DISS2]>,
399 InstrStage<1, [LRACC]>,
400 InstrStage<3, [AGEN], 1>,
401 InstrStage<2, [CRD], 1>,
402 InstrStage<1, [LWB]>]>,
403 InstrItinData<SprISYNC , [InstrStage<1, [IFTH1, IFTH2]>,
404 InstrStage<1, [PDCD1, PDCD2]>,
405 InstrStage<1, [DISS1, DISS2]>,
406 InstrStage<1, [FRACC], 0>,
407 InstrStage<1, [LRACC], 0>,
408 InstrStage<1, [IRACC]>,
409 InstrStage<1, [FEXE1], 0>,
410 InstrStage<1, [AGEN], 0>,
411 InstrStage<1, [JEXE1], 0>,
412 InstrStage<1, [IEXE1]>,
413 InstrStage<1, [FEXE2], 0>,
414 InstrStage<1, [CRD], 0>,
415 InstrStage<1, [JEXE2], 0>,
416 InstrStage<1, [IEXE2]>,
417 InstrStage<6, [FEXE3], 0>,
418 InstrStage<6, [LWB], 0>,
419 InstrStage<6, [JWB], 0>,
420 InstrStage<6, [IWB]>]>,
421 InstrItinData<SprMFSR , [InstrStage<1, [IFTH1, IFTH2]>,
422 InstrStage<1, [PDCD1, PDCD2]>,
423 InstrStage<1, [DISS1, DISS2]>,
424 InstrStage<1, [IRACC]>,
425 InstrStage<1, [IEXE1]>,
426 InstrStage<1, [IEXE2]>,
427 InstrStage<1, [IWB]>],
428 [6, 4],
429 [GPR_Bypass, GPR_Bypass]>,
430 InstrItinData<SprMTMSR , [InstrStage<1, [IFTH1, IFTH2]>,
431 InstrStage<1, [PDCD1, PDCD2]>,
432 InstrStage<1, [DISS1, DISS2]>,
433 InstrStage<1, [IRACC]>,
434 InstrStage<1, [IEXE1]>,
435 InstrStage<1, [IEXE2]>,
436 InstrStage<1, [IWB]>],
437 [6, 4],
438 [GPR_Bypass, GPR_Bypass]>,
439 InstrItinData<SprMTSR , [InstrStage<1, [IFTH1, IFTH2]>,
440 InstrStage<1, [PDCD1, PDCD2]>,
441 InstrStage<1, [DISS1, DISS2]>,
442 InstrStage<1, [IRACC]>,
443 InstrStage<1, [IEXE1]>,
444 InstrStage<1, [IEXE2]>,
445 InstrStage<3, [IWB]>],
446 [9, 4],
447 [NoBypass, GPR_Bypass]>,
448 InstrItinData<SprTLBSYNC , [InstrStage<1, [IFTH1, IFTH2]>,
449 InstrStage<1, [PDCD1, PDCD2]>,
450 InstrStage<1, [DISS1, DISS2]>,
451 InstrStage<1, [IRACC]>,
452 InstrStage<1, [IEXE1]>,
453 InstrStage<1, [IEXE2]>,
454 InstrStage<1, [IWB]>]>,
455 InstrItinData<SprMFCR , [InstrStage<1, [IFTH1, IFTH2]>,
456 InstrStage<1, [PDCD1, PDCD2]>,
457 InstrStage<1, [DISS1, DISS2]>,
458 InstrStage<1, [IRACC]>,
459 InstrStage<1, [IEXE1]>,
460 InstrStage<1, [IEXE2]>,
461 InstrStage<1, [IWB]>],
462 [8, 4],
463 [NoBypass, GPR_Bypass]>,
464 InstrItinData<SprMFMSR , [InstrStage<1, [IFTH1, IFTH2]>,
465 InstrStage<1, [PDCD1, PDCD2]>,
466 InstrStage<1, [DISS1, DISS2]>,
467 InstrStage<1, [IRACC]>,
468 InstrStage<1, [IEXE1]>,
469 InstrStage<1, [IEXE2]>,
470 InstrStage<1, [IWB]>],
471 [7, 4],
472 [GPR_Bypass, GPR_Bypass]>,
473 InstrItinData<SprMFSPR , [InstrStage<1, [IFTH1, IFTH2]>,
474 InstrStage<1, [PDCD1, PDCD2]>,
475 InstrStage<1, [DISS1, DISS2]>,
476 InstrStage<1, [IRACC]>,
477 InstrStage<1, [IEXE1]>,
478 InstrStage<1, [IEXE2]>,
479 InstrStage<3, [IWB]>],
480 [10, 4],
481 [NoBypass, GPR_Bypass]>,
482 InstrItinData<SprMFTB , [InstrStage<1, [IFTH1, IFTH2]>,
483 InstrStage<1, [PDCD1, PDCD2]>,
484 InstrStage<1, [DISS1, DISS2]>,
485 InstrStage<1, [IRACC]>,
486 InstrStage<1, [IEXE1]>,
487 InstrStage<1, [IEXE2]>,
488 InstrStage<3, [IWB]>],
489 [10, 4],
490 [NoBypass, GPR_Bypass]>,
491 InstrItinData<SprMTSPR , [InstrStage<1, [IFTH1, IFTH2]>,
492 InstrStage<1, [PDCD1, PDCD2]>,
493 InstrStage<1, [DISS1, DISS2]>,
494 InstrStage<1, [IRACC]>,
495 InstrStage<1, [IEXE1]>,
496 InstrStage<1, [IEXE2]>,
497 InstrStage<3, [IWB]>],
498 [10, 4],
499 [NoBypass, GPR_Bypass]>,
500 InstrItinData<SprMTSRIN , [InstrStage<1, [IFTH1, IFTH2]>,
501 InstrStage<1, [PDCD1, PDCD2]>,
502 InstrStage<1, [DISS1, DISS2]>,
503 InstrStage<1, [IRACC]>,
504 InstrStage<1, [IEXE1]>,
505 InstrStage<1, [IEXE2]>,
506 InstrStage<3, [IWB]>],
507 [10, 4],
508 [NoBypass, GPR_Bypass]>,
509 InstrItinData<SprRFI , [InstrStage<1, [IFTH1, IFTH2]>,
510 InstrStage<1, [PDCD1, PDCD2]>,
511 InstrStage<1, [DISS1, DISS2]>,
512 InstrStage<1, [IRACC]>,
513 InstrStage<1, [IEXE1]>,
514 InstrStage<1, [IEXE2]>,
515 InstrStage<1, [IWB]>],
516 [8, 4],
517 [NoBypass, GPR_Bypass]>,
518 InstrItinData<SprSC , [InstrStage<1, [IFTH1, IFTH2]>,
519 InstrStage<1, [PDCD1, PDCD2]>,
520 InstrStage<1, [DISS1, DISS2]>,
521 InstrStage<1, [IRACC]>,
522 InstrStage<1, [IEXE1]>,
523 InstrStage<1, [IEXE2]>,
524 InstrStage<1, [IWB]>],
525 [8, 4],
526 [NoBypass, GPR_Bypass]>,
527 InstrItinData<FPGeneral , [InstrStage<1, [IFTH1, IFTH2]>,
528 InstrStage<1, [PDCD1, PDCD2]>,
529 InstrStage<1, [DISS1, DISS2]>,
530 InstrStage<1, [FRACC]>,
531 InstrStage<1, [FEXE1]>,
532 InstrStage<1, [FEXE2]>,
533 InstrStage<1, [FEXE3]>,
534 InstrStage<1, [FEXE4]>,
535 InstrStage<1, [FEXE5]>,
536 InstrStage<1, [FEXE6]>,
537 InstrStage<1, [FWB]>],
538 [10, 4, 4],
539 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
540 InstrItinData<FPCompare , [InstrStage<1, [IFTH1, IFTH2]>,
541 InstrStage<1, [PDCD1, PDCD2]>,
542 InstrStage<1, [DISS1, DISS2]>,
543 InstrStage<1, [FRACC]>,
544 InstrStage<1, [FEXE1]>,
545 InstrStage<1, [FEXE2]>,
546 InstrStage<1, [FEXE3]>,
547 InstrStage<1, [FEXE4]>,
548 InstrStage<1, [FEXE5]>,
549 InstrStage<1, [FEXE6]>,
550 InstrStage<1, [FWB]>],
551 [10, 4, 4],
552 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
553 InstrItinData<FPDivD , [InstrStage<1, [IFTH1, IFTH2]>,
554 InstrStage<1, [PDCD1, PDCD2]>,
555 InstrStage<1, [DISS1, DISS2]>,
556 InstrStage<1, [FRACC]>,
557 InstrStage<1, [FEXE1]>,
558 InstrStage<1, [FEXE2]>,
559 InstrStage<1, [FEXE3]>,
560 InstrStage<1, [FEXE4]>,
561 InstrStage<1, [FEXE5]>,
562 InstrStage<1, [FEXE6]>,
563 InstrStage<25, [FWB]>],
564 [35, 4, 4],
565 [NoBypass, FPR_Bypass, FPR_Bypass]>,
566 InstrItinData<FPDivS , [InstrStage<1, [IFTH1, IFTH2]>,
567 InstrStage<1, [PDCD1, PDCD2]>,
568 InstrStage<1, [DISS1, DISS2]>,
569 InstrStage<1, [FRACC]>,
570 InstrStage<1, [FEXE1]>,
571 InstrStage<1, [FEXE2]>,
572 InstrStage<1, [FEXE3]>,
573 InstrStage<1, [FEXE4]>,
574 InstrStage<1, [FEXE5]>,
575 InstrStage<1, [FEXE6]>,
576 InstrStage<13, [FWB]>],
577 [23, 4, 4],
578 [NoBypass, FPR_Bypass, FPR_Bypass]>,
579 InstrItinData<FPFused , [InstrStage<1, [IFTH1, IFTH2]>,
580 InstrStage<1, [PDCD1, PDCD2]>,
581 InstrStage<1, [DISS1, DISS2]>,
582 InstrStage<1, [FRACC]>,
583 InstrStage<1, [FEXE1]>,
584 InstrStage<1, [FEXE2]>,
585 InstrStage<1, [FEXE3]>,
586 InstrStage<1, [FEXE4]>,
587 InstrStage<1, [FEXE5]>,
588 InstrStage<1, [FEXE6]>,
589 InstrStage<1, [FWB]>],
590 [10, 4, 4, 4],
591 [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
592 InstrItinData<FPRes , [InstrStage<1, [IFTH1, IFTH2]>,
593 InstrStage<1, [PDCD1, PDCD2]>,
594 InstrStage<1, [DISS1, DISS2]>,
595 InstrStage<1, [FRACC]>,
596 InstrStage<1, [FEXE1]>,
597 InstrStage<1, [FEXE2]>,
598 InstrStage<1, [FEXE3]>,
599 InstrStage<1, [FEXE4]>,
600 InstrStage<1, [FEXE5]>,
601 InstrStage<1, [FEXE6]>,
602 InstrStage<1, [FWB]>],
603 [10, 4],
604 [FPR_Bypass, FPR_Bypass]>
605]>;