Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 19c95507443ebd4f1cee80917d540c8bd27f8fe1 / . / lib / Target / PowerPC / PPC.td
blob: 8b9e3a7ac140176e1a00f11fec728085d1b1b0bb [file] [log] [blame]
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]1//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is the top level entry point for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing.
15//
16include "../Target.td"
17
18//===----------------------------------------------------------------------===//
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]19// PowerPC Subtarget features.
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]20//
21
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame^]22def Feature64Bit : SubtargetFeature<"64bit","Is64Bit", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]23 "Enable 64-bit instructions">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame^]24def Feature64BitRegs : SubtargetFeature<"64bitregs","Has64BitRegs", "true",
Chris Lattneraa38be12005-10-23 22:23:45 +0000[diff] [blame]25 "Enable 64-bit registers [beta]">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame^]26def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]27 "Enable Altivec instructions">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame^]28def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]29 "Enable GPUL instructions">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame^]30def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]31 "Enable the fsqrt instruction">;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]32
33//===----------------------------------------------------------------------===//
Chris Lattnerc8d28892005-10-23 22:08:13 +0000[diff] [blame]34// Register File Description
35//===----------------------------------------------------------------------===//
36
37include "PPCRegisterInfo.td"
38include "PPCSchedule.td"
39include "PPCInstrInfo.td"
40
41//===----------------------------------------------------------------------===//
42// PowerPC processors supported.
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]43//
44
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]45def : Processor<"generic", G3Itineraries, []>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]46def : Processor<"601", G3Itineraries, []>;
47def : Processor<"602", G3Itineraries, []>;
48def : Processor<"603", G3Itineraries, []>;
Jim Laskeyf5fc2cb2005-10-21 19:05:19 +0000[diff] [blame]49def : Processor<"603e", G3Itineraries, []>;
50def : Processor<"603ev", G3Itineraries, []>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]51def : Processor<"604", G3Itineraries, []>;
Jim Laskeyf5fc2cb2005-10-21 19:05:19 +0000[diff] [blame]52def : Processor<"604e", G3Itineraries, []>;
53def : Processor<"620", G3Itineraries, []>;
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]54def : Processor<"g3", G3Itineraries, []>;
Jim Laskeyf5fc2cb2005-10-21 19:05:19 +0000[diff] [blame]55def : Processor<"7400", G4Itineraries, [FeatureAltivec]>;
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]56def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
Jim Laskeyf5fc2cb2005-10-21 19:05:19 +0000[diff] [blame]57def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]58def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]59def : Processor<"750", G3Itineraries, []>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]60def : Processor<"970", G5Itineraries,
Jim Laskeyf5fc2cb2005-10-21 19:05:19 +0000[diff] [blame]61 [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]62 Feature64Bit /*, Feature64BitRegs */]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]63def : Processor<"g5", G5Itineraries,
Jim Laskeyf5fc2cb2005-10-21 19:05:19 +0000[diff] [blame]64 [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]65 Feature64Bit /*, Feature64BitRegs */]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]66
67
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]68def PPC : Target {
69 // Pointers on PPC are 32-bits in size.
70 let PointerType = i32;
71
72 // According to the Mach-O Runtime ABI, these regs are nonvolatile across
73 // calls
74 let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
75 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
76 F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
77 F30, F31, CR2, CR3, CR4, LR];
78
79 // Pull in Instruction Info:
80 let InstructionSet = PowerPCInstrInfo;
81}