Jia Liu | 31d157a | 2012-02-18 12:03:15 +0000 | [diff] [blame] | 1 | //===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===// |
Tony Linthicum | b4b5415 | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | // Functional Units |
| 11 | def LUNIT : FuncUnit; |
| 12 | def LSUNIT : FuncUnit; |
| 13 | def MUNIT : FuncUnit; |
| 14 | def SUNIT : FuncUnit; |
| 15 | |
Tony Linthicum | b4b5415 | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 16 | // Itinerary classes |
| 17 | def ALU32 : InstrItinClass; |
| 18 | def ALU64 : InstrItinClass; |
| 19 | def CR : InstrItinClass; |
| 20 | def J : InstrItinClass; |
| 21 | def JR : InstrItinClass; |
| 22 | def LD : InstrItinClass; |
| 23 | def M : InstrItinClass; |
| 24 | def ST : InstrItinClass; |
| 25 | def S : InstrItinClass; |
Sirish Pande | 71d5646 | 2012-05-03 16:18:50 +0000 | [diff] [blame] | 26 | def SYS : InstrItinClass; |
| 27 | def MARKER : InstrItinClass; |
Tony Linthicum | b4b5415 | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 28 | def PSEUDO : InstrItinClass; |
| 29 | |
Tony Linthicum | b4b5415 | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 30 | def HexagonItineraries : |
Sirish Pande | 71d5646 | 2012-05-03 16:18:50 +0000 | [diff] [blame] | 31 | ProcessorItineraries<[LUNIT, LSUNIT, MUNIT, SUNIT], [], [ |
| 32 | InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>, |
| 33 | InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>, |
| 34 | InstrItinData<CR , [InstrStage<1, [SUNIT]>]>, |
| 35 | InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>, |
| 36 | InstrItinData<JR , [InstrStage<1, [MUNIT]>]>, |
| 37 | InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>, |
| 38 | InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>, |
| 39 | InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>, |
| 40 | InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>, |
| 41 | InstrItinData<SYS , [InstrStage<1, [LSUNIT]>]>, |
| 42 | InstrItinData<MARKER , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>, |
| 43 | InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]> |
Andrew Trick | 2661b41 | 2012-07-07 04:00:00 +0000 | [diff] [blame^] | 44 | ]>; |
| 45 | |
| 46 | def HexagonModel : SchedMachineModel { |
Andrew Trick | fc99299 | 2012-06-05 03:44:40 +0000 | [diff] [blame] | 47 | // Max issue per cycle == bundle width. |
| 48 | let IssueWidth = 4; |
Andrew Trick | 2661b41 | 2012-07-07 04:00:00 +0000 | [diff] [blame^] | 49 | let Itineraries = HexagonItineraries; |
Andrew Trick | fc99299 | 2012-06-05 03:44:40 +0000 | [diff] [blame] | 50 | } |
Tony Linthicum | b4b5415 | 2011-12-12 21:14:40 +0000 | [diff] [blame] | 51 | |
| 52 | //===----------------------------------------------------------------------===// |
| 53 | // V4 Machine Info + |
| 54 | //===----------------------------------------------------------------------===// |
| 55 | |
| 56 | include "HexagonScheduleV4.td" |
| 57 | |
| 58 | //===----------------------------------------------------------------------===// |
| 59 | // V4 Machine Info - |
| 60 | //===----------------------------------------------------------------------===// |