Arnold Schwaighofer | 48abc5c | 2007-10-12 21:30:57 +0000 | [diff] [blame] | 1 | //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===// |
Evan Cheng | ffcb95b | 2006-02-21 19:13:53 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Evan Cheng | ffcb95b | 2006-02-21 19:13:53 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file describes the X86 SSE instruction set, defining the instructions, |
| 11 | // and properties of the instructions which are needed for code generation, |
| 12 | // machine code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Chris Lattner | 3a7cd95 | 2006-10-07 21:55:32 +0000 | [diff] [blame] | 16 | |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 17 | //===----------------------------------------------------------------------===// |
Evan Cheng | 2246f84 | 2006-03-18 01:23:20 +0000 | [diff] [blame] | 18 | // SSE specific DAG Nodes. |
| 19 | //===----------------------------------------------------------------------===// |
| 20 | |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 21 | def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>, |
| 22 | SDTCisFP<0>, SDTCisInt<2> ]>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 23 | def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, |
| 24 | SDTCisFP<1>, SDTCisVT<3, i8>]>; |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 25 | |
Evan Cheng | 8ca2932 | 2006-11-10 21:43:37 +0000 | [diff] [blame] | 26 | def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; |
| 27 | def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 28 | def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 29 | [SDNPCommutative, SDNPAssociative]>; |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 30 | def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, |
| 31 | [SDNPCommutative, SDNPAssociative]>; |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 32 | def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 33 | [SDNPCommutative, SDNPAssociative]>; |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 34 | def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; |
| 35 | def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 36 | def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>; |
Evan Cheng | fef922a | 2007-10-01 18:12:48 +0000 | [diff] [blame] | 37 | def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 38 | def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; |
Nate Begeman | b9a47b8 | 2009-02-23 08:49:38 +0000 | [diff] [blame] | 39 | def X86pshufb : SDNode<"X86ISD::PSHUFB", |
| 40 | SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, |
| 41 | SDTCisSameAs<0,2>]>>; |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 42 | def X86pextrb : SDNode<"X86ISD::PEXTRB", |
| 43 | SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; |
| 44 | def X86pextrw : SDNode<"X86ISD::PEXTRW", |
| 45 | SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; |
| 46 | def X86pinsrb : SDNode<"X86ISD::PINSRB", |
| 47 | SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, |
| 48 | SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; |
| 49 | def X86pinsrw : SDNode<"X86ISD::PINSRW", |
| 50 | SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, |
| 51 | SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; |
| 52 | def X86insrtps : SDNode<"X86ISD::INSERTPS", |
| 53 | SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, |
| 54 | SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>; |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 55 | def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", |
| 56 | SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; |
| 57 | def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, |
| 58 | [SDNPHasChain, SDNPMayLoad]>; |
Evan Cheng | f26ffe9 | 2008-05-29 08:22:04 +0000 | [diff] [blame] | 59 | def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>; |
| 60 | def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 61 | def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>; |
| 62 | def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>; |
| 63 | def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>; |
| 64 | def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>; |
| 65 | def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>; |
| 66 | def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>; |
| 67 | def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>; |
| 68 | def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>; |
| 69 | def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>; |
| 70 | def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>; |
Evan Cheng | c60bd97 | 2006-03-25 09:37:23 +0000 | [diff] [blame] | 71 | |
Evan Cheng | 2246f84 | 2006-03-18 01:23:20 +0000 | [diff] [blame] | 72 | //===----------------------------------------------------------------------===// |
Chris Lattner | 3a7cd95 | 2006-10-07 21:55:32 +0000 | [diff] [blame] | 73 | // SSE Complex Patterns |
| 74 | //===----------------------------------------------------------------------===// |
| 75 | |
| 76 | // These are 'extloads' from a scalar to the low element of a vector, zeroing |
| 77 | // the top elements. These are used for the SSE 'ss' and 'sd' instruction |
| 78 | // forms. |
Rafael Espindola | 2a6411b | 2009-04-07 21:37:46 +0000 | [diff] [blame^] | 79 | def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [], |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 80 | [SDNPHasChain, SDNPMayLoad]>; |
Rafael Espindola | 2a6411b | 2009-04-07 21:37:46 +0000 | [diff] [blame^] | 81 | def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [], |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 82 | [SDNPHasChain, SDNPMayLoad]>; |
Chris Lattner | 3a7cd95 | 2006-10-07 21:55:32 +0000 | [diff] [blame] | 83 | |
| 84 | def ssmem : Operand<v4f32> { |
| 85 | let PrintMethod = "printf32mem"; |
Rafael Espindola | 2a6411b | 2009-04-07 21:37:46 +0000 | [diff] [blame^] | 86 | let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm); |
Chris Lattner | 3a7cd95 | 2006-10-07 21:55:32 +0000 | [diff] [blame] | 87 | } |
| 88 | def sdmem : Operand<v2f64> { |
| 89 | let PrintMethod = "printf64mem"; |
Rafael Espindola | 2a6411b | 2009-04-07 21:37:46 +0000 | [diff] [blame^] | 90 | let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm); |
Chris Lattner | 3a7cd95 | 2006-10-07 21:55:32 +0000 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | //===----------------------------------------------------------------------===// |
Evan Cheng | 06a8aa1 | 2006-03-17 19:55:52 +0000 | [diff] [blame] | 94 | // SSE pattern fragments |
| 95 | //===----------------------------------------------------------------------===// |
| 96 | |
Evan Cheng | 2246f84 | 2006-03-18 01:23:20 +0000 | [diff] [blame] | 97 | def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; |
| 98 | def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; |
Dan Gohman | 0197630 | 2007-06-25 15:19:03 +0000 | [diff] [blame] | 99 | def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>; |
Evan Cheng | 24dc1f5 | 2006-03-23 07:44:07 +0000 | [diff] [blame] | 100 | def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>; |
Evan Cheng | 06a8aa1 | 2006-03-17 19:55:52 +0000 | [diff] [blame] | 101 | |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 102 | // Like 'store', but always requires vector alignment. |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 103 | def alignedstore : PatFrag<(ops node:$val, node:$ptr), |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 104 | (store node:$val, node:$ptr), [{ |
| 105 | return cast<StoreSDNode>(N)->getAlignment() >= 16; |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 106 | }]>; |
| 107 | |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 108 | // Like 'load', but always requires vector alignment. |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 109 | def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ |
| 110 | return cast<LoadSDNode>(N)->getAlignment() >= 16; |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 111 | }]>; |
| 112 | |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 113 | def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>; |
| 114 | def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>; |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 115 | def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>; |
| 116 | def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>; |
| 117 | def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>; |
| 118 | def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>; |
| 119 | |
| 120 | // Like 'load', but uses special alignment checks suitable for use in |
| 121 | // memory operands in most SSE instructions, which are required to |
| 122 | // be naturally aligned on some targets but not on others. |
| 123 | // FIXME: Actually implement support for targets that don't require the |
| 124 | // alignment. This probably wants a subtarget predicate. |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 125 | def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ |
| 126 | return cast<LoadSDNode>(N)->getAlignment() >= 16; |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 127 | }]>; |
| 128 | |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 129 | def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>; |
| 130 | def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>; |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 131 | def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; |
| 132 | def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; |
| 133 | def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>; |
| 134 | def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 135 | def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>; |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 136 | |
Bill Wendling | 01284b4 | 2007-08-11 09:52:53 +0000 | [diff] [blame] | 137 | // SSSE3 uses MMX registers for some instructions. They aren't aligned on a |
| 138 | // 16-byte boundary. |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 139 | // FIXME: 8 byte alignment for mmx reads is not required |
Dan Gohman | a7250dd | 2008-10-16 00:03:00 +0000 | [diff] [blame] | 140 | def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 141 | return cast<LoadSDNode>(N)->getAlignment() >= 8; |
Bill Wendling | 01284b4 | 2007-08-11 09:52:53 +0000 | [diff] [blame] | 142 | }]>; |
| 143 | |
| 144 | def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>; |
Bill Wendling | 01284b4 | 2007-08-11 09:52:53 +0000 | [diff] [blame] | 145 | def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>; |
| 146 | def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>; |
| 147 | def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>; |
| 148 | |
Evan Cheng | 1b32f22 | 2006-03-30 07:33:32 +0000 | [diff] [blame] | 149 | def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; |
| 150 | def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 151 | def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; |
| 152 | def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; |
Evan Cheng | 5aa97b2 | 2006-03-29 18:47:40 +0000 | [diff] [blame] | 153 | def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; |
| 154 | def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; |
| 155 | |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 156 | def vzmovl_v2i64 : PatFrag<(ops node:$src), |
| 157 | (bitconvert (v2i64 (X86vzmovl |
| 158 | (v2i64 (scalar_to_vector (loadi64 node:$src))))))>; |
| 159 | def vzmovl_v4i32 : PatFrag<(ops node:$src), |
| 160 | (bitconvert (v4i32 (X86vzmovl |
| 161 | (v4i32 (scalar_to_vector (loadi32 node:$src))))))>; |
| 162 | |
| 163 | def vzload_v2i64 : PatFrag<(ops node:$src), |
| 164 | (bitconvert (v2i64 (X86vzload node:$src)))>; |
| 165 | |
| 166 | |
Evan Cheng | 386031a | 2006-03-24 07:29:27 +0000 | [diff] [blame] | 167 | def fp32imm0 : PatLeaf<(f32 fpimm), [{ |
| 168 | return N->isExactlyValue(+0.0); |
| 169 | }]>; |
| 170 | |
Evan Cheng | ff65e38 | 2006-04-04 21:49:39 +0000 | [diff] [blame] | 171 | def PSxLDQ_imm : SDNodeXForm<imm, [{ |
| 172 | // Transformation function: imm >> 3 |
Dan Gohman | f5aeb1a | 2008-09-12 16:56:44 +0000 | [diff] [blame] | 173 | return getI32Imm(N->getZExtValue() >> 3); |
Evan Cheng | ff65e38 | 2006-04-04 21:49:39 +0000 | [diff] [blame] | 174 | }]>; |
| 175 | |
Evan Cheng | 63d3300 | 2006-03-22 08:01:21 +0000 | [diff] [blame] | 176 | // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*, |
| 177 | // SHUFP* etc. imm. |
| 178 | def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{ |
| 179 | return getI8Imm(X86::getShuffleSHUFImmediate(N)); |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 180 | }]>; |
| 181 | |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 182 | // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to |
| 183 | // PSHUFHW imm. |
| 184 | def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{ |
| 185 | return getI8Imm(X86::getShufflePSHUFHWImmediate(N)); |
| 186 | }]>; |
| 187 | |
| 188 | // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to |
| 189 | // PSHUFLW imm. |
| 190 | def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{ |
| 191 | return getI8Imm(X86::getShufflePSHUFLWImmediate(N)); |
| 192 | }]>; |
| 193 | |
Evan Cheng | 691c923 | 2006-03-29 19:02:40 +0000 | [diff] [blame] | 194 | def SSE_splat_mask : PatLeaf<(build_vector), [{ |
Evan Cheng | 0188ecb | 2006-03-22 18:59:22 +0000 | [diff] [blame] | 195 | return X86::isSplatMask(N); |
Evan Cheng | 691c923 | 2006-03-29 19:02:40 +0000 | [diff] [blame] | 196 | }], SHUFFLE_get_shuf_imm>; |
Evan Cheng | 0188ecb | 2006-03-22 18:59:22 +0000 | [diff] [blame] | 197 | |
Evan Cheng | f686d9b | 2006-10-27 21:08:32 +0000 | [diff] [blame] | 198 | def SSE_splat_lo_mask : PatLeaf<(build_vector), [{ |
| 199 | return X86::isSplatLoMask(N); |
Evan Cheng | d953947 | 2006-04-14 21:59:03 +0000 | [diff] [blame] | 200 | }]>; |
| 201 | |
Evan Cheng | 0b457f0 | 2008-09-25 20:50:48 +0000 | [diff] [blame] | 202 | def MOVDDUP_shuffle_mask : PatLeaf<(build_vector), [{ |
| 203 | return X86::isMOVDDUPMask(N); |
| 204 | }]>; |
| 205 | |
Evan Cheng | 2c0dbd0 | 2006-03-24 02:58:06 +0000 | [diff] [blame] | 206 | def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{ |
| 207 | return X86::isMOVHLPSMask(N); |
Evan Cheng | 4fcb922 | 2006-03-28 02:43:26 +0000 | [diff] [blame] | 208 | }]>; |
Evan Cheng | 2c0dbd0 | 2006-03-24 02:58:06 +0000 | [diff] [blame] | 209 | |
Evan Cheng | 6e56e2c | 2006-11-07 22:14:24 +0000 | [diff] [blame] | 210 | def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{ |
| 211 | return X86::isMOVHLPS_v_undef_Mask(N); |
| 212 | }]>; |
| 213 | |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 214 | def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{ |
| 215 | return X86::isMOVHPMask(N); |
| 216 | }]>; |
| 217 | |
| 218 | def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{ |
| 219 | return X86::isMOVLPMask(N); |
| 220 | }]>; |
| 221 | |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 222 | def MOVL_shuffle_mask : PatLeaf<(build_vector), [{ |
| 223 | return X86::isMOVLMask(N); |
Evan Cheng | d6d1cbd | 2006-04-11 00:19:04 +0000 | [diff] [blame] | 224 | }]>; |
| 225 | |
Evan Cheng | d953947 | 2006-04-14 21:59:03 +0000 | [diff] [blame] | 226 | def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{ |
| 227 | return X86::isMOVSHDUPMask(N); |
| 228 | }]>; |
| 229 | |
| 230 | def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{ |
| 231 | return X86::isMOVSLDUPMask(N); |
| 232 | }]>; |
| 233 | |
Evan Cheng | 0038e59 | 2006-03-28 00:39:58 +0000 | [diff] [blame] | 234 | def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{ |
| 235 | return X86::isUNPCKLMask(N); |
| 236 | }]>; |
| 237 | |
Evan Cheng | 4fcb922 | 2006-03-28 02:43:26 +0000 | [diff] [blame] | 238 | def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{ |
| 239 | return X86::isUNPCKHMask(N); |
| 240 | }]>; |
| 241 | |
Evan Cheng | 1d5a8cc | 2006-04-05 07:20:06 +0000 | [diff] [blame] | 242 | def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{ |
| 243 | return X86::isUNPCKL_v_undef_Mask(N); |
| 244 | }]>; |
| 245 | |
Evan Cheng | 174f803 | 2007-05-17 18:44:37 +0000 | [diff] [blame] | 246 | def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{ |
| 247 | return X86::isUNPCKH_v_undef_Mask(N); |
| 248 | }]>; |
| 249 | |
Evan Cheng | 0188ecb | 2006-03-22 18:59:22 +0000 | [diff] [blame] | 250 | def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{ |
Evan Cheng | 4f56338 | 2006-03-29 01:30:51 +0000 | [diff] [blame] | 251 | return X86::isPSHUFDMask(N); |
Evan Cheng | 14aed5e | 2006-03-24 01:18:28 +0000 | [diff] [blame] | 252 | }], SHUFFLE_get_shuf_imm>; |
Evan Cheng | 0188ecb | 2006-03-22 18:59:22 +0000 | [diff] [blame] | 253 | |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 254 | def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{ |
| 255 | return X86::isPSHUFHWMask(N); |
| 256 | }], SHUFFLE_get_pshufhw_imm>; |
| 257 | |
| 258 | def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{ |
| 259 | return X86::isPSHUFLWMask(N); |
| 260 | }], SHUFFLE_get_pshuflw_imm>; |
| 261 | |
Evan Cheng | 3d60df4 | 2006-04-10 22:35:16 +0000 | [diff] [blame] | 262 | def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{ |
| 263 | return X86::isPSHUFDMask(N); |
Evan Cheng | 7d9061e | 2006-03-30 19:54:57 +0000 | [diff] [blame] | 264 | }], SHUFFLE_get_shuf_imm>; |
| 265 | |
Evan Cheng | 14aed5e | 2006-03-24 01:18:28 +0000 | [diff] [blame] | 266 | def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{ |
| 267 | return X86::isSHUFPMask(N); |
| 268 | }], SHUFFLE_get_shuf_imm>; |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 269 | |
Evan Cheng | 3d60df4 | 2006-04-10 22:35:16 +0000 | [diff] [blame] | 270 | def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{ |
| 271 | return X86::isSHUFPMask(N); |
Evan Cheng | 475aecf | 2006-03-29 03:04:49 +0000 | [diff] [blame] | 272 | }], SHUFFLE_get_shuf_imm>; |
| 273 | |
Nate Begeman | c2616e4 | 2008-05-12 20:34:32 +0000 | [diff] [blame] | 274 | |
Evan Cheng | 06a8aa1 | 2006-03-17 19:55:52 +0000 | [diff] [blame] | 275 | //===----------------------------------------------------------------------===// |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 276 | // SSE scalar FP Instructions |
| 277 | //===----------------------------------------------------------------------===// |
| 278 | |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 279 | // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the |
| 280 | // scheduler into a branch sequence. |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 281 | // These are expanded by the scheduler. |
| 282 | let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in { |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 283 | def CMOV_FR32 : I<0, Pseudo, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 284 | (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond), |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 285 | "#CMOV_FR32 PSEUDO!", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 286 | [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond, |
| 287 | EFLAGS))]>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 288 | def CMOV_FR64 : I<0, Pseudo, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 289 | (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond), |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 290 | "#CMOV_FR64 PSEUDO!", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 291 | [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond, |
| 292 | EFLAGS))]>; |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 293 | def CMOV_V4F32 : I<0, Pseudo, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 294 | (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 295 | "#CMOV_V4F32 PSEUDO!", |
| 296 | [(set VR128:$dst, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 297 | (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond, |
| 298 | EFLAGS)))]>; |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 299 | def CMOV_V2F64 : I<0, Pseudo, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 300 | (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 301 | "#CMOV_V2F64 PSEUDO!", |
| 302 | [(set VR128:$dst, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 303 | (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond, |
| 304 | EFLAGS)))]>; |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 305 | def CMOV_V2I64 : I<0, Pseudo, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 306 | (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 307 | "#CMOV_V2I64 PSEUDO!", |
| 308 | [(set VR128:$dst, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 309 | (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 310 | EFLAGS)))]>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 311 | } |
| 312 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 313 | //===----------------------------------------------------------------------===// |
| 314 | // SSE1 Instructions |
| 315 | //===----------------------------------------------------------------------===// |
| 316 | |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 317 | // Move Instructions |
Chris Lattner | f77e037 | 2008-01-11 06:59:07 +0000 | [diff] [blame] | 318 | let neverHasSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 319 | def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 320 | "movss\t{$src, $dst|$dst, $src}", []>; |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 321 | let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 322 | def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 323 | "movss\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 324 | [(set FR32:$dst, (loadf32 addr:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 325 | def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 326 | "movss\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 327 | [(store FR32:$src, addr:$dst)]>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 328 | |
Evan Cheng | c46349d | 2006-03-28 23:51:43 +0000 | [diff] [blame] | 329 | // Conversion instructions |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 330 | def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 331 | "cvttss2si\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 332 | [(set GR32:$dst, (fp_to_sint FR32:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 333 | def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 334 | "cvttss2si\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 335 | [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 336 | def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 337 | "cvtsi2ss\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 338 | [(set FR32:$dst, (sint_to_fp GR32:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 339 | def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 340 | "cvtsi2ss\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 341 | [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>; |
Evan Cheng | c46349d | 2006-03-28 23:51:43 +0000 | [diff] [blame] | 342 | |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 343 | // Match intrinsics which expect XMM operand(s). |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 344 | def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 345 | "cvtss2si\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 346 | [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 347 | def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 348 | "cvtss2si\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 349 | [(set GR32:$dst, (int_x86_sse_cvtss2si |
| 350 | (load addr:$src)))]>; |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 351 | |
Dale Johannesen | c784208 | 2007-10-30 22:15:38 +0000 | [diff] [blame] | 352 | // Match intrinisics which expect MM and XMM operand(s). |
| 353 | def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), |
| 354 | "cvtps2pi\t{$src, $dst|$dst, $src}", |
| 355 | [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>; |
| 356 | def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src), |
| 357 | "cvtps2pi\t{$src, $dst|$dst, $src}", |
| 358 | [(set VR64:$dst, (int_x86_sse_cvtps2pi |
| 359 | (load addr:$src)))]>; |
| 360 | def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), |
| 361 | "cvttps2pi\t{$src, $dst|$dst, $src}", |
| 362 | [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>; |
| 363 | def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src), |
| 364 | "cvttps2pi\t{$src, $dst|$dst, $src}", |
| 365 | [(set VR64:$dst, (int_x86_sse_cvttps2pi |
| 366 | (load addr:$src)))]>; |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 367 | let Constraints = "$src1 = $dst" in { |
Dale Johannesen | c784208 | 2007-10-30 22:15:38 +0000 | [diff] [blame] | 368 | def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg, |
| 369 | (outs VR128:$dst), (ins VR128:$src1, VR64:$src2), |
| 370 | "cvtpi2ps\t{$src2, $dst|$dst, $src2}", |
| 371 | [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1, |
| 372 | VR64:$src2))]>; |
| 373 | def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem, |
| 374 | (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2), |
| 375 | "cvtpi2ps\t{$src2, $dst|$dst, $src2}", |
| 376 | [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1, |
| 377 | (load addr:$src2)))]>; |
| 378 | } |
| 379 | |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 380 | // Aliases for intrinsics |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 381 | def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 382 | "cvttss2si\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 383 | [(set GR32:$dst, |
| 384 | (int_x86_sse_cvttss2si VR128:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 385 | def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 386 | "cvttss2si\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 387 | [(set GR32:$dst, |
| 388 | (int_x86_sse_cvttss2si(load addr:$src)))]>; |
Evan Cheng | d03db7a | 2006-04-12 05:20:24 +0000 | [diff] [blame] | 389 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 390 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 391 | def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 392 | (outs VR128:$dst), (ins VR128:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 393 | "cvtsi2ss\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 394 | [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1, |
| 395 | GR32:$src2))]>; |
| 396 | def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 397 | (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 398 | "cvtsi2ss\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 399 | [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1, |
| 400 | (loadi32 addr:$src2)))]>; |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 401 | } |
Evan Cheng | d03db7a | 2006-04-12 05:20:24 +0000 | [diff] [blame] | 402 | |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 403 | // Comparison instructions |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 404 | let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in { |
Chris Lattner | d7610e1 | 2007-12-16 20:12:41 +0000 | [diff] [blame] | 405 | def CMPSSrr : SSIi8<0xC2, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 406 | (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 407 | "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>; |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 408 | let mayLoad = 1 in |
Chris Lattner | d7610e1 | 2007-12-16 20:12:41 +0000 | [diff] [blame] | 409 | def CMPSSrm : SSIi8<0xC2, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 410 | (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 411 | "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 412 | } |
| 413 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 414 | let Defs = [EFLAGS] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 415 | def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 416 | "ucomiss\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 417 | [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 418 | def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 419 | "ucomiss\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 420 | [(X86cmp FR32:$src1, (loadf32 addr:$src2)), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 421 | (implicit EFLAGS)]>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 422 | } // Defs = [EFLAGS] |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 423 | |
Evan Cheng | 0876aa5 | 2006-03-30 06:21:22 +0000 | [diff] [blame] | 424 | // Aliases to match intrinsics which expect XMM operand(s). |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 425 | let Constraints = "$src1 = $dst" in { |
Chris Lattner | d7610e1 | 2007-12-16 20:12:41 +0000 | [diff] [blame] | 426 | def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 427 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 428 | "cmp${cc}ss\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 429 | [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1, |
| 430 | VR128:$src, imm:$cc))]>; |
Chris Lattner | d7610e1 | 2007-12-16 20:12:41 +0000 | [diff] [blame] | 431 | def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 432 | (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 433 | "cmp${cc}ss\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 434 | [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1, |
| 435 | (load addr:$src), imm:$cc))]>; |
Evan Cheng | 0876aa5 | 2006-03-30 06:21:22 +0000 | [diff] [blame] | 436 | } |
| 437 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 438 | let Defs = [EFLAGS] in { |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 439 | def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 440 | "ucomiss\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 441 | [(X86ucomi (v4f32 VR128:$src1), VR128:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 442 | (implicit EFLAGS)]>; |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 443 | def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 444 | "ucomiss\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 445 | [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 446 | (implicit EFLAGS)]>; |
| 447 | |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 448 | def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 449 | "comiss\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 450 | [(X86comi (v4f32 VR128:$src1), VR128:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 451 | (implicit EFLAGS)]>; |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 452 | def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 453 | "comiss\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 454 | [(X86comi (v4f32 VR128:$src1), (load addr:$src2)), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 455 | (implicit EFLAGS)]>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 456 | } // Defs = [EFLAGS] |
Evan Cheng | 0876aa5 | 2006-03-30 06:21:22 +0000 | [diff] [blame] | 457 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 458 | // Aliases of packed SSE1 instructions for scalar use. These all have names that |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 459 | // start with 'Fs'. |
| 460 | |
| 461 | // Alias instructions that map fld0 to pxor for sse. |
Evan Cheng | 66e1315 | 2008-08-28 07:52:25 +0000 | [diff] [blame] | 462 | let isReMaterializable = 1, isAsCheapAsAMove = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 463 | def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 464 | "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>, |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 465 | Requires<[HasSSE1]>, TB, OpSize; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 466 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 467 | // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are |
| 468 | // disregarded. |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 469 | let neverHasSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 470 | def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 471 | "movaps\t{$src, $dst|$dst, $src}", []>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 472 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 473 | // Alias instruction to load FR32 from f128mem using movaps. Upper bits are |
| 474 | // disregarded. |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 475 | let canFoldAsLoad = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 476 | def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 477 | "movaps\t{$src, $dst|$dst, $src}", |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 478 | [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 479 | |
| 480 | // Alias bitwise logical operations using SSE logical ops on packed FP values. |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 481 | let Constraints = "$src1 = $dst" in { |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 482 | let isCommutable = 1 in { |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 483 | def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), |
| 484 | (ins FR32:$src1, FR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 485 | "andps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 486 | [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>; |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 487 | def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), |
| 488 | (ins FR32:$src1, FR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 489 | "orps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 490 | [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>; |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 491 | def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), |
| 492 | (ins FR32:$src1, FR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 493 | "xorps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 494 | [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 495 | } |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 496 | |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 497 | def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), |
| 498 | (ins FR32:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 499 | "andps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 500 | [(set FR32:$dst, (X86fand FR32:$src1, |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 501 | (memopfsf32 addr:$src2)))]>; |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 502 | def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), |
| 503 | (ins FR32:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 504 | "orps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 505 | [(set FR32:$dst, (X86for FR32:$src1, |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 506 | (memopfsf32 addr:$src2)))]>; |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 507 | def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), |
| 508 | (ins FR32:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 509 | "xorps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 510 | [(set FR32:$dst, (X86fxor FR32:$src1, |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 511 | (memopfsf32 addr:$src2)))]>; |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 512 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 513 | let neverHasSideEffects = 1 in { |
Dan Gohman | 32791e0 | 2007-06-25 15:44:19 +0000 | [diff] [blame] | 514 | def FsANDNPSrr : PSI<0x55, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 515 | (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 516 | "andnps\t{$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 517 | let mayLoad = 1 in |
Dan Gohman | 32791e0 | 2007-06-25 15:44:19 +0000 | [diff] [blame] | 518 | def FsANDNPSrm : PSI<0x55, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 519 | (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 520 | "andnps\t{$src2, $dst|$dst, $src2}", []>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 521 | } |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 522 | } |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 523 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 524 | /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms. |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 525 | /// |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 526 | /// In addition, we also have a special variant of the scalar form here to |
| 527 | /// represent the associated intrinsic operation. This form is unlike the |
| 528 | /// plain scalar form, in that it takes an entire vector (instead of a scalar) |
Evan Cheng | 236aa8a | 2009-02-26 03:12:02 +0000 | [diff] [blame] | 529 | /// and leaves the top elements unmodified (therefore these cannot be commuted). |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 530 | /// |
| 531 | /// These three forms can each be reg+reg or reg+mem, so there are a total of |
| 532 | /// six "instructions". |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 533 | /// |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 534 | let Constraints = "$src1 = $dst" in { |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 535 | multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr, |
| 536 | SDNode OpNode, Intrinsic F32Int, |
| 537 | bit Commutable = 0> { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 538 | // Scalar operation, reg+reg. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 539 | def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 540 | !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 32791e0 | 2007-06-25 15:44:19 +0000 | [diff] [blame] | 541 | [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 542 | let isCommutable = Commutable; |
| 543 | } |
| 544 | |
| 545 | // Scalar operation, reg+mem. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 546 | def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), |
| 547 | (ins FR32:$src1, f32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 548 | !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 549 | [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>; |
| 550 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 551 | // Vector operation, reg+reg. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 552 | def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), |
| 553 | (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 554 | !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 555 | [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> { |
| 556 | let isCommutable = Commutable; |
| 557 | } |
| 558 | |
| 559 | // Vector operation, reg+mem. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 560 | def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), |
| 561 | (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 562 | !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 563 | [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>; |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 564 | |
| 565 | // Intrinsic operation, reg+reg. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 566 | def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), |
| 567 | (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 568 | !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), |
Evan Cheng | 236aa8a | 2009-02-26 03:12:02 +0000 | [diff] [blame] | 569 | [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 570 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 571 | // Intrinsic operation, reg+mem. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 572 | def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), |
| 573 | (ins VR128:$src1, ssmem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 574 | !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 575 | [(set VR128:$dst, (F32Int VR128:$src1, |
| 576 | sse_load_f32:$src2))]>; |
| 577 | } |
| 578 | } |
| 579 | |
| 580 | // Arithmetic instructions |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 581 | defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>; |
| 582 | defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>; |
| 583 | defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>; |
| 584 | defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 585 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 586 | /// sse1_fp_binop_rm - Other SSE1 binops |
| 587 | /// |
| 588 | /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of |
| 589 | /// instructions for a full-vector intrinsic form. Operations that map |
| 590 | /// onto C operators don't use this form since they just use the plain |
| 591 | /// vector form instead of having a separate vector intrinsic form. |
| 592 | /// |
| 593 | /// This provides a total of eight "instructions". |
| 594 | /// |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 595 | let Constraints = "$src1 = $dst" in { |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 596 | multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr, |
| 597 | SDNode OpNode, |
| 598 | Intrinsic F32Int, |
| 599 | Intrinsic V4F32Int, |
| 600 | bit Commutable = 0> { |
| 601 | |
| 602 | // Scalar operation, reg+reg. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 603 | def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 604 | !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 605 | [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> { |
| 606 | let isCommutable = Commutable; |
| 607 | } |
| 608 | |
| 609 | // Scalar operation, reg+mem. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 610 | def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), |
| 611 | (ins FR32:$src1, f32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 612 | !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 613 | [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>; |
| 614 | |
| 615 | // Vector operation, reg+reg. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 616 | def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), |
| 617 | (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 618 | !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 619 | [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> { |
| 620 | let isCommutable = Commutable; |
| 621 | } |
| 622 | |
| 623 | // Vector operation, reg+mem. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 624 | def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), |
| 625 | (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 626 | !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 627 | [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>; |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 628 | |
| 629 | // Intrinsic operation, reg+reg. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 630 | def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), |
| 631 | (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 632 | !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 633 | [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> { |
| 634 | let isCommutable = Commutable; |
| 635 | } |
| 636 | |
| 637 | // Intrinsic operation, reg+mem. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 638 | def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), |
| 639 | (ins VR128:$src1, ssmem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 640 | !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 641 | [(set VR128:$dst, (F32Int VR128:$src1, |
| 642 | sse_load_f32:$src2))]>; |
| 643 | |
| 644 | // Vector intrinsic operation, reg+reg. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 645 | def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), |
| 646 | (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 647 | !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 648 | [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> { |
| 649 | let isCommutable = Commutable; |
| 650 | } |
| 651 | |
| 652 | // Vector intrinsic operation, reg+mem. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 653 | def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), |
| 654 | (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 655 | !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 656 | [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>; |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 657 | } |
| 658 | } |
| 659 | |
| 660 | defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax, |
| 661 | int_x86_sse_max_ss, int_x86_sse_max_ps>; |
| 662 | defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin, |
| 663 | int_x86_sse_min_ss, int_x86_sse_min_ps>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 664 | |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 665 | //===----------------------------------------------------------------------===// |
Evan Cheng | 9ab1ac5 | 2006-04-14 23:32:40 +0000 | [diff] [blame] | 666 | // SSE packed FP Instructions |
Evan Cheng | c12e6c4 | 2006-03-19 09:38:54 +0000 | [diff] [blame] | 667 | |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 668 | // Move Instructions |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 669 | let neverHasSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 670 | def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 671 | "movaps\t{$src, $dst|$dst, $src}", []>; |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 672 | let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 673 | def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 674 | "movaps\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 675 | [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>; |
Evan Cheng | ffcb95b | 2006-02-21 19:13:53 +0000 | [diff] [blame] | 676 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 677 | def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 678 | "movaps\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 679 | [(alignedstore (v4f32 VR128:$src), addr:$dst)]>; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 680 | |
Chris Lattner | f77e037 | 2008-01-11 06:59:07 +0000 | [diff] [blame] | 681 | let neverHasSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 682 | def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 683 | "movups\t{$src, $dst|$dst, $src}", []>; |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 684 | let canFoldAsLoad = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 685 | def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 686 | "movups\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 687 | [(set VR128:$dst, (loadv4f32 addr:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 688 | def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 689 | "movups\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 690 | [(store (v4f32 VR128:$src), addr:$dst)]>; |
| 691 | |
| 692 | // Intrinsic forms of MOVUPS load and store |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 693 | let canFoldAsLoad = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 694 | def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 695 | "movups\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 696 | [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 697 | def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 698 | "movups\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 699 | [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 700 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 701 | let Constraints = "$src1 = $dst" in { |
Dan Gohman | 32791e0 | 2007-06-25 15:44:19 +0000 | [diff] [blame] | 702 | let AddedComplexity = 20 in { |
| 703 | def MOVLPSrm : PSI<0x12, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 704 | (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 705 | "movlps\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | b70ea0b | 2008-05-10 00:59:18 +0000 | [diff] [blame] | 706 | [(set VR128:$dst, |
| 707 | (v4f32 (vector_shuffle VR128:$src1, |
| 708 | (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))), |
| 709 | MOVLP_shuffle_mask)))]>; |
Dan Gohman | 32791e0 | 2007-06-25 15:44:19 +0000 | [diff] [blame] | 710 | def MOVHPSrm : PSI<0x16, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 711 | (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 712 | "movhps\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | b70ea0b | 2008-05-10 00:59:18 +0000 | [diff] [blame] | 713 | [(set VR128:$dst, |
| 714 | (v4f32 (vector_shuffle VR128:$src1, |
| 715 | (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))), |
| 716 | MOVHP_shuffle_mask)))]>; |
Dan Gohman | 32791e0 | 2007-06-25 15:44:19 +0000 | [diff] [blame] | 717 | } // AddedComplexity |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 718 | } // Constraints = "$src1 = $dst" |
Evan Cheng | 4fcb922 | 2006-03-28 02:43:26 +0000 | [diff] [blame] | 719 | |
Evan Cheng | b70ea0b | 2008-05-10 00:59:18 +0000 | [diff] [blame] | 720 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 721 | def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 722 | "movlps\t{$src, $dst|$dst, $src}", |
Evan Cheng | 664ade7 | 2006-04-07 21:20:58 +0000 | [diff] [blame] | 723 | [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)), |
Evan Cheng | 015188f | 2006-06-15 08:14:54 +0000 | [diff] [blame] | 724 | (iPTR 0))), addr:$dst)]>; |
Evan Cheng | 9bbfd4f | 2006-03-28 07:01:28 +0000 | [diff] [blame] | 725 | |
Evan Cheng | 664ade7 | 2006-04-07 21:20:58 +0000 | [diff] [blame] | 726 | // v2f64 extract element 1 is always custom lowered to unpack high to low |
| 727 | // and extract element 0 so the non-store version isn't too horrible. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 728 | def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 729 | "movhps\t{$src, $dst|$dst, $src}", |
Evan Cheng | 664ade7 | 2006-04-07 21:20:58 +0000 | [diff] [blame] | 730 | [(store (f64 (vector_extract |
| 731 | (v2f64 (vector_shuffle |
| 732 | (bc_v2f64 (v4f32 VR128:$src)), (undef), |
Evan Cheng | 015188f | 2006-06-15 08:14:54 +0000 | [diff] [blame] | 733 | UNPCKH_shuffle_mask)), (iPTR 0))), |
Evan Cheng | 664ade7 | 2006-04-07 21:20:58 +0000 | [diff] [blame] | 734 | addr:$dst)]>; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 735 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 736 | let Constraints = "$src1 = $dst" in { |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 737 | let AddedComplexity = 20 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 738 | def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 739 | "movlhps\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 4fcb922 | 2006-03-28 02:43:26 +0000 | [diff] [blame] | 740 | [(set VR128:$dst, |
Evan Cheng | 2064a2b | 2006-03-28 06:50:32 +0000 | [diff] [blame] | 741 | (v4f32 (vector_shuffle VR128:$src1, VR128:$src2, |
Evan Cheng | 2dadaea | 2006-04-19 20:37:34 +0000 | [diff] [blame] | 742 | MOVHP_shuffle_mask)))]>; |
Evan Cheng | 2c0dbd0 | 2006-03-24 02:58:06 +0000 | [diff] [blame] | 743 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 744 | def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 745 | "movhlps\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 4fcb922 | 2006-03-28 02:43:26 +0000 | [diff] [blame] | 746 | [(set VR128:$dst, |
Evan Cheng | 2064a2b | 2006-03-28 06:50:32 +0000 | [diff] [blame] | 747 | (v4f32 (vector_shuffle VR128:$src1, VR128:$src2, |
Evan Cheng | 4fcb922 | 2006-03-28 02:43:26 +0000 | [diff] [blame] | 748 | MOVHLPS_shuffle_mask)))]>; |
Evan Cheng | 2dadaea | 2006-04-19 20:37:34 +0000 | [diff] [blame] | 749 | } // AddedComplexity |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 750 | } // Constraints = "$src1 = $dst" |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 751 | |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 752 | let AddedComplexity = 20 in |
Evan Cheng | 0b457f0 | 2008-09-25 20:50:48 +0000 | [diff] [blame] | 753 | def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), MOVDDUP_shuffle_mask)), |
| 754 | (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>; |
| 755 | |
| 756 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 757 | |
| 758 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 759 | // Arithmetic |
| 760 | |
| 761 | /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms. |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 762 | /// |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 763 | /// In addition, we also have a special variant of the scalar form here to |
| 764 | /// represent the associated intrinsic operation. This form is unlike the |
| 765 | /// plain scalar form, in that it takes an entire vector (instead of a |
| 766 | /// scalar) and leaves the top elements undefined. |
| 767 | /// |
| 768 | /// And, we have a special variant form for a full-vector intrinsic form. |
| 769 | /// |
| 770 | /// These four forms can each have a reg or a mem operand, so there are a |
| 771 | /// total of eight "instructions". |
| 772 | /// |
| 773 | multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr, |
| 774 | SDNode OpNode, |
| 775 | Intrinsic F32Int, |
| 776 | Intrinsic V4F32Int, |
| 777 | bit Commutable = 0> { |
| 778 | // Scalar operation, reg. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 779 | def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 780 | !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 781 | [(set FR32:$dst, (OpNode FR32:$src))]> { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 782 | let isCommutable = Commutable; |
| 783 | } |
| 784 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 785 | // Scalar operation, mem. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 786 | def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 787 | !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 788 | [(set FR32:$dst, (OpNode (load addr:$src)))]>; |
| 789 | |
| 790 | // Vector operation, reg. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 791 | def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 792 | !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 793 | [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> { |
| 794 | let isCommutable = Commutable; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 795 | } |
| 796 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 797 | // Vector operation, mem. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 798 | def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 799 | !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 800 | [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>; |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 801 | |
| 802 | // Intrinsic operation, reg. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 803 | def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 804 | !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 805 | [(set VR128:$dst, (F32Int VR128:$src))]> { |
| 806 | let isCommutable = Commutable; |
| 807 | } |
| 808 | |
| 809 | // Intrinsic operation, mem. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 810 | def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 811 | !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 812 | [(set VR128:$dst, (F32Int sse_load_f32:$src))]>; |
| 813 | |
| 814 | // Vector intrinsic operation, reg |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 815 | def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 816 | !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 817 | [(set VR128:$dst, (V4F32Int VR128:$src))]> { |
| 818 | let isCommutable = Commutable; |
| 819 | } |
| 820 | |
| 821 | // Vector intrinsic operation, mem |
Dan Gohman | f3372d1 | 2007-08-02 21:06:40 +0000 | [diff] [blame] | 822 | def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 823 | !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 824 | [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 825 | } |
| 826 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 827 | // Square root. |
| 828 | defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt, |
| 829 | int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>; |
| 830 | |
| 831 | // Reciprocal approximations. Note that these typically require refinement |
| 832 | // in order to obtain suitable precision. |
| 833 | defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt, |
| 834 | int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>; |
| 835 | defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp, |
| 836 | int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>; |
| 837 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 838 | // Logical |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 839 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 840 | let isCommutable = 1 in { |
| 841 | def ANDPSrr : PSI<0x54, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 842 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 843 | "andps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 844 | [(set VR128:$dst, (v2i64 |
| 845 | (and VR128:$src1, VR128:$src2)))]>; |
| 846 | def ORPSrr : PSI<0x56, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 847 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 848 | "orps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 849 | [(set VR128:$dst, (v2i64 |
| 850 | (or VR128:$src1, VR128:$src2)))]>; |
| 851 | def XORPSrr : PSI<0x57, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 852 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 853 | "xorps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 854 | [(set VR128:$dst, (v2i64 |
| 855 | (xor VR128:$src1, VR128:$src2)))]>; |
| 856 | } |
| 857 | |
| 858 | def ANDPSrm : PSI<0x54, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 859 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 860 | "andps\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 31d3a65 | 2007-07-19 23:34:10 +0000 | [diff] [blame] | 861 | [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)), |
| 862 | (memopv2i64 addr:$src2)))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 863 | def ORPSrm : PSI<0x56, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 864 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 865 | "orps\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 31d3a65 | 2007-07-19 23:34:10 +0000 | [diff] [blame] | 866 | [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)), |
| 867 | (memopv2i64 addr:$src2)))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 868 | def XORPSrm : PSI<0x57, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 869 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 870 | "xorps\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 31d3a65 | 2007-07-19 23:34:10 +0000 | [diff] [blame] | 871 | [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)), |
| 872 | (memopv2i64 addr:$src2)))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 873 | def ANDNPSrr : PSI<0x55, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 874 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 875 | "andnps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 876 | [(set VR128:$dst, |
| 877 | (v2i64 (and (xor VR128:$src1, |
| 878 | (bc_v2i64 (v4i32 immAllOnesV))), |
| 879 | VR128:$src2)))]>; |
| 880 | def ANDNPSrm : PSI<0x55, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 881 | (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 882 | "andnps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 883 | [(set VR128:$dst, |
Evan Cheng | 31d3a65 | 2007-07-19 23:34:10 +0000 | [diff] [blame] | 884 | (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 885 | (bc_v2i64 (v4i32 immAllOnesV))), |
Evan Cheng | 31d3a65 | 2007-07-19 23:34:10 +0000 | [diff] [blame] | 886 | (memopv2i64 addr:$src2))))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 887 | } |
| 888 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 889 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 890 | def CMPPSrri : PSIi8<0xC2, MRMSrcReg, |
Nate Begeman | c2616e4 | 2008-05-12 20:34:32 +0000 | [diff] [blame] | 891 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), |
| 892 | "cmp${cc}ps\t{$src, $dst|$dst, $src}", |
| 893 | [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1, |
| 894 | VR128:$src, imm:$cc))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 895 | def CMPPSrmi : PSIi8<0xC2, MRMSrcMem, |
Nate Begeman | c2616e4 | 2008-05-12 20:34:32 +0000 | [diff] [blame] | 896 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc), |
| 897 | "cmp${cc}ps\t{$src, $dst|$dst, $src}", |
| 898 | [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1, |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 899 | (memop addr:$src), imm:$cc))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 900 | } |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 901 | def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)), |
| 902 | (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>; |
| 903 | def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)), |
| 904 | (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 905 | |
| 906 | // Shuffle and unpack instructions |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 907 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 908 | let isConvertibleToThreeAddress = 1 in // Convert to pshufd |
| 909 | def SHUFPSrri : PSIi8<0xC6, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 910 | (outs VR128:$dst), (ins VR128:$src1, |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 911 | VR128:$src2, i32i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 912 | "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 913 | [(set VR128:$dst, |
| 914 | (v4f32 (vector_shuffle |
| 915 | VR128:$src1, VR128:$src2, |
| 916 | SHUFP_shuffle_mask:$src3)))]>; |
| 917 | def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 918 | (outs VR128:$dst), (ins VR128:$src1, |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 919 | f128mem:$src2, i32i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 920 | "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 921 | [(set VR128:$dst, |
| 922 | (v4f32 (vector_shuffle |
Dan Gohman | 7f55fcb | 2007-08-02 21:17:01 +0000 | [diff] [blame] | 923 | VR128:$src1, (memopv4f32 addr:$src2), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 924 | SHUFP_shuffle_mask:$src3)))]>; |
| 925 | |
| 926 | let AddedComplexity = 10 in { |
| 927 | def UNPCKHPSrr : PSI<0x15, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 928 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 929 | "unpckhps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 930 | [(set VR128:$dst, |
| 931 | (v4f32 (vector_shuffle |
| 932 | VR128:$src1, VR128:$src2, |
| 933 | UNPCKH_shuffle_mask)))]>; |
| 934 | def UNPCKHPSrm : PSI<0x15, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 935 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 936 | "unpckhps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 937 | [(set VR128:$dst, |
| 938 | (v4f32 (vector_shuffle |
Dan Gohman | 7f55fcb | 2007-08-02 21:17:01 +0000 | [diff] [blame] | 939 | VR128:$src1, (memopv4f32 addr:$src2), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 940 | UNPCKH_shuffle_mask)))]>; |
| 941 | |
| 942 | def UNPCKLPSrr : PSI<0x14, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 943 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 944 | "unpcklps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 945 | [(set VR128:$dst, |
| 946 | (v4f32 (vector_shuffle |
| 947 | VR128:$src1, VR128:$src2, |
| 948 | UNPCKL_shuffle_mask)))]>; |
| 949 | def UNPCKLPSrm : PSI<0x14, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 950 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 951 | "unpcklps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 952 | [(set VR128:$dst, |
| 953 | (v4f32 (vector_shuffle |
Dan Gohman | 7f55fcb | 2007-08-02 21:17:01 +0000 | [diff] [blame] | 954 | VR128:$src1, (memopv4f32 addr:$src2), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 955 | UNPCKL_shuffle_mask)))]>; |
| 956 | } // AddedComplexity |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 957 | } // Constraints = "$src1 = $dst" |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 958 | |
| 959 | // Mask creation |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 960 | def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 961 | "movmskps\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 962 | [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 963 | def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 964 | "movmskpd\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 965 | [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>; |
| 966 | |
Evan Cheng | 27b7db5 | 2008-03-08 00:58:38 +0000 | [diff] [blame] | 967 | // Prefetch intrinsic. |
| 968 | def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src), |
| 969 | "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>; |
| 970 | def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src), |
| 971 | "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>; |
| 972 | def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src), |
| 973 | "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>; |
| 974 | def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src), |
| 975 | "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 976 | |
| 977 | // Non-temporal stores |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 978 | def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 979 | "movntps\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 980 | [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>; |
| 981 | |
| 982 | // Load, store, and memory fence |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 983 | def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 984 | |
| 985 | // MXCSR register |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 986 | def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 987 | "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 988 | def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 989 | "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 990 | |
| 991 | // Alias instructions that map zero vector to pxor / xorp* for sse. |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 992 | // We set canFoldAsLoad because this can be converted to a constant-pool |
Dan Gohman | 62c939d | 2008-12-03 05:21:24 +0000 | [diff] [blame] | 993 | // load of an all-zeros value if folding it would be beneficial. |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 994 | let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 995 | def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 996 | "xorps\t$dst, $dst", |
Chris Lattner | 8a59448 | 2007-11-25 00:24:49 +0000 | [diff] [blame] | 997 | [(set VR128:$dst, (v4i32 immAllZerosV))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 998 | |
Evan Cheng | c8e3b14 | 2008-03-12 07:02:50 +0000 | [diff] [blame] | 999 | let Predicates = [HasSSE1] in { |
| 1000 | def : Pat<(v2i64 immAllZerosV), (V_SET0)>; |
| 1001 | def : Pat<(v8i16 immAllZerosV), (V_SET0)>; |
| 1002 | def : Pat<(v16i8 immAllZerosV), (V_SET0)>; |
| 1003 | def : Pat<(v2f64 immAllZerosV), (V_SET0)>; |
| 1004 | def : Pat<(v4f32 immAllZerosV), (V_SET0)>; |
| 1005 | } |
| 1006 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1007 | // FR32 to 128-bit vector conversion. |
Evan Cheng | b3379fb | 2009-02-05 08:42:55 +0000 | [diff] [blame] | 1008 | let isAsCheapAsAMove = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1009 | def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1010 | "movss\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1011 | [(set VR128:$dst, |
| 1012 | (v4f32 (scalar_to_vector FR32:$src)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1013 | def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1014 | "movss\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1015 | [(set VR128:$dst, |
| 1016 | (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>; |
| 1017 | |
| 1018 | // FIXME: may not be able to eliminate this movss with coalescing the src and |
| 1019 | // dest register classes are different. We really want to write this pattern |
| 1020 | // like this: |
| 1021 | // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), |
| 1022 | // (f32 FR32:$src)>; |
Evan Cheng | b3379fb | 2009-02-05 08:42:55 +0000 | [diff] [blame] | 1023 | let isAsCheapAsAMove = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1024 | def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1025 | "movss\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1026 | [(set FR32:$dst, (vector_extract (v4f32 VR128:$src), |
| 1027 | (iPTR 0)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1028 | def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1029 | "movss\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1030 | [(store (f32 (vector_extract (v4f32 VR128:$src), |
| 1031 | (iPTR 0))), addr:$dst)]>; |
| 1032 | |
| 1033 | |
| 1034 | // Move to lower bits of a VR128, leaving upper bits alone. |
| 1035 | // Three operand (but two address) aliases. |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1036 | let Constraints = "$src1 = $dst" in { |
Chris Lattner | f77e037 | 2008-01-11 06:59:07 +0000 | [diff] [blame] | 1037 | let neverHasSideEffects = 1 in |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1038 | def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1039 | (outs VR128:$dst), (ins VR128:$src1, FR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1040 | "movss\t{$src2, $dst|$dst, $src2}", []>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1041 | |
| 1042 | let AddedComplexity = 15 in |
| 1043 | def MOVLPSrr : SSI<0x10, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1044 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1045 | "movss\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1046 | [(set VR128:$dst, |
| 1047 | (v4f32 (vector_shuffle VR128:$src1, VR128:$src2, |
| 1048 | MOVL_shuffle_mask)))]>; |
| 1049 | } |
| 1050 | |
| 1051 | // Move to lower bits of a VR128 and zeroing upper bits. |
| 1052 | // Loading from memory automatically zeroing upper bits. |
| 1053 | let AddedComplexity = 20 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1054 | def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1055 | "movss\t{$src, $dst|$dst, $src}", |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 1056 | [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector |
Evan Cheng | 7e2ff77 | 2008-05-08 00:57:18 +0000 | [diff] [blame] | 1057 | (loadf32 addr:$src))))))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1058 | |
Evan Cheng | 8e8de68 | 2008-05-20 18:24:47 +0000 | [diff] [blame] | 1059 | def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))), |
Evan Cheng | 7e2ff77 | 2008-05-08 00:57:18 +0000 | [diff] [blame] | 1060 | (MOVZSS2PSrm addr:$src)>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1061 | |
| 1062 | //===----------------------------------------------------------------------===// |
| 1063 | // SSE2 Instructions |
| 1064 | //===----------------------------------------------------------------------===// |
| 1065 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1066 | // Move Instructions |
Chris Lattner | f77e037 | 2008-01-11 06:59:07 +0000 | [diff] [blame] | 1067 | let neverHasSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1068 | def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1069 | "movsd\t{$src, $dst|$dst, $src}", []>; |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 1070 | let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1071 | def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1072 | "movsd\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1073 | [(set FR64:$dst, (loadf64 addr:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1074 | def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1075 | "movsd\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1076 | [(store FR64:$src, addr:$dst)]>; |
| 1077 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1078 | // Conversion instructions |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1079 | def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1080 | "cvttsd2si\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1081 | [(set GR32:$dst, (fp_to_sint FR64:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1082 | def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1083 | "cvttsd2si\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1084 | [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1085 | def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1086 | "cvtsd2ss\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1087 | [(set FR32:$dst, (fround FR64:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1088 | def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1089 | "cvtsd2ss\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1090 | [(set FR32:$dst, (fround (loadf64 addr:$src)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1091 | def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1092 | "cvtsi2sd\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1093 | [(set FR64:$dst, (sint_to_fp GR32:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1094 | def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1095 | "cvtsi2sd\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1096 | [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>; |
| 1097 | |
| 1098 | // SSE2 instructions with XS prefix |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1099 | def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1100 | "cvtss2sd\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1101 | [(set FR64:$dst, (fextend FR32:$src))]>, XS, |
| 1102 | Requires<[HasSSE2]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1103 | def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1104 | "cvtss2sd\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1105 | [(set FR64:$dst, (extloadf32 addr:$src))]>, XS, |
| 1106 | Requires<[HasSSE2]>; |
| 1107 | |
| 1108 | // Match intrinsics which expect XMM operand(s). |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1109 | def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1110 | "cvtsd2si\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1111 | [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1112 | def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1113 | "cvtsd2si\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1114 | [(set GR32:$dst, (int_x86_sse2_cvtsd2si |
| 1115 | (load addr:$src)))]>; |
| 1116 | |
Dale Johannesen | c784208 | 2007-10-30 22:15:38 +0000 | [diff] [blame] | 1117 | // Match intrinisics which expect MM and XMM operand(s). |
| 1118 | def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), |
| 1119 | "cvtpd2pi\t{$src, $dst|$dst, $src}", |
| 1120 | [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>; |
| 1121 | def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src), |
| 1122 | "cvtpd2pi\t{$src, $dst|$dst, $src}", |
| 1123 | [(set VR64:$dst, (int_x86_sse_cvtpd2pi |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1124 | (memop addr:$src)))]>; |
Dale Johannesen | c784208 | 2007-10-30 22:15:38 +0000 | [diff] [blame] | 1125 | def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), |
| 1126 | "cvttpd2pi\t{$src, $dst|$dst, $src}", |
| 1127 | [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>; |
| 1128 | def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src), |
| 1129 | "cvttpd2pi\t{$src, $dst|$dst, $src}", |
| 1130 | [(set VR64:$dst, (int_x86_sse_cvttpd2pi |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1131 | (memop addr:$src)))]>; |
Dale Johannesen | c784208 | 2007-10-30 22:15:38 +0000 | [diff] [blame] | 1132 | def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src), |
| 1133 | "cvtpi2pd\t{$src, $dst|$dst, $src}", |
| 1134 | [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>; |
| 1135 | def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), |
| 1136 | "cvtpi2pd\t{$src, $dst|$dst, $src}", |
| 1137 | [(set VR128:$dst, (int_x86_sse_cvtpi2pd |
| 1138 | (load addr:$src)))]>; |
| 1139 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1140 | // Aliases for intrinsics |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1141 | def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1142 | "cvttsd2si\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1143 | [(set GR32:$dst, |
| 1144 | (int_x86_sse2_cvttsd2si VR128:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1145 | def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1146 | "cvttsd2si\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1147 | [(set GR32:$dst, (int_x86_sse2_cvttsd2si |
| 1148 | (load addr:$src)))]>; |
| 1149 | |
| 1150 | // Comparison instructions |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1151 | let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in { |
Evan Cheng | 700a0fb | 2007-12-20 19:57:09 +0000 | [diff] [blame] | 1152 | def CMPSDrr : SDIi8<0xC2, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1153 | (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1154 | "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>; |
Chris Lattner | f77e037 | 2008-01-11 06:59:07 +0000 | [diff] [blame] | 1155 | let mayLoad = 1 in |
Evan Cheng | 700a0fb | 2007-12-20 19:57:09 +0000 | [diff] [blame] | 1156 | def CMPSDrm : SDIi8<0xC2, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1157 | (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1158 | "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1159 | } |
| 1160 | |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1161 | let Defs = [EFLAGS] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1162 | def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1163 | "ucomisd\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1164 | [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1165 | def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1166 | "ucomisd\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1167 | [(X86cmp FR64:$src1, (loadf64 addr:$src2)), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1168 | (implicit EFLAGS)]>; |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 1169 | } // Defs = [EFLAGS] |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1170 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1171 | // Aliases to match intrinsics which expect XMM operand(s). |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1172 | let Constraints = "$src1 = $dst" in { |
Evan Cheng | 700a0fb | 2007-12-20 19:57:09 +0000 | [diff] [blame] | 1173 | def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1174 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1175 | "cmp${cc}sd\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1176 | [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1, |
| 1177 | VR128:$src, imm:$cc))]>; |
Evan Cheng | 700a0fb | 2007-12-20 19:57:09 +0000 | [diff] [blame] | 1178 | def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1179 | (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1180 | "cmp${cc}sd\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1181 | [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1, |
| 1182 | (load addr:$src), imm:$cc))]>; |
| 1183 | } |
| 1184 | |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1185 | let Defs = [EFLAGS] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1186 | def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1187 | "ucomisd\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1188 | [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)), |
| 1189 | (implicit EFLAGS)]>; |
| 1190 | def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1191 | "ucomisd\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1192 | [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)), |
| 1193 | (implicit EFLAGS)]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1194 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1195 | def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1196 | "comisd\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1197 | [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)), |
| 1198 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1199 | def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1200 | "comisd\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1201 | [(X86comi (v2f64 VR128:$src1), (load addr:$src2)), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1202 | (implicit EFLAGS)]>; |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 1203 | } // Defs = [EFLAGS] |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1204 | |
Dan Gohman | 32791e0 | 2007-06-25 15:44:19 +0000 | [diff] [blame] | 1205 | // Aliases of packed SSE2 instructions for scalar use. These all have names that |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1206 | // start with 'Fs'. |
| 1207 | |
| 1208 | // Alias instructions that map fld0 to pxor for sse. |
Evan Cheng | 66e1315 | 2008-08-28 07:52:25 +0000 | [diff] [blame] | 1209 | let isReMaterializable = 1, isAsCheapAsAMove = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1210 | def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1211 | "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>, |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1212 | Requires<[HasSSE2]>, TB, OpSize; |
| 1213 | |
Dan Gohman | 32791e0 | 2007-06-25 15:44:19 +0000 | [diff] [blame] | 1214 | // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1215 | // disregarded. |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1216 | let neverHasSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1217 | def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1218 | "movapd\t{$src, $dst|$dst, $src}", []>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1219 | |
Dan Gohman | 32791e0 | 2007-06-25 15:44:19 +0000 | [diff] [blame] | 1220 | // Alias instruction to load FR64 from f128mem using movapd. Upper bits are |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1221 | // disregarded. |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 1222 | let canFoldAsLoad = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1223 | def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1224 | "movapd\t{$src, $dst|$dst, $src}", |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 1225 | [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1226 | |
| 1227 | // Alias bitwise logical operations using SSE logical ops on packed FP values. |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1228 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1229 | let isCommutable = 1 in { |
Evan Cheng | b609339 | 2008-05-02 07:53:32 +0000 | [diff] [blame] | 1230 | def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst), |
| 1231 | (ins FR64:$src1, FR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1232 | "andpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1233 | [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>; |
Evan Cheng | b609339 | 2008-05-02 07:53:32 +0000 | [diff] [blame] | 1234 | def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst), |
| 1235 | (ins FR64:$src1, FR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1236 | "orpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1237 | [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>; |
Evan Cheng | b609339 | 2008-05-02 07:53:32 +0000 | [diff] [blame] | 1238 | def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst), |
| 1239 | (ins FR64:$src1, FR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1240 | "xorpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1241 | [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>; |
| 1242 | } |
| 1243 | |
Evan Cheng | b609339 | 2008-05-02 07:53:32 +0000 | [diff] [blame] | 1244 | def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst), |
| 1245 | (ins FR64:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1246 | "andpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1247 | [(set FR64:$dst, (X86fand FR64:$src1, |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 1248 | (memopfsf64 addr:$src2)))]>; |
Evan Cheng | b609339 | 2008-05-02 07:53:32 +0000 | [diff] [blame] | 1249 | def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst), |
| 1250 | (ins FR64:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1251 | "orpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1252 | [(set FR64:$dst, (X86for FR64:$src1, |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 1253 | (memopfsf64 addr:$src2)))]>; |
Evan Cheng | b609339 | 2008-05-02 07:53:32 +0000 | [diff] [blame] | 1254 | def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst), |
| 1255 | (ins FR64:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1256 | "xorpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1257 | [(set FR64:$dst, (X86fxor FR64:$src1, |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 1258 | (memopfsf64 addr:$src2)))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1259 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1260 | let neverHasSideEffects = 1 in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1261 | def FsANDNPDrr : PDI<0x55, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1262 | (outs FR64:$dst), (ins FR64:$src1, FR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1263 | "andnpd\t{$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1264 | let mayLoad = 1 in |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1265 | def FsANDNPDrm : PDI<0x55, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1266 | (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1267 | "andnpd\t{$src2, $dst|$dst, $src2}", []>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1268 | } |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1269 | } |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1270 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1271 | /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms. |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1272 | /// |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1273 | /// In addition, we also have a special variant of the scalar form here to |
| 1274 | /// represent the associated intrinsic operation. This form is unlike the |
| 1275 | /// plain scalar form, in that it takes an entire vector (instead of a scalar) |
Evan Cheng | 236aa8a | 2009-02-26 03:12:02 +0000 | [diff] [blame] | 1276 | /// and leaves the top elements unmodified (therefore these cannot be commuted). |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1277 | /// |
| 1278 | /// These three forms can each be reg+reg or reg+mem, so there are a total of |
| 1279 | /// six "instructions". |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1280 | /// |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1281 | let Constraints = "$src1 = $dst" in { |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1282 | multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr, |
| 1283 | SDNode OpNode, Intrinsic F64Int, |
| 1284 | bit Commutable = 0> { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1285 | // Scalar operation, reg+reg. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1286 | def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1287 | !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1288 | [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> { |
| 1289 | let isCommutable = Commutable; |
| 1290 | } |
| 1291 | |
| 1292 | // Scalar operation, reg+mem. |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 1293 | def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), |
| 1294 | (ins FR64:$src1, f64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1295 | !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1296 | [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>; |
| 1297 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1298 | // Vector operation, reg+reg. |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 1299 | def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), |
| 1300 | (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1301 | !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1302 | [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> { |
| 1303 | let isCommutable = Commutable; |
| 1304 | } |
| 1305 | |
| 1306 | // Vector operation, reg+mem. |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 1307 | def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), |
| 1308 | (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1309 | !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 1310 | [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>; |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1311 | |
| 1312 | // Intrinsic operation, reg+reg. |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 1313 | def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), |
| 1314 | (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1315 | !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"), |
Evan Cheng | 236aa8a | 2009-02-26 03:12:02 +0000 | [diff] [blame] | 1316 | [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1317 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1318 | // Intrinsic operation, reg+mem. |
Dan Gohman | b134709 | 2009-01-09 02:27:34 +0000 | [diff] [blame] | 1319 | def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), |
| 1320 | (ins VR128:$src1, sdmem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1321 | !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1322 | [(set VR128:$dst, (F64Int VR128:$src1, |
| 1323 | sse_load_f64:$src2))]>; |
| 1324 | } |
| 1325 | } |
| 1326 | |
| 1327 | // Arithmetic instructions |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1328 | defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>; |
| 1329 | defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>; |
| 1330 | defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>; |
| 1331 | defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1332 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1333 | /// sse2_fp_binop_rm - Other SSE2 binops |
| 1334 | /// |
| 1335 | /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of |
| 1336 | /// instructions for a full-vector intrinsic form. Operations that map |
| 1337 | /// onto C operators don't use this form since they just use the plain |
| 1338 | /// vector form instead of having a separate vector intrinsic form. |
| 1339 | /// |
| 1340 | /// This provides a total of eight "instructions". |
| 1341 | /// |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1342 | let Constraints = "$src1 = $dst" in { |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1343 | multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr, |
| 1344 | SDNode OpNode, |
| 1345 | Intrinsic F64Int, |
| 1346 | Intrinsic V2F64Int, |
| 1347 | bit Commutable = 0> { |
| 1348 | |
| 1349 | // Scalar operation, reg+reg. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1350 | def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1351 | !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1352 | [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> { |
| 1353 | let isCommutable = Commutable; |
| 1354 | } |
| 1355 | |
| 1356 | // Scalar operation, reg+mem. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1357 | def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), |
| 1358 | (ins FR64:$src1, f64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1359 | !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1360 | [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>; |
| 1361 | |
| 1362 | // Vector operation, reg+reg. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1363 | def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), |
| 1364 | (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1365 | !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1366 | [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> { |
| 1367 | let isCommutable = Commutable; |
| 1368 | } |
| 1369 | |
| 1370 | // Vector operation, reg+mem. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1371 | def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), |
| 1372 | (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1373 | !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1374 | [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>; |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1375 | |
| 1376 | // Intrinsic operation, reg+reg. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1377 | def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), |
| 1378 | (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1379 | !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1380 | [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> { |
| 1381 | let isCommutable = Commutable; |
| 1382 | } |
| 1383 | |
| 1384 | // Intrinsic operation, reg+mem. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1385 | def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), |
| 1386 | (ins VR128:$src1, sdmem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1387 | !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1388 | [(set VR128:$dst, (F64Int VR128:$src1, |
| 1389 | sse_load_f64:$src2))]>; |
| 1390 | |
| 1391 | // Vector intrinsic operation, reg+reg. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1392 | def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), |
| 1393 | (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1394 | !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1395 | [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> { |
| 1396 | let isCommutable = Commutable; |
| 1397 | } |
| 1398 | |
| 1399 | // Vector intrinsic operation, reg+mem. |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1400 | def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), |
| 1401 | (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1402 | !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1403 | [(set VR128:$dst, (V2F64Int VR128:$src1, |
| 1404 | (memopv2f64 addr:$src2)))]>; |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1405 | } |
| 1406 | } |
| 1407 | |
| 1408 | defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax, |
| 1409 | int_x86_sse2_max_sd, int_x86_sse2_max_pd>; |
| 1410 | defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin, |
| 1411 | int_x86_sse2_min_sd, int_x86_sse2_min_pd>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1412 | |
| 1413 | //===----------------------------------------------------------------------===// |
| 1414 | // SSE packed FP Instructions |
| 1415 | |
| 1416 | // Move Instructions |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1417 | let neverHasSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1418 | def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1419 | "movapd\t{$src, $dst|$dst, $src}", []>; |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 1420 | let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1421 | def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1422 | "movapd\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 1423 | [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1424 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1425 | def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1426 | "movapd\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 1427 | [(alignedstore (v2f64 VR128:$src), addr:$dst)]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1428 | |
Chris Lattner | f77e037 | 2008-01-11 06:59:07 +0000 | [diff] [blame] | 1429 | let neverHasSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1430 | def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1431 | "movupd\t{$src, $dst|$dst, $src}", []>; |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 1432 | let canFoldAsLoad = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1433 | def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1434 | "movupd\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 1435 | [(set VR128:$dst, (loadv2f64 addr:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1436 | def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1437 | "movupd\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 1438 | [(store (v2f64 VR128:$src), addr:$dst)]>; |
| 1439 | |
| 1440 | // Intrinsic forms of MOVUPD load and store |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1441 | def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1442 | "movupd\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 1443 | [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1444 | def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1445 | "movupd\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 1446 | [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1447 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1448 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1449 | let AddedComplexity = 20 in { |
| 1450 | def MOVLPDrm : PDI<0x12, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1451 | (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1452 | "movlpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1453 | [(set VR128:$dst, |
| 1454 | (v2f64 (vector_shuffle VR128:$src1, |
| 1455 | (scalar_to_vector (loadf64 addr:$src2)), |
| 1456 | MOVLP_shuffle_mask)))]>; |
| 1457 | def MOVHPDrm : PDI<0x16, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1458 | (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1459 | "movhpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1460 | [(set VR128:$dst, |
| 1461 | (v2f64 (vector_shuffle VR128:$src1, |
| 1462 | (scalar_to_vector (loadf64 addr:$src2)), |
| 1463 | MOVHP_shuffle_mask)))]>; |
| 1464 | } // AddedComplexity |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1465 | } // Constraints = "$src1 = $dst" |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1466 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1467 | def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1468 | "movlpd\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1469 | [(store (f64 (vector_extract (v2f64 VR128:$src), |
| 1470 | (iPTR 0))), addr:$dst)]>; |
| 1471 | |
| 1472 | // v2f64 extract element 1 is always custom lowered to unpack high to low |
| 1473 | // and extract element 0 so the non-store version isn't too horrible. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1474 | def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1475 | "movhpd\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1476 | [(store (f64 (vector_extract |
| 1477 | (v2f64 (vector_shuffle VR128:$src, (undef), |
| 1478 | UNPCKH_shuffle_mask)), (iPTR 0))), |
| 1479 | addr:$dst)]>; |
Evan Cheng | d953947 | 2006-04-14 21:59:03 +0000 | [diff] [blame] | 1480 | |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 1481 | // SSE2 instructions without OpSize prefix |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1482 | def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1483 | "cvtdq2ps\t{$src, $dst|$dst, $src}", |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1484 | [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>, |
| 1485 | TB, Requires<[HasSSE2]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1486 | def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), |
Evan Cheng | 029d9da | 2008-03-14 07:46:48 +0000 | [diff] [blame] | 1487 | "cvtdq2ps\t{$src, $dst|$dst, $src}", |
| 1488 | [(set VR128:$dst, (int_x86_sse2_cvtdq2ps |
| 1489 | (bitconvert (memopv2i64 addr:$src))))]>, |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1490 | TB, Requires<[HasSSE2]>; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 1491 | |
| 1492 | // SSE2 instructions with XS prefix |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1493 | def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1494 | "cvtdq2pd\t{$src, $dst|$dst, $src}", |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1495 | [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>, |
| 1496 | XS, Requires<[HasSSE2]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1497 | def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), |
Evan Cheng | 029d9da | 2008-03-14 07:46:48 +0000 | [diff] [blame] | 1498 | "cvtdq2pd\t{$src, $dst|$dst, $src}", |
| 1499 | [(set VR128:$dst, (int_x86_sse2_cvtdq2pd |
| 1500 | (bitconvert (memopv2i64 addr:$src))))]>, |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1501 | XS, Requires<[HasSSE2]>; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 1502 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1503 | def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Evan Cheng | 029d9da | 2008-03-14 07:46:48 +0000 | [diff] [blame] | 1504 | "cvtps2dq\t{$src, $dst|$dst, $src}", |
| 1505 | [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1506 | def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1507 | "cvtps2dq\t{$src, $dst|$dst, $src}", |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1508 | [(set VR128:$dst, (int_x86_sse2_cvtps2dq |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1509 | (memop addr:$src)))]>; |
Evan Cheng | d03db7a | 2006-04-12 05:20:24 +0000 | [diff] [blame] | 1510 | // SSE2 packed instructions with XS prefix |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1511 | def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1512 | "cvttps2dq\t{$src, $dst|$dst, $src}", |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1513 | [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>, |
| 1514 | XS, Requires<[HasSSE2]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1515 | def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1516 | "cvttps2dq\t{$src, $dst|$dst, $src}", |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1517 | [(set VR128:$dst, (int_x86_sse2_cvttps2dq |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1518 | (memop addr:$src)))]>, |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1519 | XS, Requires<[HasSSE2]>; |
Evan Cheng | d03db7a | 2006-04-12 05:20:24 +0000 | [diff] [blame] | 1520 | |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 1521 | // SSE2 packed instructions with XD prefix |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1522 | def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1523 | "cvtpd2dq\t{$src, $dst|$dst, $src}", |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1524 | [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>, |
| 1525 | XD, Requires<[HasSSE2]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1526 | def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1527 | "cvtpd2dq\t{$src, $dst|$dst, $src}", |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1528 | [(set VR128:$dst, (int_x86_sse2_cvtpd2dq |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1529 | (memop addr:$src)))]>, |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1530 | XD, Requires<[HasSSE2]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1531 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1532 | def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1533 | "cvttpd2dq\t{$src, $dst|$dst, $src}", |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1534 | [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>; |
Evan Cheng | 029d9da | 2008-03-14 07:46:48 +0000 | [diff] [blame] | 1535 | def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1536 | "cvttpd2dq\t{$src, $dst|$dst, $src}", |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1537 | [(set VR128:$dst, (int_x86_sse2_cvttpd2dq |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1538 | (memop addr:$src)))]>; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 1539 | |
| 1540 | // SSE2 instructions without OpSize prefix |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1541 | def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1542 | "cvtps2pd\t{$src, $dst|$dst, $src}", |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1543 | [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>, |
| 1544 | TB, Requires<[HasSSE2]>; |
Mon P Wang | bfbbd4d | 2008-05-28 00:42:27 +0000 | [diff] [blame] | 1545 | def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1546 | "cvtps2pd\t{$src, $dst|$dst, $src}", |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1547 | [(set VR128:$dst, (int_x86_sse2_cvtps2pd |
Chris Lattner | 15258d5 | 2006-10-07 06:17:43 +0000 | [diff] [blame] | 1548 | (load addr:$src)))]>, |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1549 | TB, Requires<[HasSSE2]>; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 1550 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1551 | def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1552 | "cvtpd2ps\t{$src, $dst|$dst, $src}", |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1553 | [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>; |
Mon P Wang | bfbbd4d | 2008-05-28 00:42:27 +0000 | [diff] [blame] | 1554 | def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1555 | "cvtpd2ps\t{$src, $dst|$dst, $src}", |
Evan Cheng | 190717d | 2006-05-31 19:00:07 +0000 | [diff] [blame] | 1556 | [(set VR128:$dst, (int_x86_sse2_cvtpd2ps |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1557 | (memop addr:$src)))]>; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 1558 | |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 1559 | // Match intrinsics which expect XMM operand(s). |
| 1560 | // Aliases for intrinsics |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1561 | let Constraints = "$src1 = $dst" in { |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 1562 | def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1563 | (outs VR128:$dst), (ins VR128:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1564 | "cvtsi2sd\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 1565 | [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1566 | GR32:$src2))]>; |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 1567 | def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1568 | (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1569 | "cvtsi2sd\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 1570 | [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1, |
| 1571 | (loadi32 addr:$src2)))]>; |
| 1572 | def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1573 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1574 | "cvtsd2ss\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 1575 | [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1, |
| 1576 | VR128:$src2))]>; |
| 1577 | def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1578 | (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1579 | "cvtsd2ss\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 1580 | [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1, |
Chris Lattner | 15258d5 | 2006-10-07 06:17:43 +0000 | [diff] [blame] | 1581 | (load addr:$src2)))]>; |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 1582 | def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1583 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1584 | "cvtss2sd\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 1585 | [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1, |
| 1586 | VR128:$src2))]>, XS, |
| 1587 | Requires<[HasSSE2]>; |
| 1588 | def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1589 | (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1590 | "cvtss2sd\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 1591 | [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1, |
Chris Lattner | 15258d5 | 2006-10-07 06:17:43 +0000 | [diff] [blame] | 1592 | (load addr:$src2)))]>, XS, |
Evan Cheng | d2a6d54 | 2006-04-12 23:42:44 +0000 | [diff] [blame] | 1593 | Requires<[HasSSE2]>; |
| 1594 | } |
| 1595 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1596 | // Arithmetic |
| 1597 | |
| 1598 | /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms. |
Chris Lattner | 6f98773 | 2006-10-07 21:17:13 +0000 | [diff] [blame] | 1599 | /// |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1600 | /// In addition, we also have a special variant of the scalar form here to |
| 1601 | /// represent the associated intrinsic operation. This form is unlike the |
| 1602 | /// plain scalar form, in that it takes an entire vector (instead of a |
| 1603 | /// scalar) and leaves the top elements undefined. |
| 1604 | /// |
| 1605 | /// And, we have a special variant form for a full-vector intrinsic form. |
| 1606 | /// |
| 1607 | /// These four forms can each have a reg or a mem operand, so there are a |
| 1608 | /// total of eight "instructions". |
| 1609 | /// |
| 1610 | multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr, |
| 1611 | SDNode OpNode, |
| 1612 | Intrinsic F64Int, |
| 1613 | Intrinsic V2F64Int, |
| 1614 | bit Commutable = 0> { |
| 1615 | // Scalar operation, reg. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1616 | def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1617 | !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1618 | [(set FR64:$dst, (OpNode FR64:$src))]> { |
Chris Lattner | 6f98773 | 2006-10-07 21:17:13 +0000 | [diff] [blame] | 1619 | let isCommutable = Commutable; |
| 1620 | } |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1621 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1622 | // Scalar operation, mem. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1623 | def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1624 | !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1625 | [(set FR64:$dst, (OpNode (load addr:$src)))]>; |
| 1626 | |
| 1627 | // Vector operation, reg. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1628 | def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1629 | !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1630 | [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> { |
| 1631 | let isCommutable = Commutable; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1632 | } |
| 1633 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1634 | // Vector operation, mem. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1635 | def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1636 | !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 1637 | [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>; |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1638 | |
| 1639 | // Intrinsic operation, reg. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1640 | def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1641 | !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1642 | [(set VR128:$dst, (F64Int VR128:$src))]> { |
| 1643 | let isCommutable = Commutable; |
| 1644 | } |
| 1645 | |
| 1646 | // Intrinsic operation, mem. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1647 | def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1648 | !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1649 | [(set VR128:$dst, (F64Int sse_load_f64:$src))]>; |
| 1650 | |
| 1651 | // Vector intrinsic operation, reg |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1652 | def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1653 | !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"), |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1654 | [(set VR128:$dst, (V2F64Int VR128:$src))]> { |
| 1655 | let isCommutable = Commutable; |
| 1656 | } |
| 1657 | |
| 1658 | // Vector intrinsic operation, mem |
Dan Gohman | f3372d1 | 2007-08-02 21:06:40 +0000 | [diff] [blame] | 1659 | def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1660 | !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1661 | [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>; |
Evan Cheng | 97ac5fa | 2006-04-03 23:49:17 +0000 | [diff] [blame] | 1662 | } |
Evan Cheng | ffcb95b | 2006-02-21 19:13:53 +0000 | [diff] [blame] | 1663 | |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 1664 | // Square root. |
| 1665 | defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt, |
| 1666 | int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>; |
| 1667 | |
| 1668 | // There is no f64 version of the reciprocal approximation instructions. |
| 1669 | |
Evan Cheng | ffcb95b | 2006-02-21 19:13:53 +0000 | [diff] [blame] | 1670 | // Logical |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1671 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1672 | let isCommutable = 1 in { |
| 1673 | def ANDPDrr : PDI<0x54, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1674 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1675 | "andpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1676 | [(set VR128:$dst, |
| 1677 | (and (bc_v2i64 (v2f64 VR128:$src1)), |
Chris Lattner | 3b57a83 | 2006-10-07 06:27:03 +0000 | [diff] [blame] | 1678 | (bc_v2i64 (v2f64 VR128:$src2))))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1679 | def ORPDrr : PDI<0x56, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1680 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1681 | "orpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1682 | [(set VR128:$dst, |
| 1683 | (or (bc_v2i64 (v2f64 VR128:$src1)), |
| 1684 | (bc_v2i64 (v2f64 VR128:$src2))))]>; |
| 1685 | def XORPDrr : PDI<0x57, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1686 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1687 | "xorpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1688 | [(set VR128:$dst, |
| 1689 | (xor (bc_v2i64 (v2f64 VR128:$src1)), |
| 1690 | (bc_v2i64 (v2f64 VR128:$src2))))]>; |
| 1691 | } |
| 1692 | |
| 1693 | def ANDPDrm : PDI<0x54, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1694 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1695 | "andpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1696 | [(set VR128:$dst, |
| 1697 | (and (bc_v2i64 (v2f64 VR128:$src1)), |
Evan Cheng | 31d3a65 | 2007-07-19 23:34:10 +0000 | [diff] [blame] | 1698 | (memopv2i64 addr:$src2)))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1699 | def ORPDrm : PDI<0x56, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1700 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1701 | "orpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1702 | [(set VR128:$dst, |
| 1703 | (or (bc_v2i64 (v2f64 VR128:$src1)), |
Evan Cheng | 31d3a65 | 2007-07-19 23:34:10 +0000 | [diff] [blame] | 1704 | (memopv2i64 addr:$src2)))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1705 | def XORPDrm : PDI<0x57, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1706 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1707 | "xorpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1708 | [(set VR128:$dst, |
| 1709 | (xor (bc_v2i64 (v2f64 VR128:$src1)), |
Evan Cheng | 31d3a65 | 2007-07-19 23:34:10 +0000 | [diff] [blame] | 1710 | (memopv2i64 addr:$src2)))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1711 | def ANDNPDrr : PDI<0x55, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1712 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1713 | "andnpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1714 | [(set VR128:$dst, |
| 1715 | (and (vnot (bc_v2i64 (v2f64 VR128:$src1))), |
Chris Lattner | 3b57a83 | 2006-10-07 06:27:03 +0000 | [diff] [blame] | 1716 | (bc_v2i64 (v2f64 VR128:$src2))))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1717 | def ANDNPDrm : PDI<0x55, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1718 | (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1719 | "andnpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1720 | [(set VR128:$dst, |
| 1721 | (and (vnot (bc_v2i64 (v2f64 VR128:$src1))), |
Evan Cheng | 31d3a65 | 2007-07-19 23:34:10 +0000 | [diff] [blame] | 1722 | (memopv2i64 addr:$src2)))]>; |
Evan Cheng | ffcb95b | 2006-02-21 19:13:53 +0000 | [diff] [blame] | 1723 | } |
Evan Cheng | bf156d1 | 2006-02-21 19:26:52 +0000 | [diff] [blame] | 1724 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1725 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1726 | def CMPPDrri : PDIi8<0xC2, MRMSrcReg, |
Evan Cheng | 029d9da | 2008-03-14 07:46:48 +0000 | [diff] [blame] | 1727 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), |
| 1728 | "cmp${cc}pd\t{$src, $dst|$dst, $src}", |
| 1729 | [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1, |
Nate Begeman | c2616e4 | 2008-05-12 20:34:32 +0000 | [diff] [blame] | 1730 | VR128:$src, imm:$cc))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1731 | def CMPPDrmi : PDIi8<0xC2, MRMSrcMem, |
Evan Cheng | 029d9da | 2008-03-14 07:46:48 +0000 | [diff] [blame] | 1732 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc), |
| 1733 | "cmp${cc}pd\t{$src, $dst|$dst, $src}", |
| 1734 | [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1, |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 1735 | (memop addr:$src), imm:$cc))]>; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 1736 | } |
Evan Cheng | e9d5035 | 2008-08-05 22:19:15 +0000 | [diff] [blame] | 1737 | def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)), |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 1738 | (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>; |
Evan Cheng | e9d5035 | 2008-08-05 22:19:15 +0000 | [diff] [blame] | 1739 | def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)), |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 1740 | (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 1741 | |
| 1742 | // Shuffle and unpack instructions |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1743 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1744 | def SHUFPDrri : PDIi8<0xC6, MRMSrcReg, |
Evan Cheng | 029d9da | 2008-03-14 07:46:48 +0000 | [diff] [blame] | 1745 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3), |
| 1746 | "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 1747 | [(set VR128:$dst, (v2f64 (vector_shuffle |
| 1748 | VR128:$src1, VR128:$src2, |
| 1749 | SHUFP_shuffle_mask:$src3)))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1750 | def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1751 | (outs VR128:$dst), (ins VR128:$src1, |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1752 | f128mem:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1753 | "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1754 | [(set VR128:$dst, |
| 1755 | (v2f64 (vector_shuffle |
Dan Gohman | 7f55fcb | 2007-08-02 21:17:01 +0000 | [diff] [blame] | 1756 | VR128:$src1, (memopv2f64 addr:$src2), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1757 | SHUFP_shuffle_mask:$src3)))]>; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 1758 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1759 | let AddedComplexity = 10 in { |
| 1760 | def UNPCKHPDrr : PDI<0x15, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1761 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1762 | "unpckhpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1763 | [(set VR128:$dst, |
| 1764 | (v2f64 (vector_shuffle |
| 1765 | VR128:$src1, VR128:$src2, |
| 1766 | UNPCKH_shuffle_mask)))]>; |
| 1767 | def UNPCKHPDrm : PDI<0x15, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1768 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1769 | "unpckhpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1770 | [(set VR128:$dst, |
| 1771 | (v2f64 (vector_shuffle |
Dan Gohman | 7f55fcb | 2007-08-02 21:17:01 +0000 | [diff] [blame] | 1772 | VR128:$src1, (memopv2f64 addr:$src2), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1773 | UNPCKH_shuffle_mask)))]>; |
Evan Cheng | 4fcb922 | 2006-03-28 02:43:26 +0000 | [diff] [blame] | 1774 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1775 | def UNPCKLPDrr : PDI<0x14, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1776 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1777 | "unpcklpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1778 | [(set VR128:$dst, |
| 1779 | (v2f64 (vector_shuffle |
| 1780 | VR128:$src1, VR128:$src2, |
| 1781 | UNPCKL_shuffle_mask)))]>; |
| 1782 | def UNPCKLPDrm : PDI<0x14, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1783 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1784 | "unpcklpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1785 | [(set VR128:$dst, |
| 1786 | (v2f64 (vector_shuffle |
Dan Gohman | 7f55fcb | 2007-08-02 21:17:01 +0000 | [diff] [blame] | 1787 | VR128:$src1, (memopv2f64 addr:$src2), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1788 | UNPCKL_shuffle_mask)))]>; |
| 1789 | } // AddedComplexity |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1790 | } // Constraints = "$src1 = $dst" |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 1791 | |
Evan Cheng | 4b1734f | 2006-03-31 21:29:33 +0000 | [diff] [blame] | 1792 | |
Evan Cheng | bf156d1 | 2006-02-21 19:26:52 +0000 | [diff] [blame] | 1793 | //===----------------------------------------------------------------------===// |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 1794 | // SSE integer instructions |
Evan Cheng | bf156d1 | 2006-02-21 19:26:52 +0000 | [diff] [blame] | 1795 | |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 1796 | // Move Instructions |
Chris Lattner | f77e037 | 2008-01-11 06:59:07 +0000 | [diff] [blame] | 1797 | let neverHasSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1798 | def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1799 | "movdqa\t{$src, $dst|$dst, $src}", []>; |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 1800 | let canFoldAsLoad = 1, mayLoad = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1801 | def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1802 | "movdqa\t{$src, $dst|$dst, $src}", |
Evan Cheng | b4162fd | 2007-07-20 00:27:43 +0000 | [diff] [blame] | 1803 | [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>; |
Chris Lattner | f77e037 | 2008-01-11 06:59:07 +0000 | [diff] [blame] | 1804 | let mayStore = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1805 | def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1806 | "movdqa\t{$src, $dst|$dst, $src}", |
Evan Cheng | b4162fd | 2007-07-20 00:27:43 +0000 | [diff] [blame] | 1807 | [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>; |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 1808 | let canFoldAsLoad = 1, mayLoad = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1809 | def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1810 | "movdqu\t{$src, $dst|$dst, $src}", |
Evan Cheng | b4162fd | 2007-07-20 00:27:43 +0000 | [diff] [blame] | 1811 | [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>, |
Evan Cheng | 9ab1ac5 | 2006-04-14 23:32:40 +0000 | [diff] [blame] | 1812 | XS, Requires<[HasSSE2]>; |
Chris Lattner | f77e037 | 2008-01-11 06:59:07 +0000 | [diff] [blame] | 1813 | let mayStore = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1814 | def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1815 | "movdqu\t{$src, $dst|$dst, $src}", |
Evan Cheng | b4162fd | 2007-07-20 00:27:43 +0000 | [diff] [blame] | 1816 | [/*(store (v2i64 VR128:$src), addr:$dst)*/]>, |
Evan Cheng | 9ab1ac5 | 2006-04-14 23:32:40 +0000 | [diff] [blame] | 1817 | XS, Requires<[HasSSE2]>; |
Evan Cheng | 24dc1f5 | 2006-03-23 07:44:07 +0000 | [diff] [blame] | 1818 | |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 1819 | // Intrinsic forms of MOVDQU load and store |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 1820 | let canFoldAsLoad = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1821 | def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1822 | "movdqu\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 1823 | [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>, |
| 1824 | XS, Requires<[HasSSE2]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1825 | def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1826 | "movdqu\t{$src, $dst|$dst, $src}", |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 1827 | [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>, |
| 1828 | XS, Requires<[HasSSE2]>; |
Chris Lattner | 8139e28 | 2006-10-07 18:39:00 +0000 | [diff] [blame] | 1829 | |
Evan Cheng | e7b8a8b | 2008-03-05 08:11:27 +0000 | [diff] [blame] | 1830 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1831 | |
Chris Lattner | 45e123c | 2006-10-07 19:02:31 +0000 | [diff] [blame] | 1832 | multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId, |
| 1833 | bit Commutable = 0> { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1834 | def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1835 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
Chris Lattner | 8139e28 | 2006-10-07 18:39:00 +0000 | [diff] [blame] | 1836 | [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> { |
| 1837 | let isCommutable = Commutable; |
| 1838 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1839 | def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1840 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
Chris Lattner | 8139e28 | 2006-10-07 18:39:00 +0000 | [diff] [blame] | 1841 | [(set VR128:$dst, (IntId VR128:$src1, |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 1842 | (bitconvert (memopv2i64 addr:$src2))))]>; |
Chris Lattner | 8139e28 | 2006-10-07 18:39:00 +0000 | [diff] [blame] | 1843 | } |
Chris Lattner | 8139e28 | 2006-10-07 18:39:00 +0000 | [diff] [blame] | 1844 | |
Evan Cheng | 22b942a | 2008-05-03 00:52:09 +0000 | [diff] [blame] | 1845 | multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, |
| 1846 | string OpcodeStr, |
| 1847 | Intrinsic IntId, Intrinsic IntId2> { |
| 1848 | def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
| 1849 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 1850 | [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>; |
| 1851 | def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), |
| 1852 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 1853 | [(set VR128:$dst, (IntId VR128:$src1, |
| 1854 | (bitconvert (memopv2i64 addr:$src2))))]>; |
| 1855 | def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2), |
| 1856 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 1857 | [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>; |
| 1858 | } |
| 1859 | |
Chris Lattner | 7c47f9a | 2006-10-07 19:14:49 +0000 | [diff] [blame] | 1860 | /// PDI_binop_rm - Simple SSE2 binary operator. |
| 1861 | multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, |
| 1862 | ValueType OpVT, bit Commutable = 0> { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1863 | def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1864 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
Chris Lattner | 7c47f9a | 2006-10-07 19:14:49 +0000 | [diff] [blame] | 1865 | [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> { |
| 1866 | let isCommutable = Commutable; |
| 1867 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1868 | def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1869 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
Chris Lattner | 7c47f9a | 2006-10-07 19:14:49 +0000 | [diff] [blame] | 1870 | [(set VR128:$dst, (OpVT (OpNode VR128:$src1, |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 1871 | (bitconvert (memopv2i64 addr:$src2)))))]>; |
Chris Lattner | 7c47f9a | 2006-10-07 19:14:49 +0000 | [diff] [blame] | 1872 | } |
Chris Lattner | 70f4f2e | 2006-10-07 19:34:33 +0000 | [diff] [blame] | 1873 | |
| 1874 | /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64. |
| 1875 | /// |
| 1876 | /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew |
| 1877 | /// to collapse (bitconvert VT to VT) into its operand. |
| 1878 | /// |
| 1879 | multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode, |
| 1880 | bit Commutable = 0> { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1881 | def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1882 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
Chris Lattner | 70f4f2e | 2006-10-07 19:34:33 +0000 | [diff] [blame] | 1883 | [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> { |
| 1884 | let isCommutable = Commutable; |
| 1885 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1886 | def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1887 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 1888 | [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>; |
Chris Lattner | 70f4f2e | 2006-10-07 19:34:33 +0000 | [diff] [blame] | 1889 | } |
Chris Lattner | 7c47f9a | 2006-10-07 19:14:49 +0000 | [diff] [blame] | 1890 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1891 | } // Constraints = "$src1 = $dst" |
Chris Lattner | 7c47f9a | 2006-10-07 19:14:49 +0000 | [diff] [blame] | 1892 | |
| 1893 | // 128-bit Integer Arithmetic |
| 1894 | |
| 1895 | defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>; |
| 1896 | defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>; |
| 1897 | defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>; |
Chris Lattner | 70f4f2e | 2006-10-07 19:34:33 +0000 | [diff] [blame] | 1898 | defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>; |
Evan Cheng | 49ac1bf | 2006-04-13 00:43:35 +0000 | [diff] [blame] | 1899 | |
Chris Lattner | 45e123c | 2006-10-07 19:02:31 +0000 | [diff] [blame] | 1900 | defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>; |
| 1901 | defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>; |
| 1902 | defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>; |
| 1903 | defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>; |
Evan Cheng | 49ac1bf | 2006-04-13 00:43:35 +0000 | [diff] [blame] | 1904 | |
Chris Lattner | 7c47f9a | 2006-10-07 19:14:49 +0000 | [diff] [blame] | 1905 | defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>; |
| 1906 | defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>; |
| 1907 | defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>; |
Chris Lattner | 70f4f2e | 2006-10-07 19:34:33 +0000 | [diff] [blame] | 1908 | defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>; |
Evan Cheng | 49ac1bf | 2006-04-13 00:43:35 +0000 | [diff] [blame] | 1909 | |
Chris Lattner | 45e123c | 2006-10-07 19:02:31 +0000 | [diff] [blame] | 1910 | defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>; |
| 1911 | defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>; |
| 1912 | defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>; |
| 1913 | defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>; |
Evan Cheng | 49ac1bf | 2006-04-13 00:43:35 +0000 | [diff] [blame] | 1914 | |
Chris Lattner | 7c47f9a | 2006-10-07 19:14:49 +0000 | [diff] [blame] | 1915 | defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>; |
Evan Cheng | 0058694 | 2006-04-13 06:11:45 +0000 | [diff] [blame] | 1916 | |
Chris Lattner | 45e123c | 2006-10-07 19:02:31 +0000 | [diff] [blame] | 1917 | defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>; |
| 1918 | defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>; |
| 1919 | defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>; |
Evan Cheng | 0058694 | 2006-04-13 06:11:45 +0000 | [diff] [blame] | 1920 | |
Chris Lattner | 45e123c | 2006-10-07 19:02:31 +0000 | [diff] [blame] | 1921 | defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>; |
Chris Lattner | 7733799 | 2006-10-07 07:06:17 +0000 | [diff] [blame] | 1922 | |
Chris Lattner | 45e123c | 2006-10-07 19:02:31 +0000 | [diff] [blame] | 1923 | defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>; |
| 1924 | defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>; |
Chris Lattner | 8139e28 | 2006-10-07 18:39:00 +0000 | [diff] [blame] | 1925 | |
Chris Lattner | 7733799 | 2006-10-07 07:06:17 +0000 | [diff] [blame] | 1926 | |
Chris Lattner | 45e123c | 2006-10-07 19:02:31 +0000 | [diff] [blame] | 1927 | defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>; |
| 1928 | defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>; |
| 1929 | defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>; |
| 1930 | defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>; |
| 1931 | defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>; |
Evan Cheng | c60bd97 | 2006-03-25 09:37:23 +0000 | [diff] [blame] | 1932 | |
Chris Lattner | 7733799 | 2006-10-07 07:06:17 +0000 | [diff] [blame] | 1933 | |
Evan Cheng | 22b942a | 2008-05-03 00:52:09 +0000 | [diff] [blame] | 1934 | defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", |
| 1935 | int_x86_sse2_psll_w, int_x86_sse2_pslli_w>; |
| 1936 | defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", |
| 1937 | int_x86_sse2_psll_d, int_x86_sse2_pslli_d>; |
| 1938 | defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", |
| 1939 | int_x86_sse2_psll_q, int_x86_sse2_pslli_q>; |
Chris Lattner | 7733799 | 2006-10-07 07:06:17 +0000 | [diff] [blame] | 1940 | |
Evan Cheng | 22b942a | 2008-05-03 00:52:09 +0000 | [diff] [blame] | 1941 | defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", |
| 1942 | int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>; |
| 1943 | defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", |
| 1944 | int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>; |
Nate Begeman | 32097bd | 2008-05-13 17:52:09 +0000 | [diff] [blame] | 1945 | defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", |
Evan Cheng | 22b942a | 2008-05-03 00:52:09 +0000 | [diff] [blame] | 1946 | int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>; |
Chris Lattner | 7733799 | 2006-10-07 07:06:17 +0000 | [diff] [blame] | 1947 | |
Evan Cheng | 22b942a | 2008-05-03 00:52:09 +0000 | [diff] [blame] | 1948 | defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", |
| 1949 | int_x86_sse2_psra_w, int_x86_sse2_psrai_w>; |
Nate Begeman | c9bdb00 | 2008-05-13 01:47:52 +0000 | [diff] [blame] | 1950 | defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", |
Evan Cheng | 22b942a | 2008-05-03 00:52:09 +0000 | [diff] [blame] | 1951 | int_x86_sse2_psra_d, int_x86_sse2_psrai_d>; |
Chris Lattner | 7733799 | 2006-10-07 07:06:17 +0000 | [diff] [blame] | 1952 | |
Chris Lattner | 6970eda | 2006-10-07 19:49:05 +0000 | [diff] [blame] | 1953 | // 128-bit logical shifts. |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1954 | let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1955 | def PSLLDQri : PDIi8<0x73, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1956 | (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1957 | "pslldq\t{$src2, $dst|$dst, $src2}", []>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1958 | def PSRLDQri : PDIi8<0x73, MRM3r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1959 | (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1960 | "psrldq\t{$src2, $dst|$dst, $src2}", []>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1961 | // PSRADQri doesn't exist in SSE[1-3]. |
Evan Cheng | ff65e38 | 2006-04-04 21:49:39 +0000 | [diff] [blame] | 1962 | } |
| 1963 | |
Chris Lattner | 6970eda | 2006-10-07 19:49:05 +0000 | [diff] [blame] | 1964 | let Predicates = [HasSSE2] in { |
| 1965 | def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2), |
| 1966 | (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; |
| 1967 | def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2), |
| 1968 | (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; |
Bill Wendling | 5e249b4 | 2008-10-02 05:56:52 +0000 | [diff] [blame] | 1969 | def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2), |
| 1970 | (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>; |
| 1971 | def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2), |
| 1972 | (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>; |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 1973 | def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)), |
| 1974 | (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; |
Evan Cheng | f26ffe9 | 2008-05-29 08:22:04 +0000 | [diff] [blame] | 1975 | |
| 1976 | // Shift up / down and insert zero's. |
| 1977 | def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))), |
| 1978 | (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>; |
| 1979 | def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))), |
| 1980 | (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>; |
Chris Lattner | 6970eda | 2006-10-07 19:49:05 +0000 | [diff] [blame] | 1981 | } |
| 1982 | |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 1983 | // Logical |
Chris Lattner | a7ebe55 | 2006-10-07 19:37:30 +0000 | [diff] [blame] | 1984 | defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>; |
| 1985 | defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>; |
| 1986 | defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>; |
| 1987 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 1988 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1989 | def PANDNrr : PDI<0xDF, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1990 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1991 | "pandn\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1992 | [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1), |
| 1993 | VR128:$src2)))]>; |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 1994 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1995 | def PANDNrm : PDI<0xDF, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1996 | (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1997 | "pandn\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 1998 | [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1), |
Dan Gohman | 7f55fcb | 2007-08-02 21:17:01 +0000 | [diff] [blame] | 1999 | (memopv2i64 addr:$src2))))]>; |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2000 | } |
| 2001 | |
Evan Cheng | 9ab1ac5 | 2006-04-14 23:32:40 +0000 | [diff] [blame] | 2002 | // SSE2 Integer comparison |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2003 | defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>; |
| 2004 | defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>; |
| 2005 | defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>; |
| 2006 | defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>; |
| 2007 | defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>; |
| 2008 | defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>; |
Evan Cheng | 9ab1ac5 | 2006-04-14 23:32:40 +0000 | [diff] [blame] | 2009 | |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 2010 | def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)), |
Nate Begeman | 0d1704b | 2008-05-12 23:09:43 +0000 | [diff] [blame] | 2011 | (PCMPEQBrr VR128:$src1, VR128:$src2)>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 2012 | def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))), |
Nate Begeman | 0d1704b | 2008-05-12 23:09:43 +0000 | [diff] [blame] | 2013 | (PCMPEQBrm VR128:$src1, addr:$src2)>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 2014 | def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)), |
Nate Begeman | 0d1704b | 2008-05-12 23:09:43 +0000 | [diff] [blame] | 2015 | (PCMPEQWrr VR128:$src1, VR128:$src2)>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 2016 | def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))), |
Nate Begeman | 0d1704b | 2008-05-12 23:09:43 +0000 | [diff] [blame] | 2017 | (PCMPEQWrm VR128:$src1, addr:$src2)>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 2018 | def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)), |
Nate Begeman | 0d1704b | 2008-05-12 23:09:43 +0000 | [diff] [blame] | 2019 | (PCMPEQDrr VR128:$src1, VR128:$src2)>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 2020 | def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))), |
Nate Begeman | 0d1704b | 2008-05-12 23:09:43 +0000 | [diff] [blame] | 2021 | (PCMPEQDrm VR128:$src1, addr:$src2)>; |
| 2022 | |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 2023 | def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)), |
Nate Begeman | 0d1704b | 2008-05-12 23:09:43 +0000 | [diff] [blame] | 2024 | (PCMPGTBrr VR128:$src1, VR128:$src2)>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 2025 | def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))), |
Nate Begeman | 0d1704b | 2008-05-12 23:09:43 +0000 | [diff] [blame] | 2026 | (PCMPGTBrm VR128:$src1, addr:$src2)>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 2027 | def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)), |
Nate Begeman | 0d1704b | 2008-05-12 23:09:43 +0000 | [diff] [blame] | 2028 | (PCMPGTWrr VR128:$src1, VR128:$src2)>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 2029 | def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))), |
Nate Begeman | 0d1704b | 2008-05-12 23:09:43 +0000 | [diff] [blame] | 2030 | (PCMPGTWrm VR128:$src1, addr:$src2)>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 2031 | def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)), |
Nate Begeman | 0d1704b | 2008-05-12 23:09:43 +0000 | [diff] [blame] | 2032 | (PCMPGTDrr VR128:$src1, VR128:$src2)>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 2033 | def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))), |
Nate Begeman | 0d1704b | 2008-05-12 23:09:43 +0000 | [diff] [blame] | 2034 | (PCMPGTDrm VR128:$src1, addr:$src2)>; |
| 2035 | |
| 2036 | |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2037 | // Pack instructions |
Chris Lattner | 45e123c | 2006-10-07 19:02:31 +0000 | [diff] [blame] | 2038 | defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>; |
| 2039 | defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>; |
| 2040 | defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>; |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2041 | |
| 2042 | // Shuffle and unpack instructions |
Evan Cheng | 8703be4 | 2006-04-04 19:12:30 +0000 | [diff] [blame] | 2043 | def PSHUFDri : PDIi8<0x70, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2044 | (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2045 | "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2046 | [(set VR128:$dst, (v4i32 (vector_shuffle |
| 2047 | VR128:$src1, (undef), |
| 2048 | PSHUFD_shuffle_mask:$src2)))]>; |
Evan Cheng | 8703be4 | 2006-04-04 19:12:30 +0000 | [diff] [blame] | 2049 | def PSHUFDmi : PDIi8<0x70, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2050 | (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2051 | "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2052 | [(set VR128:$dst, (v4i32 (vector_shuffle |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2053 | (bc_v4i32(memopv2i64 addr:$src1)), |
Evan Cheng | 91b740d | 2006-04-12 17:12:36 +0000 | [diff] [blame] | 2054 | (undef), |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2055 | PSHUFD_shuffle_mask:$src2)))]>; |
| 2056 | |
| 2057 | // SSE2 with ImmT == Imm8 and XS prefix. |
Evan Cheng | 8703be4 | 2006-04-04 19:12:30 +0000 | [diff] [blame] | 2058 | def PSHUFHWri : Ii8<0x70, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2059 | (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2060 | "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2061 | [(set VR128:$dst, (v8i16 (vector_shuffle |
| 2062 | VR128:$src1, (undef), |
| 2063 | PSHUFHW_shuffle_mask:$src2)))]>, |
| 2064 | XS, Requires<[HasSSE2]>; |
Evan Cheng | 8703be4 | 2006-04-04 19:12:30 +0000 | [diff] [blame] | 2065 | def PSHUFHWmi : Ii8<0x70, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2066 | (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2067 | "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2068 | [(set VR128:$dst, (v8i16 (vector_shuffle |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2069 | (bc_v8i16 (memopv2i64 addr:$src1)), |
Evan Cheng | 91b740d | 2006-04-12 17:12:36 +0000 | [diff] [blame] | 2070 | (undef), |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2071 | PSHUFHW_shuffle_mask:$src2)))]>, |
| 2072 | XS, Requires<[HasSSE2]>; |
| 2073 | |
| 2074 | // SSE2 with ImmT == Imm8 and XD prefix. |
Evan Cheng | 8703be4 | 2006-04-04 19:12:30 +0000 | [diff] [blame] | 2075 | def PSHUFLWri : Ii8<0x70, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2076 | (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2077 | "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2078 | [(set VR128:$dst, (v8i16 (vector_shuffle |
| 2079 | VR128:$src1, (undef), |
| 2080 | PSHUFLW_shuffle_mask:$src2)))]>, |
| 2081 | XD, Requires<[HasSSE2]>; |
Evan Cheng | 8703be4 | 2006-04-04 19:12:30 +0000 | [diff] [blame] | 2082 | def PSHUFLWmi : Ii8<0x70, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2083 | (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2084 | "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2085 | [(set VR128:$dst, (v8i16 (vector_shuffle |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2086 | (bc_v8i16 (memopv2i64 addr:$src1)), |
Evan Cheng | 91b740d | 2006-04-12 17:12:36 +0000 | [diff] [blame] | 2087 | (undef), |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2088 | PSHUFLW_shuffle_mask:$src2)))]>, |
| 2089 | XD, Requires<[HasSSE2]>; |
| 2090 | |
Evan Cheng | c60bd97 | 2006-03-25 09:37:23 +0000 | [diff] [blame] | 2091 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 2092 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2093 | def PUNPCKLBWrr : PDI<0x60, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2094 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2095 | "punpcklbw\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2096 | [(set VR128:$dst, |
| 2097 | (v16i8 (vector_shuffle VR128:$src1, VR128:$src2, |
| 2098 | UNPCKL_shuffle_mask)))]>; |
| 2099 | def PUNPCKLBWrm : PDI<0x60, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2100 | (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2101 | "punpcklbw\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2102 | [(set VR128:$dst, |
| 2103 | (v16i8 (vector_shuffle VR128:$src1, |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2104 | (bc_v16i8 (memopv2i64 addr:$src2)), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2105 | UNPCKL_shuffle_mask)))]>; |
| 2106 | def PUNPCKLWDrr : PDI<0x61, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2107 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2108 | "punpcklwd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2109 | [(set VR128:$dst, |
| 2110 | (v8i16 (vector_shuffle VR128:$src1, VR128:$src2, |
| 2111 | UNPCKL_shuffle_mask)))]>; |
| 2112 | def PUNPCKLWDrm : PDI<0x61, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2113 | (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2114 | "punpcklwd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2115 | [(set VR128:$dst, |
| 2116 | (v8i16 (vector_shuffle VR128:$src1, |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2117 | (bc_v8i16 (memopv2i64 addr:$src2)), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2118 | UNPCKL_shuffle_mask)))]>; |
| 2119 | def PUNPCKLDQrr : PDI<0x62, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2120 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2121 | "punpckldq\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2122 | [(set VR128:$dst, |
| 2123 | (v4i32 (vector_shuffle VR128:$src1, VR128:$src2, |
| 2124 | UNPCKL_shuffle_mask)))]>; |
| 2125 | def PUNPCKLDQrm : PDI<0x62, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2126 | (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2127 | "punpckldq\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2128 | [(set VR128:$dst, |
| 2129 | (v4i32 (vector_shuffle VR128:$src1, |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2130 | (bc_v4i32 (memopv2i64 addr:$src2)), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2131 | UNPCKL_shuffle_mask)))]>; |
| 2132 | def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2133 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2134 | "punpcklqdq\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2135 | [(set VR128:$dst, |
| 2136 | (v2i64 (vector_shuffle VR128:$src1, VR128:$src2, |
| 2137 | UNPCKL_shuffle_mask)))]>; |
| 2138 | def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2139 | (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2140 | "punpcklqdq\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2141 | [(set VR128:$dst, |
| 2142 | (v2i64 (vector_shuffle VR128:$src1, |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2143 | (memopv2i64 addr:$src2), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2144 | UNPCKL_shuffle_mask)))]>; |
| 2145 | |
| 2146 | def PUNPCKHBWrr : PDI<0x68, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2147 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2148 | "punpckhbw\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2149 | [(set VR128:$dst, |
| 2150 | (v16i8 (vector_shuffle VR128:$src1, VR128:$src2, |
| 2151 | UNPCKH_shuffle_mask)))]>; |
| 2152 | def PUNPCKHBWrm : PDI<0x68, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2153 | (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2154 | "punpckhbw\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2155 | [(set VR128:$dst, |
| 2156 | (v16i8 (vector_shuffle VR128:$src1, |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2157 | (bc_v16i8 (memopv2i64 addr:$src2)), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2158 | UNPCKH_shuffle_mask)))]>; |
| 2159 | def PUNPCKHWDrr : PDI<0x69, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2160 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2161 | "punpckhwd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2162 | [(set VR128:$dst, |
| 2163 | (v8i16 (vector_shuffle VR128:$src1, VR128:$src2, |
| 2164 | UNPCKH_shuffle_mask)))]>; |
| 2165 | def PUNPCKHWDrm : PDI<0x69, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2166 | (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2167 | "punpckhwd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2168 | [(set VR128:$dst, |
| 2169 | (v8i16 (vector_shuffle VR128:$src1, |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2170 | (bc_v8i16 (memopv2i64 addr:$src2)), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2171 | UNPCKH_shuffle_mask)))]>; |
| 2172 | def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2173 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2174 | "punpckhdq\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2175 | [(set VR128:$dst, |
| 2176 | (v4i32 (vector_shuffle VR128:$src1, VR128:$src2, |
| 2177 | UNPCKH_shuffle_mask)))]>; |
| 2178 | def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2179 | (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2180 | "punpckhdq\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2181 | [(set VR128:$dst, |
| 2182 | (v4i32 (vector_shuffle VR128:$src1, |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2183 | (bc_v4i32 (memopv2i64 addr:$src2)), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2184 | UNPCKH_shuffle_mask)))]>; |
| 2185 | def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2186 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2187 | "punpckhqdq\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2188 | [(set VR128:$dst, |
| 2189 | (v2i64 (vector_shuffle VR128:$src1, VR128:$src2, |
| 2190 | UNPCKH_shuffle_mask)))]>; |
| 2191 | def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2192 | (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2193 | "punpckhqdq\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2194 | [(set VR128:$dst, |
| 2195 | (v2i64 (vector_shuffle VR128:$src1, |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2196 | (memopv2i64 addr:$src2), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2197 | UNPCKH_shuffle_mask)))]>; |
Evan Cheng | a971f6f | 2006-03-23 01:57:24 +0000 | [diff] [blame] | 2198 | } |
Evan Cheng | 82521dd | 2006-03-21 07:09:35 +0000 | [diff] [blame] | 2199 | |
Evan Cheng | b067a1e | 2006-03-31 19:22:53 +0000 | [diff] [blame] | 2200 | // Extract / Insert |
Evan Cheng | 9ab1ac5 | 2006-04-14 23:32:40 +0000 | [diff] [blame] | 2201 | def PEXTRWri : PDIi8<0xC5, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2202 | (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2203 | "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2204 | [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1), |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 2205 | imm:$src2))]>; |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 2206 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2207 | def PINSRWrri : PDIi8<0xC4, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2208 | (outs VR128:$dst), (ins VR128:$src1, |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2209 | GR32:$src2, i32i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2210 | "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2211 | [(set VR128:$dst, |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 2212 | (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2213 | def PINSRWrmi : PDIi8<0xC4, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2214 | (outs VR128:$dst), (ins VR128:$src1, |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2215 | i16mem:$src2, i32i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2216 | "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 2217 | [(set VR128:$dst, |
| 2218 | (X86pinsrw VR128:$src1, (extloadi16 addr:$src2), |
| 2219 | imm:$src3))]>; |
Evan Cheng | b067a1e | 2006-03-31 19:22:53 +0000 | [diff] [blame] | 2220 | } |
| 2221 | |
Evan Cheng | c5fb2b1 | 2006-03-30 00:33:26 +0000 | [diff] [blame] | 2222 | // Mask creation |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2223 | def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2224 | "pmovmskb\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2225 | [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>; |
Evan Cheng | c5fb2b1 | 2006-03-30 00:33:26 +0000 | [diff] [blame] | 2226 | |
Evan Cheng | fcf5e21 | 2006-04-11 06:57:30 +0000 | [diff] [blame] | 2227 | // Conditional store |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2228 | let Uses = [EDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2229 | def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2230 | "maskmovdqu\t{$mask, $src|$src, $mask}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2231 | [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>; |
Evan Cheng | fcf5e21 | 2006-04-11 06:57:30 +0000 | [diff] [blame] | 2232 | |
Evan Cheng | 1d76864 | 2009-02-10 22:06:28 +0000 | [diff] [blame] | 2233 | let Uses = [RDI] in |
| 2234 | def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask), |
| 2235 | "maskmovdqu\t{$mask, $src|$src, $mask}", |
| 2236 | [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>; |
| 2237 | |
Evan Cheng | ecac9cb | 2006-03-25 06:03:26 +0000 | [diff] [blame] | 2238 | // Non-temporal stores |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2239 | def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2240 | "movntpd\t{$src, $dst|$dst, $src}", |
Evan Cheng | fcf5e21 | 2006-04-11 06:57:30 +0000 | [diff] [blame] | 2241 | [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2242 | def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2243 | "movntdq\t{$src, $dst|$dst, $src}", |
Evan Cheng | fcf5e21 | 2006-04-11 06:57:30 +0000 | [diff] [blame] | 2244 | [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2245 | def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2246 | "movnti\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2247 | [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>, |
Evan Cheng | fcf5e21 | 2006-04-11 06:57:30 +0000 | [diff] [blame] | 2248 | TB, Requires<[HasSSE2]>; |
Evan Cheng | ecac9cb | 2006-03-25 06:03:26 +0000 | [diff] [blame] | 2249 | |
Evan Cheng | f3e1b1d | 2006-04-14 07:43:12 +0000 | [diff] [blame] | 2250 | // Flush cache |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2251 | def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2252 | "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>, |
Evan Cheng | f3e1b1d | 2006-04-14 07:43:12 +0000 | [diff] [blame] | 2253 | TB, Requires<[HasSSE2]>; |
| 2254 | |
| 2255 | // Load, store, and memory fence |
Evan Cheng | 4b299d4 | 2008-10-17 17:14:20 +0000 | [diff] [blame] | 2256 | def LFENCE : I<0xAE, MRM5r, (outs), (ins), |
Evan Cheng | f3e1b1d | 2006-04-14 07:43:12 +0000 | [diff] [blame] | 2257 | "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>; |
Evan Cheng | 4b299d4 | 2008-10-17 17:14:20 +0000 | [diff] [blame] | 2258 | def MFENCE : I<0xAE, MRM6r, (outs), (ins), |
Evan Cheng | f3e1b1d | 2006-04-14 07:43:12 +0000 | [diff] [blame] | 2259 | "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>; |
Evan Cheng | ecac9cb | 2006-03-25 06:03:26 +0000 | [diff] [blame] | 2260 | |
Andrew Lenharth | 22c5c1b | 2008-02-16 01:24:58 +0000 | [diff] [blame] | 2261 | //TODO: custom lower this so as to never even generate the noop |
| 2262 | def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss), |
| 2263 | (i8 0)), (NOOP)>; |
| 2264 | def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; |
| 2265 | def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; |
| 2266 | def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss), |
| 2267 | (i8 1)), (MFENCE)>; |
| 2268 | |
Evan Cheng | ffea91e | 2006-03-26 09:53:12 +0000 | [diff] [blame] | 2269 | // Alias instructions that map zero vector to pxor / xorp* for sse. |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 2270 | // We set canFoldAsLoad because this can be converted to a constant-pool |
Dan Gohman | 62c939d | 2008-12-03 05:21:24 +0000 | [diff] [blame] | 2271 | // load of an all-ones value if folding it would be beneficial. |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 2272 | let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2273 | def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2274 | "pcmpeqd\t$dst, $dst", |
Chris Lattner | 8a59448 | 2007-11-25 00:24:49 +0000 | [diff] [blame] | 2275 | [(set VR128:$dst, (v4i32 immAllOnesV))]>; |
Evan Cheng | 386031a | 2006-03-24 07:29:27 +0000 | [diff] [blame] | 2276 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2277 | // FR64 to 128-bit vector conversion. |
Evan Cheng | b3379fb | 2009-02-05 08:42:55 +0000 | [diff] [blame] | 2278 | let isAsCheapAsAMove = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2279 | def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2280 | "movsd\t{$src, $dst|$dst, $src}", |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 2281 | [(set VR128:$dst, |
| 2282 | (v2f64 (scalar_to_vector FR64:$src)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2283 | def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2284 | "movsd\t{$src, $dst|$dst, $src}", |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 2285 | [(set VR128:$dst, |
| 2286 | (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>; |
| 2287 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2288 | def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2289 | "movd\t{$src, $dst|$dst, $src}", |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 2290 | [(set VR128:$dst, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2291 | (v4i32 (scalar_to_vector GR32:$src)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2292 | def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2293 | "movd\t{$src, $dst|$dst, $src}", |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 2294 | [(set VR128:$dst, |
| 2295 | (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>; |
Evan Cheng | ebf01d6 | 2006-11-16 23:33:25 +0000 | [diff] [blame] | 2296 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2297 | def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2298 | "movd\t{$src, $dst|$dst, $src}", |
Chris Lattner | f3597a1 | 2006-12-05 18:45:06 +0000 | [diff] [blame] | 2299 | [(set FR32:$dst, (bitconvert GR32:$src))]>; |
| 2300 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2301 | def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2302 | "movd\t{$src, $dst|$dst, $src}", |
Evan Cheng | c9f0923 | 2006-12-14 19:43:11 +0000 | [diff] [blame] | 2303 | [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>; |
Chris Lattner | f3597a1 | 2006-12-05 18:45:06 +0000 | [diff] [blame] | 2304 | |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 2305 | // SSE2 instructions with XS prefix |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2306 | def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2307 | "movq\t{$src, $dst|$dst, $src}", |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 2308 | [(set VR128:$dst, |
| 2309 | (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS, |
| 2310 | Requires<[HasSSE2]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2311 | def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2312 | "movq\t{$src, $dst|$dst, $src}", |
Evan Cheng | ebf01d6 | 2006-11-16 23:33:25 +0000 | [diff] [blame] | 2313 | [(store (i64 (vector_extract (v2i64 VR128:$src), |
| 2314 | (iPTR 0))), addr:$dst)]>; |
| 2315 | |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 2316 | // FIXME: may not be able to eliminate this movss with coalescing the src and |
| 2317 | // dest register classes are different. We really want to write this pattern |
| 2318 | // like this: |
Evan Cheng | 015188f | 2006-06-15 08:14:54 +0000 | [diff] [blame] | 2319 | // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 2320 | // (f32 FR32:$src)>; |
Evan Cheng | b3379fb | 2009-02-05 08:42:55 +0000 | [diff] [blame] | 2321 | let isAsCheapAsAMove = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2322 | def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2323 | "movsd\t{$src, $dst|$dst, $src}", |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 2324 | [(set FR64:$dst, (vector_extract (v2f64 VR128:$src), |
Evan Cheng | 015188f | 2006-06-15 08:14:54 +0000 | [diff] [blame] | 2325 | (iPTR 0)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2326 | def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2327 | "movsd\t{$src, $dst|$dst, $src}", |
Evan Cheng | fb2a3b2 | 2006-04-18 21:29:08 +0000 | [diff] [blame] | 2328 | [(store (f64 (vector_extract (v2f64 VR128:$src), |
Evan Cheng | 015188f | 2006-06-15 08:14:54 +0000 | [diff] [blame] | 2329 | (iPTR 0))), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2330 | def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2331 | "movd\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2332 | [(set GR32:$dst, (vector_extract (v4i32 VR128:$src), |
Evan Cheng | 015188f | 2006-06-15 08:14:54 +0000 | [diff] [blame] | 2333 | (iPTR 0)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2334 | def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2335 | "movd\t{$src, $dst|$dst, $src}", |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 2336 | [(store (i32 (vector_extract (v4i32 VR128:$src), |
Evan Cheng | 015188f | 2006-06-15 08:14:54 +0000 | [diff] [blame] | 2337 | (iPTR 0))), addr:$dst)]>; |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 2338 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2339 | def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2340 | "movd\t{$src, $dst|$dst, $src}", |
Evan Cheng | c9f0923 | 2006-12-14 19:43:11 +0000 | [diff] [blame] | 2341 | [(set GR32:$dst, (bitconvert FR32:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2342 | def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2343 | "movd\t{$src, $dst|$dst, $src}", |
Evan Cheng | c9f0923 | 2006-12-14 19:43:11 +0000 | [diff] [blame] | 2344 | [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>; |
Chris Lattner | f3597a1 | 2006-12-05 18:45:06 +0000 | [diff] [blame] | 2345 | |
| 2346 | |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 2347 | // Move to lower bits of a VR128, leaving upper bits alone. |
Evan Cheng | bc4832b | 2006-03-24 23:15:12 +0000 | [diff] [blame] | 2348 | // Three operand (but two address) aliases. |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 2349 | let Constraints = "$src1 = $dst" in { |
Chris Lattner | f77e037 | 2008-01-11 06:59:07 +0000 | [diff] [blame] | 2350 | let neverHasSideEffects = 1 in |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2351 | def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2352 | (outs VR128:$dst), (ins VR128:$src1, FR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2353 | "movsd\t{$src2, $dst|$dst, $src2}", []>; |
Evan Cheng | d6d1cbd | 2006-04-11 00:19:04 +0000 | [diff] [blame] | 2354 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2355 | let AddedComplexity = 15 in |
| 2356 | def MOVLPDrr : SDI<0x10, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2357 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2358 | "movsd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2359 | [(set VR128:$dst, |
| 2360 | (v2f64 (vector_shuffle VR128:$src1, VR128:$src2, |
| 2361 | MOVL_shuffle_mask)))]>; |
Evan Cheng | fd111b5 | 2006-04-19 21:15:24 +0000 | [diff] [blame] | 2362 | } |
Evan Cheng | 82521dd | 2006-03-21 07:09:35 +0000 | [diff] [blame] | 2363 | |
Evan Cheng | 397edef | 2006-04-11 22:28:25 +0000 | [diff] [blame] | 2364 | // Store / copy lower 64-bits of a XMM register. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2365 | def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2366 | "movq\t{$src, $dst|$dst, $src}", |
Evan Cheng | 397edef | 2006-04-11 22:28:25 +0000 | [diff] [blame] | 2367 | [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>; |
| 2368 | |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 2369 | // Move to lower bits of a VR128 and zeroing upper bits. |
Evan Cheng | bc4832b | 2006-03-24 23:15:12 +0000 | [diff] [blame] | 2370 | // Loading from memory automatically zeroing upper bits. |
Evan Cheng | b70ea0b | 2008-05-10 00:59:18 +0000 | [diff] [blame] | 2371 | let AddedComplexity = 20 in { |
| 2372 | def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), |
| 2373 | "movsd\t{$src, $dst|$dst, $src}", |
| 2374 | [(set VR128:$dst, |
| 2375 | (v2f64 (X86vzmovl (v2f64 (scalar_to_vector |
| 2376 | (loadf64 addr:$src))))))]>; |
Evan Cheng | 7e2ff77 | 2008-05-08 00:57:18 +0000 | [diff] [blame] | 2377 | |
Evan Cheng | 8e8de68 | 2008-05-20 18:24:47 +0000 | [diff] [blame] | 2378 | def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))), |
| 2379 | (MOVZSD2PDrm addr:$src)>; |
| 2380 | def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))), |
Evan Cheng | b70ea0b | 2008-05-10 00:59:18 +0000 | [diff] [blame] | 2381 | (MOVZSD2PDrm addr:$src)>; |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 2382 | def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>; |
Evan Cheng | b70ea0b | 2008-05-10 00:59:18 +0000 | [diff] [blame] | 2383 | } |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2384 | |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 2385 | // movd / movq to XMM register zero-extends |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2386 | let AddedComplexity = 15 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2387 | def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2388 | "movd\t{$src, $dst|$dst, $src}", |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 2389 | [(set VR128:$dst, (v4i32 (X86vzmovl |
Evan Cheng | 7e2ff77 | 2008-05-08 00:57:18 +0000 | [diff] [blame] | 2390 | (v4i32 (scalar_to_vector GR32:$src)))))]>; |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2391 | // This is X86-64 only. |
| 2392 | def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src), |
| 2393 | "mov{d|q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 2394 | [(set VR128:$dst, (v2i64 (X86vzmovl |
Evan Cheng | 7e2ff77 | 2008-05-08 00:57:18 +0000 | [diff] [blame] | 2395 | (v2i64 (scalar_to_vector GR64:$src)))))]>; |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2396 | } |
| 2397 | |
| 2398 | let AddedComplexity = 20 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2399 | def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2400 | "movd\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2401 | [(set VR128:$dst, |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 2402 | (v4i32 (X86vzmovl (v4i32 (scalar_to_vector |
Evan Cheng | 7e2ff77 | 2008-05-08 00:57:18 +0000 | [diff] [blame] | 2403 | (loadi32 addr:$src))))))]>; |
Evan Cheng | c36c0ab | 2008-05-22 18:56:56 +0000 | [diff] [blame] | 2404 | |
| 2405 | def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))), |
| 2406 | (MOVZDI2PDIrm addr:$src)>; |
| 2407 | def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))), |
| 2408 | (MOVZDI2PDIrm addr:$src)>; |
Duncan Sands | d4b9c17 | 2008-06-13 19:07:40 +0000 | [diff] [blame] | 2409 | def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))), |
| 2410 | (MOVZDI2PDIrm addr:$src)>; |
Evan Cheng | c36c0ab | 2008-05-22 18:56:56 +0000 | [diff] [blame] | 2411 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2412 | def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2413 | "movq\t{$src, $dst|$dst, $src}", |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2414 | [(set VR128:$dst, |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 2415 | (v2i64 (X86vzmovl (v2i64 (scalar_to_vector |
Evan Cheng | 7e2ff77 | 2008-05-08 00:57:18 +0000 | [diff] [blame] | 2416 | (loadi64 addr:$src))))))]>, XS, |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2417 | Requires<[HasSSE2]>; |
Evan Cheng | 48090aa | 2006-03-21 23:01:21 +0000 | [diff] [blame] | 2418 | |
Evan Cheng | c36c0ab | 2008-05-22 18:56:56 +0000 | [diff] [blame] | 2419 | def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))), |
| 2420 | (MOVZQI2PQIrm addr:$src)>; |
| 2421 | def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))), |
| 2422 | (MOVZQI2PQIrm addr:$src)>; |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 2423 | def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>; |
Evan Cheng | b70ea0b | 2008-05-10 00:59:18 +0000 | [diff] [blame] | 2424 | } |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 2425 | |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2426 | // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in |
| 2427 | // IA32 document. movq xmm1, xmm2 does clear the high bits. |
| 2428 | let AddedComplexity = 15 in |
| 2429 | def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
| 2430 | "movq\t{$src, $dst|$dst, $src}", |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 2431 | [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>, |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2432 | XS, Requires<[HasSSE2]>; |
| 2433 | |
Evan Cheng | 8e8de68 | 2008-05-20 18:24:47 +0000 | [diff] [blame] | 2434 | let AddedComplexity = 20 in { |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2435 | def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), |
| 2436 | "movq\t{$src, $dst|$dst, $src}", |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 2437 | [(set VR128:$dst, (v2i64 (X86vzmovl |
Evan Cheng | 8e8de68 | 2008-05-20 18:24:47 +0000 | [diff] [blame] | 2438 | (loadv2i64 addr:$src))))]>, |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2439 | XS, Requires<[HasSSE2]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2440 | |
Evan Cheng | 8e8de68 | 2008-05-20 18:24:47 +0000 | [diff] [blame] | 2441 | def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))), |
| 2442 | (MOVZPQILo2PQIrm addr:$src)>; |
| 2443 | } |
| 2444 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2445 | //===----------------------------------------------------------------------===// |
| 2446 | // SSE3 Instructions |
| 2447 | //===----------------------------------------------------------------------===// |
| 2448 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2449 | // Move Instructions |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2450 | def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2451 | "movshdup\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2452 | [(set VR128:$dst, (v4f32 (vector_shuffle |
| 2453 | VR128:$src, (undef), |
| 2454 | MOVSHDUP_shuffle_mask)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2455 | def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2456 | "movshdup\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2457 | [(set VR128:$dst, (v4f32 (vector_shuffle |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2458 | (memopv4f32 addr:$src), (undef), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2459 | MOVSHDUP_shuffle_mask)))]>; |
| 2460 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2461 | def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2462 | "movsldup\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2463 | [(set VR128:$dst, (v4f32 (vector_shuffle |
| 2464 | VR128:$src, (undef), |
| 2465 | MOVSLDUP_shuffle_mask)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2466 | def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2467 | "movsldup\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2468 | [(set VR128:$dst, (v4f32 (vector_shuffle |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2469 | (memopv4f32 addr:$src), (undef), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2470 | MOVSLDUP_shuffle_mask)))]>; |
| 2471 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2472 | def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2473 | "movddup\t{$src, $dst|$dst, $src}", |
Evan Cheng | 0b457f0 | 2008-09-25 20:50:48 +0000 | [diff] [blame] | 2474 | [(set VR128:$dst, |
| 2475 | (v2f64 (vector_shuffle VR128:$src, (undef), |
| 2476 | MOVDDUP_shuffle_mask)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2477 | def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2478 | "movddup\t{$src, $dst|$dst, $src}", |
Evan Cheng | 0b457f0 | 2008-09-25 20:50:48 +0000 | [diff] [blame] | 2479 | [(set VR128:$dst, |
| 2480 | (v2f64 (vector_shuffle |
| 2481 | (scalar_to_vector (loadf64 addr:$src)), |
| 2482 | (undef), MOVDDUP_shuffle_mask)))]>; |
| 2483 | |
| 2484 | def : Pat<(vector_shuffle |
| 2485 | (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))), |
| 2486 | (undef), MOVDDUP_shuffle_mask), |
| 2487 | (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>; |
| 2488 | def : Pat<(vector_shuffle |
| 2489 | (memopv2f64 addr:$src), (undef), MOVDDUP_shuffle_mask), |
| 2490 | (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>; |
| 2491 | |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2492 | |
| 2493 | // Arithmetic |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 2494 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2495 | def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2496 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2497 | "addsubps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2498 | [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1, |
| 2499 | VR128:$src2))]>; |
| 2500 | def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2501 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2502 | "addsubps\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2503 | [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1, |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 2504 | (memop addr:$src2)))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2505 | def ADDSUBPDrr : S3I<0xD0, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2506 | (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2507 | "addsubpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2508 | [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1, |
| 2509 | VR128:$src2))]>; |
| 2510 | def ADDSUBPDrm : S3I<0xD0, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2511 | (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2512 | "addsubpd\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2513 | [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1, |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 2514 | (memop addr:$src2)))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2515 | } |
| 2516 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2517 | def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2518 | "lddqu\t{$src, $dst|$dst, $src}", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2519 | [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>; |
| 2520 | |
| 2521 | // Horizontal ops |
| 2522 | class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId> |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2523 | : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2524 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2525 | [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>; |
| 2526 | class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId> |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2527 | : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2528 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 2529 | [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2530 | class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId> |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2531 | : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2532 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2533 | [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>; |
| 2534 | class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId> |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2535 | : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2536 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 2537 | [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2538 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 2539 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2540 | def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>; |
| 2541 | def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>; |
| 2542 | def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>; |
| 2543 | def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>; |
| 2544 | def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>; |
| 2545 | def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>; |
| 2546 | def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>; |
| 2547 | def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>; |
| 2548 | } |
| 2549 | |
| 2550 | // Thread synchronization |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2551 | def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2552 | [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2553 | def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait", |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2554 | [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>; |
| 2555 | |
| 2556 | // vector_shuffle v1, <undef> <1, 1, 3, 3> |
| 2557 | let AddedComplexity = 15 in |
| 2558 | def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef), |
| 2559 | MOVSHDUP_shuffle_mask)), |
| 2560 | (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>; |
| 2561 | let AddedComplexity = 20 in |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2562 | def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2563 | MOVSHDUP_shuffle_mask)), |
| 2564 | (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>; |
| 2565 | |
| 2566 | // vector_shuffle v1, <undef> <0, 0, 2, 2> |
| 2567 | let AddedComplexity = 15 in |
| 2568 | def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef), |
| 2569 | MOVSLDUP_shuffle_mask)), |
| 2570 | (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>; |
| 2571 | let AddedComplexity = 20 in |
Dan Gohman | 4106f37 | 2007-07-18 20:23:34 +0000 | [diff] [blame] | 2572 | def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef), |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2573 | MOVSLDUP_shuffle_mask)), |
| 2574 | (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>; |
| 2575 | |
| 2576 | //===----------------------------------------------------------------------===// |
| 2577 | // SSSE3 Instructions |
| 2578 | //===----------------------------------------------------------------------===// |
| 2579 | |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2580 | /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8. |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 2581 | multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr, |
| 2582 | Intrinsic IntId64, Intrinsic IntId128> { |
| 2583 | def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), |
| 2584 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 2585 | [(set VR64:$dst, (IntId64 VR64:$src))]>; |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2586 | |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 2587 | def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), |
| 2588 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 2589 | [(set VR64:$dst, |
| 2590 | (IntId64 (bitconvert (memopv8i8 addr:$src))))]>; |
| 2591 | |
| 2592 | def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst), |
| 2593 | (ins VR128:$src), |
| 2594 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 2595 | [(set VR128:$dst, (IntId128 VR128:$src))]>, |
| 2596 | OpSize; |
| 2597 | |
| 2598 | def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst), |
| 2599 | (ins i128mem:$src), |
| 2600 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 2601 | [(set VR128:$dst, |
| 2602 | (IntId128 |
| 2603 | (bitconvert (memopv16i8 addr:$src))))]>, OpSize; |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2604 | } |
| 2605 | |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2606 | /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16. |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 2607 | multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr, |
| 2608 | Intrinsic IntId64, Intrinsic IntId128> { |
| 2609 | def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), |
| 2610 | (ins VR64:$src), |
| 2611 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 2612 | [(set VR64:$dst, (IntId64 VR64:$src))]>; |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2613 | |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 2614 | def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), |
| 2615 | (ins i64mem:$src), |
| 2616 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 2617 | [(set VR64:$dst, |
| 2618 | (IntId64 |
| 2619 | (bitconvert (memopv4i16 addr:$src))))]>; |
| 2620 | |
| 2621 | def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst), |
| 2622 | (ins VR128:$src), |
| 2623 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 2624 | [(set VR128:$dst, (IntId128 VR128:$src))]>, |
| 2625 | OpSize; |
| 2626 | |
| 2627 | def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst), |
| 2628 | (ins i128mem:$src), |
| 2629 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 2630 | [(set VR128:$dst, |
| 2631 | (IntId128 |
| 2632 | (bitconvert (memopv8i16 addr:$src))))]>, OpSize; |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2633 | } |
| 2634 | |
| 2635 | /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32. |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 2636 | multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr, |
| 2637 | Intrinsic IntId64, Intrinsic IntId128> { |
| 2638 | def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), |
| 2639 | (ins VR64:$src), |
| 2640 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 2641 | [(set VR64:$dst, (IntId64 VR64:$src))]>; |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2642 | |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 2643 | def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), |
| 2644 | (ins i64mem:$src), |
| 2645 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 2646 | [(set VR64:$dst, |
| 2647 | (IntId64 |
| 2648 | (bitconvert (memopv2i32 addr:$src))))]>; |
| 2649 | |
| 2650 | def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst), |
| 2651 | (ins VR128:$src), |
| 2652 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 2653 | [(set VR128:$dst, (IntId128 VR128:$src))]>, |
| 2654 | OpSize; |
| 2655 | |
| 2656 | def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst), |
| 2657 | (ins i128mem:$src), |
| 2658 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 2659 | [(set VR128:$dst, |
| 2660 | (IntId128 |
| 2661 | (bitconvert (memopv4i32 addr:$src))))]>, OpSize; |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2662 | } |
| 2663 | |
| 2664 | defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb", |
| 2665 | int_x86_ssse3_pabs_b, |
| 2666 | int_x86_ssse3_pabs_b_128>; |
| 2667 | defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw", |
| 2668 | int_x86_ssse3_pabs_w, |
| 2669 | int_x86_ssse3_pabs_w_128>; |
| 2670 | defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd", |
| 2671 | int_x86_ssse3_pabs_d, |
| 2672 | int_x86_ssse3_pabs_d_128>; |
| 2673 | |
| 2674 | /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8. |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 2675 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2676 | multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr, |
| 2677 | Intrinsic IntId64, Intrinsic IntId128, |
| 2678 | bit Commutable = 0> { |
| 2679 | def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), |
| 2680 | (ins VR64:$src1, VR64:$src2), |
| 2681 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 2682 | [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> { |
| 2683 | let isCommutable = Commutable; |
| 2684 | } |
| 2685 | def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), |
| 2686 | (ins VR64:$src1, i64mem:$src2), |
| 2687 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 2688 | [(set VR64:$dst, |
| 2689 | (IntId64 VR64:$src1, |
| 2690 | (bitconvert (memopv8i8 addr:$src2))))]>; |
| 2691 | |
| 2692 | def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst), |
| 2693 | (ins VR128:$src1, VR128:$src2), |
| 2694 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 2695 | [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, |
| 2696 | OpSize { |
| 2697 | let isCommutable = Commutable; |
| 2698 | } |
| 2699 | def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst), |
| 2700 | (ins VR128:$src1, i128mem:$src2), |
| 2701 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 2702 | [(set VR128:$dst, |
| 2703 | (IntId128 VR128:$src1, |
| 2704 | (bitconvert (memopv16i8 addr:$src2))))]>, OpSize; |
| 2705 | } |
| 2706 | } |
| 2707 | |
| 2708 | /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16. |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 2709 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2710 | multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr, |
| 2711 | Intrinsic IntId64, Intrinsic IntId128, |
| 2712 | bit Commutable = 0> { |
| 2713 | def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), |
| 2714 | (ins VR64:$src1, VR64:$src2), |
| 2715 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 2716 | [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> { |
| 2717 | let isCommutable = Commutable; |
| 2718 | } |
| 2719 | def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), |
| 2720 | (ins VR64:$src1, i64mem:$src2), |
| 2721 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 2722 | [(set VR64:$dst, |
| 2723 | (IntId64 VR64:$src1, |
| 2724 | (bitconvert (memopv4i16 addr:$src2))))]>; |
| 2725 | |
| 2726 | def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst), |
| 2727 | (ins VR128:$src1, VR128:$src2), |
| 2728 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 2729 | [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, |
| 2730 | OpSize { |
| 2731 | let isCommutable = Commutable; |
| 2732 | } |
| 2733 | def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst), |
| 2734 | (ins VR128:$src1, i128mem:$src2), |
| 2735 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 2736 | [(set VR128:$dst, |
| 2737 | (IntId128 VR128:$src1, |
| 2738 | (bitconvert (memopv8i16 addr:$src2))))]>, OpSize; |
| 2739 | } |
| 2740 | } |
| 2741 | |
| 2742 | /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32. |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 2743 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2744 | multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr, |
| 2745 | Intrinsic IntId64, Intrinsic IntId128, |
| 2746 | bit Commutable = 0> { |
| 2747 | def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), |
| 2748 | (ins VR64:$src1, VR64:$src2), |
| 2749 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 2750 | [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> { |
| 2751 | let isCommutable = Commutable; |
| 2752 | } |
| 2753 | def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), |
| 2754 | (ins VR64:$src1, i64mem:$src2), |
| 2755 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 2756 | [(set VR64:$dst, |
| 2757 | (IntId64 VR64:$src1, |
| 2758 | (bitconvert (memopv2i32 addr:$src2))))]>; |
| 2759 | |
| 2760 | def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst), |
| 2761 | (ins VR128:$src1, VR128:$src2), |
| 2762 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 2763 | [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, |
| 2764 | OpSize { |
| 2765 | let isCommutable = Commutable; |
| 2766 | } |
| 2767 | def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst), |
| 2768 | (ins VR128:$src1, i128mem:$src2), |
| 2769 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 2770 | [(set VR128:$dst, |
| 2771 | (IntId128 VR128:$src1, |
| 2772 | (bitconvert (memopv4i32 addr:$src2))))]>, OpSize; |
| 2773 | } |
| 2774 | } |
| 2775 | |
| 2776 | defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw", |
| 2777 | int_x86_ssse3_phadd_w, |
Evan Cheng | 4e44443 | 2008-06-16 21:16:24 +0000 | [diff] [blame] | 2778 | int_x86_ssse3_phadd_w_128>; |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2779 | defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd", |
| 2780 | int_x86_ssse3_phadd_d, |
Evan Cheng | 4e44443 | 2008-06-16 21:16:24 +0000 | [diff] [blame] | 2781 | int_x86_ssse3_phadd_d_128>; |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2782 | defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw", |
| 2783 | int_x86_ssse3_phadd_sw, |
Evan Cheng | 4e44443 | 2008-06-16 21:16:24 +0000 | [diff] [blame] | 2784 | int_x86_ssse3_phadd_sw_128>; |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2785 | defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw", |
| 2786 | int_x86_ssse3_phsub_w, |
| 2787 | int_x86_ssse3_phsub_w_128>; |
| 2788 | defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd", |
| 2789 | int_x86_ssse3_phsub_d, |
| 2790 | int_x86_ssse3_phsub_d_128>; |
| 2791 | defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw", |
| 2792 | int_x86_ssse3_phsub_sw, |
| 2793 | int_x86_ssse3_phsub_sw_128>; |
| 2794 | defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw", |
| 2795 | int_x86_ssse3_pmadd_ub_sw, |
Evan Cheng | 4e44443 | 2008-06-16 21:16:24 +0000 | [diff] [blame] | 2796 | int_x86_ssse3_pmadd_ub_sw_128>; |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2797 | defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw", |
| 2798 | int_x86_ssse3_pmul_hr_sw, |
| 2799 | int_x86_ssse3_pmul_hr_sw_128, 1>; |
| 2800 | defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb", |
| 2801 | int_x86_ssse3_pshuf_b, |
| 2802 | int_x86_ssse3_pshuf_b_128>; |
| 2803 | defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb", |
| 2804 | int_x86_ssse3_psign_b, |
| 2805 | int_x86_ssse3_psign_b_128>; |
| 2806 | defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw", |
| 2807 | int_x86_ssse3_psign_w, |
| 2808 | int_x86_ssse3_psign_w_128>; |
| 2809 | defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd", |
| 2810 | int_x86_ssse3_psign_d, |
| 2811 | int_x86_ssse3_psign_d_128>; |
| 2812 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 2813 | let Constraints = "$src1 = $dst" in { |
Bill Wendling | ae9671b | 2007-08-10 09:00:17 +0000 | [diff] [blame] | 2814 | def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), |
| 2815 | (ins VR64:$src1, VR64:$src2, i16imm:$src3), |
Dale Johannesen | 83e105c | 2007-10-11 20:58:37 +0000 | [diff] [blame] | 2816 | "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Bill Wendling | ae9671b | 2007-08-10 09:00:17 +0000 | [diff] [blame] | 2817 | [(set VR64:$dst, |
| 2818 | (int_x86_ssse3_palign_r |
| 2819 | VR64:$src1, VR64:$src2, |
| 2820 | imm:$src3))]>; |
Dan Gohman | c2ecdc5 | 2008-05-28 01:50:19 +0000 | [diff] [blame] | 2821 | def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), |
Bill Wendling | ae9671b | 2007-08-10 09:00:17 +0000 | [diff] [blame] | 2822 | (ins VR64:$src1, i64mem:$src2, i16imm:$src3), |
Dale Johannesen | 83e105c | 2007-10-11 20:58:37 +0000 | [diff] [blame] | 2823 | "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Bill Wendling | ae9671b | 2007-08-10 09:00:17 +0000 | [diff] [blame] | 2824 | [(set VR64:$dst, |
| 2825 | (int_x86_ssse3_palign_r |
| 2826 | VR64:$src1, |
| 2827 | (bitconvert (memopv2i32 addr:$src2)), |
| 2828 | imm:$src3))]>; |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2829 | |
Bill Wendling | ae9671b | 2007-08-10 09:00:17 +0000 | [diff] [blame] | 2830 | def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst), |
| 2831 | (ins VR128:$src1, VR128:$src2, i32imm:$src3), |
Dale Johannesen | 83e105c | 2007-10-11 20:58:37 +0000 | [diff] [blame] | 2832 | "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Bill Wendling | ae9671b | 2007-08-10 09:00:17 +0000 | [diff] [blame] | 2833 | [(set VR128:$dst, |
| 2834 | (int_x86_ssse3_palign_r_128 |
| 2835 | VR128:$src1, VR128:$src2, |
| 2836 | imm:$src3))]>, OpSize; |
Dan Gohman | c2ecdc5 | 2008-05-28 01:50:19 +0000 | [diff] [blame] | 2837 | def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst), |
Bill Wendling | ae9671b | 2007-08-10 09:00:17 +0000 | [diff] [blame] | 2838 | (ins VR128:$src1, i128mem:$src2, i32imm:$src3), |
Dale Johannesen | 83e105c | 2007-10-11 20:58:37 +0000 | [diff] [blame] | 2839 | "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Bill Wendling | ae9671b | 2007-08-10 09:00:17 +0000 | [diff] [blame] | 2840 | [(set VR128:$dst, |
| 2841 | (int_x86_ssse3_palign_r_128 |
| 2842 | VR128:$src1, |
| 2843 | (bitconvert (memopv4i32 addr:$src2)), |
| 2844 | imm:$src3))]>, OpSize; |
Bill Wendling | 76d708b | 2007-08-10 06:22:27 +0000 | [diff] [blame] | 2845 | } |
Bill Wendling | ddd3532 | 2007-05-02 23:11:52 +0000 | [diff] [blame] | 2846 | |
Nate Begeman | b9a47b8 | 2009-02-23 08:49:38 +0000 | [diff] [blame] | 2847 | def : Pat<(X86pshufb VR128:$src, VR128:$mask), |
| 2848 | (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>; |
| 2849 | def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))), |
| 2850 | (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>; |
| 2851 | |
Evan Cheng | 48090aa | 2006-03-21 23:01:21 +0000 | [diff] [blame] | 2852 | //===----------------------------------------------------------------------===// |
| 2853 | // Non-Instruction Patterns |
| 2854 | //===----------------------------------------------------------------------===// |
| 2855 | |
Chris Lattner | d43d00c | 2008-01-24 08:07:48 +0000 | [diff] [blame] | 2856 | // extload f32 -> f64. This matches load+fextend because we have a hack in |
| 2857 | // the isel (PreprocessForFPConvert) that can introduce loads after dag combine. |
| 2858 | // Since these loads aren't folded into the fextend, we have to match it |
| 2859 | // explicitly here. |
| 2860 | let Predicates = [HasSSE2] in |
| 2861 | def : Pat<(fextend (loadf32 addr:$src)), |
| 2862 | (CVTSS2SDrm addr:$src)>; |
| 2863 | |
Evan Cheng | 2c0dbd0 | 2006-03-24 02:58:06 +0000 | [diff] [blame] | 2864 | // bit_convert |
Chris Lattner | 4cc84ed | 2006-10-07 04:52:09 +0000 | [diff] [blame] | 2865 | let Predicates = [HasSSE2] in { |
| 2866 | def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; |
| 2867 | def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; |
| 2868 | def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>; |
| 2869 | def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>; |
| 2870 | def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>; |
| 2871 | def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>; |
| 2872 | def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>; |
| 2873 | def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>; |
| 2874 | def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>; |
| 2875 | def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>; |
| 2876 | def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>; |
| 2877 | def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>; |
| 2878 | def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>; |
| 2879 | def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>; |
| 2880 | def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>; |
| 2881 | def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>; |
| 2882 | def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>; |
| 2883 | def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>; |
| 2884 | def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>; |
| 2885 | def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>; |
| 2886 | def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>; |
| 2887 | def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>; |
| 2888 | def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>; |
| 2889 | def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>; |
| 2890 | def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>; |
| 2891 | def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>; |
| 2892 | def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>; |
| 2893 | def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>; |
| 2894 | def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>; |
| 2895 | def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; |
| 2896 | } |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 2897 | |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 2898 | // Move scalar to XMM zero-extended |
| 2899 | // movd to XMM register zero-extends |
Evan Cheng | f2ea84a | 2006-10-09 21:42:15 +0000 | [diff] [blame] | 2900 | let AddedComplexity = 15 in { |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 2901 | // Zeroing a VR128 then do a MOVS{S|D} to the lower bits. |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 2902 | def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))), |
Evan Cheng | 775ff18 | 2006-06-29 18:04:54 +0000 | [diff] [blame] | 2903 | (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>; |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 2904 | def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))), |
Anders Carlsson | ae436ce | 2008-10-07 16:14:11 +0000 | [diff] [blame] | 2905 | (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE1]>; |
Evan Cheng | 23573e5 | 2008-05-09 23:37:55 +0000 | [diff] [blame] | 2906 | def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), |
Anders Carlsson | ae436ce | 2008-10-07 16:14:11 +0000 | [diff] [blame] | 2907 | (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>; |
Evan Cheng | 331e2bd | 2008-07-10 01:08:23 +0000 | [diff] [blame] | 2908 | def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), |
Anders Carlsson | ae436ce | 2008-10-07 16:14:11 +0000 | [diff] [blame] | 2909 | (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>; |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 2910 | } |
Evan Cheng | bc4832b | 2006-03-24 23:15:12 +0000 | [diff] [blame] | 2911 | |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 2912 | // Splat v2f64 / v2i64 |
Evan Cheng | fd111b5 | 2006-04-19 21:15:24 +0000 | [diff] [blame] | 2913 | let AddedComplexity = 10 in { |
Evan Cheng | f686d9b | 2006-10-27 21:08:32 +0000 | [diff] [blame] | 2914 | def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 2915 | (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; |
Evan Cheng | f686d9b | 2006-10-27 21:08:32 +0000 | [diff] [blame] | 2916 | def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm), |
| 2917 | (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; |
| 2918 | def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 2919 | (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; |
Evan Cheng | f686d9b | 2006-10-27 21:08:32 +0000 | [diff] [blame] | 2920 | def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm), |
| 2921 | (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; |
Evan Cheng | fd111b5 | 2006-04-19 21:15:24 +0000 | [diff] [blame] | 2922 | } |
Evan Cheng | 475aecf | 2006-03-29 03:04:49 +0000 | [diff] [blame] | 2923 | |
Evan Cheng | b7a5c52 | 2006-04-18 21:55:35 +0000 | [diff] [blame] | 2924 | // Special unary SHUFPSrri case. |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2925 | def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef), |
| 2926 | SHUFP_unary_shuffle_mask:$sm)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 2927 | (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>, |
Evan Cheng | 56e7301 | 2006-04-10 21:42:19 +0000 | [diff] [blame] | 2928 | Requires<[HasSSE1]>; |
Dan Gohman | 7f55fcb | 2007-08-02 21:17:01 +0000 | [diff] [blame] | 2929 | // Special unary SHUFPDrri case. |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2930 | def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef), |
| 2931 | SHUFP_unary_shuffle_mask:$sm)), |
Dan Gohman | 7f55fcb | 2007-08-02 21:17:01 +0000 | [diff] [blame] | 2932 | (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>, |
| 2933 | Requires<[HasSSE2]>; |
Evan Cheng | 3d60df4 | 2006-04-10 22:35:16 +0000 | [diff] [blame] | 2934 | // Unary v4f32 shuffle with PSHUF* in order to fold a load. |
Evan Cheng | 0c0f83f | 2008-04-05 00:30:36 +0000 | [diff] [blame] | 2935 | def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef), |
Evan Cheng | 3d60df4 | 2006-04-10 22:35:16 +0000 | [diff] [blame] | 2936 | SHUFP_unary_shuffle_mask:$sm), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 2937 | (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>, |
Evan Cheng | 7d9061e | 2006-03-30 19:54:57 +0000 | [diff] [blame] | 2938 | Requires<[HasSSE2]>; |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 2939 | |
Evan Cheng | 3d60df4 | 2006-04-10 22:35:16 +0000 | [diff] [blame] | 2940 | // Special binary v4i32 shuffle cases with SHUFPS. |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2941 | def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2), |
| 2942 | PSHUFD_binary_shuffle_mask:$sm)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 2943 | (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>, |
| 2944 | Requires<[HasSSE2]>; |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2945 | def : Pat<(v4i32 (vector_shuffle VR128:$src1, |
| 2946 | (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 2947 | (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>, |
| 2948 | Requires<[HasSSE2]>; |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2949 | // Special binary v2i64 shuffle cases using SHUFPDrri. |
| 2950 | def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2, |
| 2951 | SHUFP_shuffle_mask:$sm)), |
| 2952 | (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>, |
| 2953 | Requires<[HasSSE2]>; |
| 2954 | // Special unary SHUFPDrri case. |
| 2955 | def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef), |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 2956 | SHUFP_unary_shuffle_mask:$sm)), |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 2957 | (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>, |
| 2958 | Requires<[HasSSE2]>; |
Evan Cheng | 1b32f22 | 2006-03-30 07:33:32 +0000 | [diff] [blame] | 2959 | |
Evan Cheng | 1d5a8cc | 2006-04-05 07:20:06 +0000 | [diff] [blame] | 2960 | // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...> |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 2961 | let AddedComplexity = 15 in { |
| 2962 | def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef), |
| 2963 | UNPCKL_v_undef_shuffle_mask:$sm)), |
| 2964 | (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>, |
| 2965 | Requires<[OptForSpeed, HasSSE2]>; |
| 2966 | def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), |
| 2967 | UNPCKL_v_undef_shuffle_mask:$sm)), |
| 2968 | (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>, |
| 2969 | Requires<[OptForSpeed, HasSSE2]>; |
| 2970 | } |
Evan Cheng | fd111b5 | 2006-04-19 21:15:24 +0000 | [diff] [blame] | 2971 | let AddedComplexity = 10 in { |
Evan Cheng | 1d5a8cc | 2006-04-05 07:20:06 +0000 | [diff] [blame] | 2972 | def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), |
| 2973 | UNPCKL_v_undef_shuffle_mask)), |
Evan Cheng | c739489 | 2008-09-26 21:26:30 +0000 | [diff] [blame] | 2974 | (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>; |
Evan Cheng | 1d5a8cc | 2006-04-05 07:20:06 +0000 | [diff] [blame] | 2975 | def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef), |
| 2976 | UNPCKL_v_undef_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 2977 | (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; |
Evan Cheng | 1d5a8cc | 2006-04-05 07:20:06 +0000 | [diff] [blame] | 2978 | def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef), |
| 2979 | UNPCKL_v_undef_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 2980 | (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; |
Evan Cheng | 1d5a8cc | 2006-04-05 07:20:06 +0000 | [diff] [blame] | 2981 | def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef), |
| 2982 | UNPCKL_v_undef_shuffle_mask)), |
Evan Cheng | c739489 | 2008-09-26 21:26:30 +0000 | [diff] [blame] | 2983 | (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; |
Evan Cheng | fd111b5 | 2006-04-19 21:15:24 +0000 | [diff] [blame] | 2984 | } |
Evan Cheng | 1d5a8cc | 2006-04-05 07:20:06 +0000 | [diff] [blame] | 2985 | |
Evan Cheng | 174f803 | 2007-05-17 18:44:37 +0000 | [diff] [blame] | 2986 | // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...> |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 2987 | let AddedComplexity = 15 in { |
| 2988 | def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef), |
| 2989 | UNPCKH_v_undef_shuffle_mask:$sm)), |
| 2990 | (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>, |
| 2991 | Requires<[OptForSpeed, HasSSE2]>; |
| 2992 | def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), |
| 2993 | UNPCKH_v_undef_shuffle_mask:$sm)), |
| 2994 | (PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>, |
| 2995 | Requires<[OptForSpeed, HasSSE2]>; |
| 2996 | } |
Evan Cheng | 174f803 | 2007-05-17 18:44:37 +0000 | [diff] [blame] | 2997 | let AddedComplexity = 10 in { |
| 2998 | def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), |
| 2999 | UNPCKH_v_undef_shuffle_mask)), |
Evan Cheng | c739489 | 2008-09-26 21:26:30 +0000 | [diff] [blame] | 3000 | (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>; |
Evan Cheng | 174f803 | 2007-05-17 18:44:37 +0000 | [diff] [blame] | 3001 | def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef), |
| 3002 | UNPCKH_v_undef_shuffle_mask)), |
| 3003 | (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; |
| 3004 | def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef), |
| 3005 | UNPCKH_v_undef_shuffle_mask)), |
| 3006 | (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; |
| 3007 | def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef), |
| 3008 | UNPCKH_v_undef_shuffle_mask)), |
Evan Cheng | c739489 | 2008-09-26 21:26:30 +0000 | [diff] [blame] | 3009 | (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; |
Evan Cheng | 174f803 | 2007-05-17 18:44:37 +0000 | [diff] [blame] | 3010 | } |
| 3011 | |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 3012 | let AddedComplexity = 20 in { |
Evan Cheng | 2dadaea | 2006-04-19 20:37:34 +0000 | [diff] [blame] | 3013 | // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS |
| 3014 | def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2, |
| 3015 | MOVHP_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3016 | (MOVLHPSrr VR128:$src1, VR128:$src2)>; |
Evan Cheng | 2dadaea | 2006-04-19 20:37:34 +0000 | [diff] [blame] | 3017 | |
| 3018 | // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS |
| 3019 | def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2, |
| 3020 | MOVHLPS_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3021 | (MOVHLPSrr VR128:$src1, VR128:$src2)>; |
Evan Cheng | 2dadaea | 2006-04-19 20:37:34 +0000 | [diff] [blame] | 3022 | |
Evan Cheng | 6e56e2c | 2006-11-07 22:14:24 +0000 | [diff] [blame] | 3023 | // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS |
Evan Cheng | 9d09b89 | 2006-05-31 00:51:37 +0000 | [diff] [blame] | 3024 | def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef), |
Evan Cheng | 6e56e2c | 2006-11-07 22:14:24 +0000 | [diff] [blame] | 3025 | MOVHLPS_v_undef_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3026 | (MOVHLPSrr VR128:$src1, VR128:$src1)>; |
Evan Cheng | 9d09b89 | 2006-05-31 00:51:37 +0000 | [diff] [blame] | 3027 | def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef), |
Evan Cheng | 6e56e2c | 2006-11-07 22:14:24 +0000 | [diff] [blame] | 3028 | MOVHLPS_v_undef_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3029 | (MOVHLPSrr VR128:$src1, VR128:$src1)>; |
Evan Cheng | f2ea84a | 2006-10-09 21:42:15 +0000 | [diff] [blame] | 3030 | } |
Evan Cheng | 9d09b89 | 2006-05-31 00:51:37 +0000 | [diff] [blame] | 3031 | |
Evan Cheng | 6e56e2c | 2006-11-07 22:14:24 +0000 | [diff] [blame] | 3032 | let AddedComplexity = 20 in { |
Evan Cheng | 2dadaea | 2006-04-19 20:37:34 +0000 | [diff] [blame] | 3033 | // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS |
| 3034 | // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3035 | def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2), |
Evan Cheng | f66a094 | 2006-04-19 18:20:17 +0000 | [diff] [blame] | 3036 | MOVLP_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3037 | (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>; |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3038 | def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2), |
Evan Cheng | f66a094 | 2006-04-19 18:20:17 +0000 | [diff] [blame] | 3039 | MOVLP_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3040 | (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3041 | def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2), |
Evan Cheng | f66a094 | 2006-04-19 18:20:17 +0000 | [diff] [blame] | 3042 | MOVHP_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3043 | (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>; |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3044 | def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2), |
Evan Cheng | f66a094 | 2006-04-19 18:20:17 +0000 | [diff] [blame] | 3045 | MOVHP_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3046 | (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | f66a094 | 2006-04-19 18:20:17 +0000 | [diff] [blame] | 3047 | |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3048 | def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2), |
Evan Cheng | f66a094 | 2006-04-19 18:20:17 +0000 | [diff] [blame] | 3049 | MOVLP_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3050 | (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3051 | def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2), |
Evan Cheng | 64e9769 | 2006-04-24 21:58:20 +0000 | [diff] [blame] | 3052 | MOVLP_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3053 | (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3054 | def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2), |
Evan Cheng | 64e9769 | 2006-04-24 21:58:20 +0000 | [diff] [blame] | 3055 | MOVHP_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3056 | (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>; |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3057 | def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2), |
Evan Cheng | 50f778d | 2008-05-23 18:00:18 +0000 | [diff] [blame] | 3058 | MOVHP_shuffle_mask)), |
| 3059 | (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | f2ea84a | 2006-10-09 21:42:15 +0000 | [diff] [blame] | 3060 | } |
Evan Cheng | 64e9769 | 2006-04-24 21:58:20 +0000 | [diff] [blame] | 3061 | |
Evan Cheng | cd0baf2 | 2008-05-23 21:23:16 +0000 | [diff] [blame] | 3062 | // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS |
| 3063 | // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3064 | def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2, |
Evan Cheng | cd0baf2 | 2008-05-23 21:23:16 +0000 | [diff] [blame] | 3065 | MOVLP_shuffle_mask)), addr:$src1), |
| 3066 | (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>; |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3067 | def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2, |
Evan Cheng | cd0baf2 | 2008-05-23 21:23:16 +0000 | [diff] [blame] | 3068 | MOVLP_shuffle_mask)), addr:$src1), |
| 3069 | (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3070 | def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2, |
Evan Cheng | cd0baf2 | 2008-05-23 21:23:16 +0000 | [diff] [blame] | 3071 | MOVHP_shuffle_mask)), addr:$src1), |
| 3072 | (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>; |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3073 | def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2, |
Evan Cheng | cd0baf2 | 2008-05-23 21:23:16 +0000 | [diff] [blame] | 3074 | MOVHP_shuffle_mask)), addr:$src1), |
| 3075 | (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>; |
| 3076 | |
| 3077 | def : Pat<(store (v4i32 (vector_shuffle |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3078 | (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2, |
Evan Cheng | cd0baf2 | 2008-05-23 21:23:16 +0000 | [diff] [blame] | 3079 | MOVLP_shuffle_mask)), addr:$src1), |
| 3080 | (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>; |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3081 | def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2, |
Evan Cheng | cd0baf2 | 2008-05-23 21:23:16 +0000 | [diff] [blame] | 3082 | MOVLP_shuffle_mask)), addr:$src1), |
| 3083 | (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>; |
| 3084 | def : Pat<(store (v4i32 (vector_shuffle |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3085 | (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2, |
Evan Cheng | cd0baf2 | 2008-05-23 21:23:16 +0000 | [diff] [blame] | 3086 | MOVHP_shuffle_mask)), addr:$src1), |
| 3087 | (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>; |
Evan Cheng | 1632782 | 2009-01-28 08:35:02 +0000 | [diff] [blame] | 3088 | def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2, |
Evan Cheng | cd0baf2 | 2008-05-23 21:23:16 +0000 | [diff] [blame] | 3089 | MOVHP_shuffle_mask)), addr:$src1), |
| 3090 | (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>; |
| 3091 | |
| 3092 | |
Evan Cheng | f2ea84a | 2006-10-09 21:42:15 +0000 | [diff] [blame] | 3093 | let AddedComplexity = 15 in { |
Evan Cheng | 64e9769 | 2006-04-24 21:58:20 +0000 | [diff] [blame] | 3094 | // Setting the lowest element in the vector. |
| 3095 | def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2, |
| 3096 | MOVL_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3097 | (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | cc0e98c | 2006-04-19 18:11:52 +0000 | [diff] [blame] | 3098 | def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2, |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 3099 | MOVL_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3100 | (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | a7fc642 | 2006-04-24 23:34:56 +0000 | [diff] [blame] | 3101 | |
Evan Cheng | 9e062ed | 2006-05-03 20:32:03 +0000 | [diff] [blame] | 3102 | // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd) |
| 3103 | def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2, |
| 3104 | MOVLP_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3105 | (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | 9e062ed | 2006-05-03 20:32:03 +0000 | [diff] [blame] | 3106 | def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2, |
| 3107 | MOVLP_shuffle_mask)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3108 | (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | f2ea84a | 2006-10-09 21:42:15 +0000 | [diff] [blame] | 3109 | } |
Evan Cheng | 9e062ed | 2006-05-03 20:32:03 +0000 | [diff] [blame] | 3110 | |
Evan Cheng | a7fc642 | 2006-04-24 23:34:56 +0000 | [diff] [blame] | 3111 | // Set lowest element and zero upper elements. |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 3112 | let AddedComplexity = 15 in |
| 3113 | def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src, |
| 3114 | MOVL_shuffle_mask)), |
| 3115 | (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>; |
Evan Cheng | d880b97 | 2008-05-09 21:53:03 +0000 | [diff] [blame] | 3116 | def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))), |
Evan Cheng | fd17f42 | 2008-05-08 22:35:02 +0000 | [diff] [blame] | 3117 | (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>; |
Evan Cheng | cdfc3c8 | 2006-04-17 22:45:49 +0000 | [diff] [blame] | 3118 | |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 3119 | // Some special case pandn patterns. |
| 3120 | def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))), |
| 3121 | VR128:$src2)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3122 | (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 3123 | def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))), |
| 3124 | VR128:$src2)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3125 | (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 3126 | def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))), |
| 3127 | VR128:$src2)), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3128 | (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | 1b32f22 | 2006-03-30 07:33:32 +0000 | [diff] [blame] | 3129 | |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 3130 | def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 3131 | (memop addr:$src2))), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3132 | (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 3133 | def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 3134 | (memop addr:$src2))), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3135 | (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 3136 | def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 3137 | (memop addr:$src2))), |
Chris Lattner | 30da68a | 2006-06-20 00:25:29 +0000 | [diff] [blame] | 3138 | (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>; |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 3139 | |
Nate Begeman | b348d18 | 2007-11-17 03:58:34 +0000 | [diff] [blame] | 3140 | // vector -> vector casts |
| 3141 | def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))), |
| 3142 | (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>; |
| 3143 | def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))), |
| 3144 | (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>; |
Eli Friedman | d0c0fae | 2008-09-05 23:07:03 +0000 | [diff] [blame] | 3145 | def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))), |
| 3146 | (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>; |
| 3147 | def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))), |
| 3148 | (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>; |
Nate Begeman | b348d18 | 2007-11-17 03:58:34 +0000 | [diff] [blame] | 3149 | |
Evan Cheng | b4162fd | 2007-07-20 00:27:43 +0000 | [diff] [blame] | 3150 | // Use movaps / movups for SSE integer load / store (one byte shorter). |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 3151 | def : Pat<(alignedloadv4i32 addr:$src), |
| 3152 | (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>; |
| 3153 | def : Pat<(loadv4i32 addr:$src), |
| 3154 | (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>; |
Evan Cheng | b4162fd | 2007-07-20 00:27:43 +0000 | [diff] [blame] | 3155 | def : Pat<(alignedloadv2i64 addr:$src), |
| 3156 | (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>; |
| 3157 | def : Pat<(loadv2i64 addr:$src), |
| 3158 | (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>; |
| 3159 | |
| 3160 | def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst), |
| 3161 | (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; |
| 3162 | def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst), |
| 3163 | (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; |
| 3164 | def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst), |
| 3165 | (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; |
| 3166 | def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst), |
| 3167 | (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; |
| 3168 | def : Pat<(store (v2i64 VR128:$src), addr:$dst), |
| 3169 | (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; |
| 3170 | def : Pat<(store (v4i32 VR128:$src), addr:$dst), |
| 3171 | (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; |
| 3172 | def : Pat<(store (v8i16 VR128:$src), addr:$dst), |
| 3173 | (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; |
| 3174 | def : Pat<(store (v16i8 VR128:$src), addr:$dst), |
| 3175 | (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3176 | |
| 3177 | //===----------------------------------------------------------------------===// |
| 3178 | // SSE4.1 Instructions |
| 3179 | //===----------------------------------------------------------------------===// |
| 3180 | |
Dale Johannesen | e397acc | 2008-10-10 23:51:03 +0000 | [diff] [blame] | 3181 | multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3182 | string OpcodeStr, |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3183 | Intrinsic V4F32Int, |
Nate Begeman | 2f6f1c0 | 2008-02-04 05:34:34 +0000 | [diff] [blame] | 3184 | Intrinsic V2F64Int> { |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3185 | // Intrinsic operation, reg. |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3186 | // Vector intrinsic operation, reg |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3187 | def PSr_Int : SS4AIi8<opcps, MRMSrcReg, |
Nate Begeman | 204e84e | 2008-02-04 06:00:24 +0000 | [diff] [blame] | 3188 | (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2), |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3189 | !strconcat(OpcodeStr, |
| 3190 | "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
Nate Begeman | 2f6f1c0 | 2008-02-04 05:34:34 +0000 | [diff] [blame] | 3191 | [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>, |
| 3192 | OpSize; |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3193 | |
| 3194 | // Vector intrinsic operation, mem |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3195 | def PSm_Int : SS4AIi8<opcps, MRMSrcMem, |
Nate Begeman | 204e84e | 2008-02-04 06:00:24 +0000 | [diff] [blame] | 3196 | (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2), |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3197 | !strconcat(OpcodeStr, |
| 3198 | "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 3199 | [(set VR128:$dst, |
| 3200 | (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>, |
Nate Begeman | 2f6f1c0 | 2008-02-04 05:34:34 +0000 | [diff] [blame] | 3201 | OpSize; |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3202 | |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3203 | // Vector intrinsic operation, reg |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3204 | def PDr_Int : SS4AIi8<opcpd, MRMSrcReg, |
Nate Begeman | 204e84e | 2008-02-04 06:00:24 +0000 | [diff] [blame] | 3205 | (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2), |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3206 | !strconcat(OpcodeStr, |
| 3207 | "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
Nate Begeman | 2f6f1c0 | 2008-02-04 05:34:34 +0000 | [diff] [blame] | 3208 | [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>, |
| 3209 | OpSize; |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3210 | |
| 3211 | // Vector intrinsic operation, mem |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3212 | def PDm_Int : SS4AIi8<opcpd, MRMSrcMem, |
Nate Begeman | 204e84e | 2008-02-04 06:00:24 +0000 | [diff] [blame] | 3213 | (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2), |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3214 | !strconcat(OpcodeStr, |
| 3215 | "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 3216 | [(set VR128:$dst, |
| 3217 | (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>, |
Nate Begeman | 2f6f1c0 | 2008-02-04 05:34:34 +0000 | [diff] [blame] | 3218 | OpSize; |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3219 | } |
| 3220 | |
Dale Johannesen | e397acc | 2008-10-10 23:51:03 +0000 | [diff] [blame] | 3221 | let Constraints = "$src1 = $dst" in { |
| 3222 | multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd, |
| 3223 | string OpcodeStr, |
| 3224 | Intrinsic F32Int, |
| 3225 | Intrinsic F64Int> { |
| 3226 | // Intrinsic operation, reg. |
| 3227 | def SSr_Int : SS4AIi8<opcss, MRMSrcReg, |
| 3228 | (outs VR128:$dst), |
| 3229 | (ins VR128:$src1, VR128:$src2, i32i8imm:$src3), |
| 3230 | !strconcat(OpcodeStr, |
| 3231 | "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"), |
| 3232 | [(set VR128:$dst, |
| 3233 | (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>, |
| 3234 | OpSize; |
| 3235 | |
| 3236 | // Intrinsic operation, mem. |
| 3237 | def SSm_Int : SS4AIi8<opcss, MRMSrcMem, |
| 3238 | (outs VR128:$dst), |
| 3239 | (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3), |
| 3240 | !strconcat(OpcodeStr, |
| 3241 | "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"), |
| 3242 | [(set VR128:$dst, |
| 3243 | (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>, |
| 3244 | OpSize; |
| 3245 | |
| 3246 | // Intrinsic operation, reg. |
| 3247 | def SDr_Int : SS4AIi8<opcsd, MRMSrcReg, |
| 3248 | (outs VR128:$dst), |
| 3249 | (ins VR128:$src1, VR128:$src2, i32i8imm:$src3), |
| 3250 | !strconcat(OpcodeStr, |
| 3251 | "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"), |
| 3252 | [(set VR128:$dst, |
| 3253 | (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>, |
| 3254 | OpSize; |
| 3255 | |
| 3256 | // Intrinsic operation, mem. |
| 3257 | def SDm_Int : SS4AIi8<opcsd, MRMSrcMem, |
| 3258 | (outs VR128:$dst), |
| 3259 | (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3), |
| 3260 | !strconcat(OpcodeStr, |
| 3261 | "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"), |
| 3262 | [(set VR128:$dst, |
| 3263 | (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>, |
| 3264 | OpSize; |
| 3265 | } |
| 3266 | } |
| 3267 | |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 3268 | // FP round - roundss, roundps, roundsd, roundpd |
Dale Johannesen | e397acc | 2008-10-10 23:51:03 +0000 | [diff] [blame] | 3269 | defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", |
| 3270 | int_x86_sse41_round_ps, int_x86_sse41_round_pd>; |
| 3271 | defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round", |
| 3272 | int_x86_sse41_round_ss, int_x86_sse41_round_sd>; |
Nate Begeman | 2f6f1c0 | 2008-02-04 05:34:34 +0000 | [diff] [blame] | 3273 | |
| 3274 | // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16. |
| 3275 | multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr, |
| 3276 | Intrinsic IntId128> { |
| 3277 | def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst), |
| 3278 | (ins VR128:$src), |
| 3279 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 3280 | [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize; |
| 3281 | def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst), |
| 3282 | (ins i128mem:$src), |
| 3283 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 3284 | [(set VR128:$dst, |
| 3285 | (IntId128 |
| 3286 | (bitconvert (memopv8i16 addr:$src))))]>, OpSize; |
| 3287 | } |
| 3288 | |
| 3289 | defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw", |
| 3290 | int_x86_sse41_phminposuw>; |
| 3291 | |
| 3292 | /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 3293 | let Constraints = "$src1 = $dst" in { |
Nate Begeman | 2f6f1c0 | 2008-02-04 05:34:34 +0000 | [diff] [blame] | 3294 | multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr, |
| 3295 | Intrinsic IntId128, bit Commutable = 0> { |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3296 | def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), |
| 3297 | (ins VR128:$src1, VR128:$src2), |
| 3298 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 3299 | [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, |
| 3300 | OpSize { |
Nate Begeman | 2f6f1c0 | 2008-02-04 05:34:34 +0000 | [diff] [blame] | 3301 | let isCommutable = Commutable; |
| 3302 | } |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3303 | def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), |
| 3304 | (ins VR128:$src1, i128mem:$src2), |
| 3305 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 3306 | [(set VR128:$dst, |
| 3307 | (IntId128 VR128:$src1, |
| 3308 | (bitconvert (memopv16i8 addr:$src2))))]>, OpSize; |
Nate Begeman | 2f6f1c0 | 2008-02-04 05:34:34 +0000 | [diff] [blame] | 3309 | } |
| 3310 | } |
| 3311 | |
| 3312 | defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", |
| 3313 | int_x86_sse41_pcmpeqq, 1>; |
| 3314 | defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", |
| 3315 | int_x86_sse41_packusdw, 0>; |
| 3316 | defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", |
| 3317 | int_x86_sse41_pminsb, 1>; |
| 3318 | defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", |
| 3319 | int_x86_sse41_pminsd, 1>; |
| 3320 | defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", |
| 3321 | int_x86_sse41_pminud, 1>; |
| 3322 | defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", |
| 3323 | int_x86_sse41_pminuw, 1>; |
| 3324 | defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", |
| 3325 | int_x86_sse41_pmaxsb, 1>; |
| 3326 | defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", |
| 3327 | int_x86_sse41_pmaxsd, 1>; |
| 3328 | defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", |
| 3329 | int_x86_sse41_pmaxud, 1>; |
| 3330 | defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", |
| 3331 | int_x86_sse41_pmaxuw, 1>; |
Nate Begeman | 204e84e | 2008-02-04 06:00:24 +0000 | [diff] [blame] | 3332 | |
Mon P Wang | af9b952 | 2008-12-18 21:42:19 +0000 | [diff] [blame] | 3333 | defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>; |
| 3334 | |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 3335 | def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)), |
| 3336 | (PCMPEQQrr VR128:$src1, VR128:$src2)>; |
| 3337 | def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))), |
| 3338 | (PCMPEQQrm VR128:$src1, addr:$src2)>; |
| 3339 | |
Nate Begeman | 1426d52 | 2008-02-09 01:38:08 +0000 | [diff] [blame] | 3340 | /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 3341 | let Constraints = "$src1 = $dst" in { |
Dan Gohman | 0b924dc | 2008-05-23 17:49:40 +0000 | [diff] [blame] | 3342 | multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT, |
| 3343 | SDNode OpNode, Intrinsic IntId128, |
| 3344 | bit Commutable = 0> { |
Nate Begeman | 1426d52 | 2008-02-09 01:38:08 +0000 | [diff] [blame] | 3345 | def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), |
| 3346 | (ins VR128:$src1, VR128:$src2), |
| 3347 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
Dan Gohman | 0b924dc | 2008-05-23 17:49:40 +0000 | [diff] [blame] | 3348 | [(set VR128:$dst, (OpNode (OpVT VR128:$src1), |
| 3349 | VR128:$src2))]>, OpSize { |
Nate Begeman | 1426d52 | 2008-02-09 01:38:08 +0000 | [diff] [blame] | 3350 | let isCommutable = Commutable; |
| 3351 | } |
| 3352 | def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst), |
| 3353 | (ins VR128:$src1, VR128:$src2), |
| 3354 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 3355 | [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, |
| 3356 | OpSize { |
| 3357 | let isCommutable = Commutable; |
| 3358 | } |
| 3359 | def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), |
| 3360 | (ins VR128:$src1, i128mem:$src2), |
| 3361 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 3362 | [(set VR128:$dst, |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 3363 | (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize; |
Nate Begeman | 1426d52 | 2008-02-09 01:38:08 +0000 | [diff] [blame] | 3364 | def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst), |
| 3365 | (ins VR128:$src1, i128mem:$src2), |
| 3366 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 3367 | [(set VR128:$dst, |
Evan Cheng | b193826 | 2008-05-23 00:37:07 +0000 | [diff] [blame] | 3368 | (IntId128 VR128:$src1, (memop addr:$src2)))]>, |
Nate Begeman | 1426d52 | 2008-02-09 01:38:08 +0000 | [diff] [blame] | 3369 | OpSize; |
| 3370 | } |
| 3371 | } |
Dan Gohman | 0b924dc | 2008-05-23 17:49:40 +0000 | [diff] [blame] | 3372 | defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul, |
Nate Begeman | 1426d52 | 2008-02-09 01:38:08 +0000 | [diff] [blame] | 3373 | int_x86_sse41_pmulld, 1>; |
Nate Begeman | 1426d52 | 2008-02-09 01:38:08 +0000 | [diff] [blame] | 3374 | |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3375 | /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 3376 | let Constraints = "$src1 = $dst" in { |
Nate Begeman | 204e84e | 2008-02-04 06:00:24 +0000 | [diff] [blame] | 3377 | multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr, |
| 3378 | Intrinsic IntId128, bit Commutable = 0> { |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3379 | def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst), |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3380 | (ins VR128:$src1, VR128:$src2, i32i8imm:$src3), |
| 3381 | !strconcat(OpcodeStr, |
Nate Begeman | ab5d56c | 2008-02-10 18:47:57 +0000 | [diff] [blame] | 3382 | "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3383 | [(set VR128:$dst, |
| 3384 | (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>, |
| 3385 | OpSize { |
Nate Begeman | 204e84e | 2008-02-04 06:00:24 +0000 | [diff] [blame] | 3386 | let isCommutable = Commutable; |
| 3387 | } |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3388 | def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst), |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3389 | (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3), |
| 3390 | !strconcat(OpcodeStr, |
Nate Begeman | ab5d56c | 2008-02-10 18:47:57 +0000 | [diff] [blame] | 3391 | "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3392 | [(set VR128:$dst, |
| 3393 | (IntId128 VR128:$src1, |
| 3394 | (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>, |
| 3395 | OpSize; |
Nate Begeman | 204e84e | 2008-02-04 06:00:24 +0000 | [diff] [blame] | 3396 | } |
| 3397 | } |
| 3398 | |
| 3399 | defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", |
| 3400 | int_x86_sse41_blendps, 0>; |
| 3401 | defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", |
| 3402 | int_x86_sse41_blendpd, 0>; |
| 3403 | defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", |
| 3404 | int_x86_sse41_pblendw, 0>; |
| 3405 | defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", |
| 3406 | int_x86_sse41_dpps, 1>; |
| 3407 | defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", |
| 3408 | int_x86_sse41_dppd, 1>; |
| 3409 | defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", |
Evan Cheng | 35b9a77 | 2008-06-16 20:25:59 +0000 | [diff] [blame] | 3410 | int_x86_sse41_mpsadbw, 1>; |
Nate Begeman | 1426d52 | 2008-02-09 01:38:08 +0000 | [diff] [blame] | 3411 | |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3412 | |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3413 | /// SS41I_ternary_int - SSE 4.1 ternary operator |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 3414 | let Uses = [XMM0], Constraints = "$src1 = $dst" in { |
Nate Begeman | ab5d56c | 2008-02-10 18:47:57 +0000 | [diff] [blame] | 3415 | multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> { |
| 3416 | def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst), |
| 3417 | (ins VR128:$src1, VR128:$src2), |
| 3418 | !strconcat(OpcodeStr, |
| 3419 | "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"), |
| 3420 | [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>, |
| 3421 | OpSize; |
| 3422 | |
| 3423 | def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst), |
| 3424 | (ins VR128:$src1, i128mem:$src2), |
| 3425 | !strconcat(OpcodeStr, |
| 3426 | "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"), |
| 3427 | [(set VR128:$dst, |
| 3428 | (IntId VR128:$src1, |
| 3429 | (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize; |
| 3430 | } |
| 3431 | } |
| 3432 | |
| 3433 | defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>; |
| 3434 | defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>; |
| 3435 | defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>; |
| 3436 | |
| 3437 | |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3438 | multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> { |
| 3439 | def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
| 3440 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 3441 | [(set VR128:$dst, (IntId VR128:$src))]>, OpSize; |
| 3442 | |
| 3443 | def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), |
| 3444 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 3445 | [(set VR128:$dst, |
| 3446 | (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>, |
| 3447 | OpSize; |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3448 | } |
| 3449 | |
| 3450 | defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>; |
| 3451 | defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>; |
| 3452 | defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>; |
| 3453 | defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>; |
| 3454 | defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>; |
| 3455 | defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>; |
| 3456 | |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 3457 | // Common patterns involving scalar load. |
| 3458 | def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)), |
| 3459 | (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>; |
| 3460 | def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)), |
| 3461 | (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>; |
| 3462 | |
| 3463 | def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)), |
| 3464 | (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>; |
| 3465 | def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)), |
| 3466 | (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>; |
| 3467 | |
| 3468 | def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)), |
| 3469 | (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>; |
| 3470 | def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)), |
| 3471 | (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>; |
| 3472 | |
| 3473 | def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)), |
| 3474 | (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>; |
| 3475 | def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)), |
| 3476 | (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>; |
| 3477 | |
| 3478 | def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)), |
| 3479 | (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>; |
| 3480 | def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)), |
| 3481 | (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>; |
| 3482 | |
| 3483 | def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)), |
| 3484 | (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>; |
| 3485 | def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)), |
| 3486 | (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>; |
| 3487 | |
| 3488 | |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3489 | multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> { |
| 3490 | def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
| 3491 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 3492 | [(set VR128:$dst, (IntId VR128:$src))]>, OpSize; |
| 3493 | |
| 3494 | def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src), |
| 3495 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 3496 | [(set VR128:$dst, |
| 3497 | (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>, |
| 3498 | OpSize; |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3499 | } |
| 3500 | |
| 3501 | defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>; |
| 3502 | defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>; |
| 3503 | defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>; |
| 3504 | defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>; |
| 3505 | |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 3506 | // Common patterns involving scalar load |
| 3507 | def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)), |
Evan Cheng | 89d4a28 | 2008-09-25 00:49:51 +0000 | [diff] [blame] | 3508 | (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>; |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 3509 | def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)), |
Evan Cheng | 89d4a28 | 2008-09-25 00:49:51 +0000 | [diff] [blame] | 3510 | (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>; |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 3511 | |
| 3512 | def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)), |
Evan Cheng | 89d4a28 | 2008-09-25 00:49:51 +0000 | [diff] [blame] | 3513 | (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>; |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 3514 | def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)), |
Evan Cheng | 89d4a28 | 2008-09-25 00:49:51 +0000 | [diff] [blame] | 3515 | (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>; |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 3516 | |
| 3517 | |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3518 | multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> { |
| 3519 | def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), |
| 3520 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
| 3521 | [(set VR128:$dst, (IntId VR128:$src))]>, OpSize; |
| 3522 | |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 3523 | // Expecting a i16 load any extended to i32 value. |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3524 | def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src), |
| 3525 | !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 3526 | [(set VR128:$dst, (IntId (bitconvert |
| 3527 | (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>, |
| 3528 | OpSize; |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3529 | } |
| 3530 | |
| 3531 | defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>; |
| 3532 | defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>; |
| 3533 | |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 3534 | // Common patterns involving scalar load |
| 3535 | def : Pat<(int_x86_sse41_pmovsxbq |
| 3536 | (bitconvert (v4i32 (X86vzmovl |
| 3537 | (v4i32 (scalar_to_vector (loadi32 addr:$src))))))), |
Evan Cheng | 89d4a28 | 2008-09-25 00:49:51 +0000 | [diff] [blame] | 3538 | (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>; |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 3539 | |
| 3540 | def : Pat<(int_x86_sse41_pmovzxbq |
| 3541 | (bitconvert (v4i32 (X86vzmovl |
| 3542 | (v4i32 (scalar_to_vector (loadi32 addr:$src))))))), |
Evan Cheng | 89d4a28 | 2008-09-25 00:49:51 +0000 | [diff] [blame] | 3543 | (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>; |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 3544 | |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3545 | |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3546 | /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem |
| 3547 | multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> { |
Evan Cheng | 7aae876 | 2008-03-26 08:11:49 +0000 | [diff] [blame] | 3548 | def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst), |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3549 | (ins VR128:$src1, i32i8imm:$src2), |
| 3550 | !strconcat(OpcodeStr, |
| 3551 | "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3552 | [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>, |
| 3553 | OpSize; |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3554 | def mr : SS4AIi8<opc, MRMDestMem, (outs), |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3555 | (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2), |
| 3556 | !strconcat(OpcodeStr, |
| 3557 | "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3558 | []>, OpSize; |
| 3559 | // FIXME: |
| 3560 | // There's an AssertZext in the way of writing the store pattern |
| 3561 | // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst) |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3562 | } |
| 3563 | |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3564 | defm PEXTRB : SS41I_extract8<0x14, "pextrb">; |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3565 | |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3566 | |
| 3567 | /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination |
| 3568 | multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> { |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3569 | def mr : SS4AIi8<opc, MRMDestMem, (outs), |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3570 | (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2), |
| 3571 | !strconcat(OpcodeStr, |
| 3572 | "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
| 3573 | []>, OpSize; |
| 3574 | // FIXME: |
| 3575 | // There's an AssertZext in the way of writing the store pattern |
| 3576 | // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst) |
| 3577 | } |
| 3578 | |
| 3579 | defm PEXTRW : SS41I_extract16<0x15, "pextrw">; |
| 3580 | |
| 3581 | |
| 3582 | /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination |
| 3583 | multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> { |
Evan Cheng | 7aae876 | 2008-03-26 08:11:49 +0000 | [diff] [blame] | 3584 | def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst), |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3585 | (ins VR128:$src1, i32i8imm:$src2), |
| 3586 | !strconcat(OpcodeStr, |
| 3587 | "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
| 3588 | [(set GR32:$dst, |
| 3589 | (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize; |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3590 | def mr : SS4AIi8<opc, MRMDestMem, (outs), |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3591 | (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2), |
| 3592 | !strconcat(OpcodeStr, |
| 3593 | "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
| 3594 | [(store (extractelt (v4i32 VR128:$src1), imm:$src2), |
| 3595 | addr:$dst)]>, OpSize; |
Nate Begeman | 1426d52 | 2008-02-09 01:38:08 +0000 | [diff] [blame] | 3596 | } |
| 3597 | |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3598 | defm PEXTRD : SS41I_extract32<0x16, "pextrd">; |
Nate Begeman | 1426d52 | 2008-02-09 01:38:08 +0000 | [diff] [blame] | 3599 | |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3600 | |
Evan Cheng | 62a3f15 | 2008-03-24 21:52:23 +0000 | [diff] [blame] | 3601 | /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory |
| 3602 | /// destination |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3603 | multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> { |
Evan Cheng | 7aae876 | 2008-03-26 08:11:49 +0000 | [diff] [blame] | 3604 | def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst), |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3605 | (ins VR128:$src1, i32i8imm:$src2), |
| 3606 | !strconcat(OpcodeStr, |
| 3607 | "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
Dan Gohman | 171c11e | 2008-04-16 02:32:24 +0000 | [diff] [blame] | 3608 | [(set GR32:$dst, |
| 3609 | (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>, |
Evan Cheng | 62a3f15 | 2008-03-24 21:52:23 +0000 | [diff] [blame] | 3610 | OpSize; |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3611 | def mr : SS4AIi8<opc, MRMDestMem, (outs), |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3612 | (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2), |
| 3613 | !strconcat(OpcodeStr, |
| 3614 | "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
Evan Cheng | 62a3f15 | 2008-03-24 21:52:23 +0000 | [diff] [blame] | 3615 | [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2), |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3616 | addr:$dst)]>, OpSize; |
Nate Begeman | 1426d52 | 2008-02-09 01:38:08 +0000 | [diff] [blame] | 3617 | } |
| 3618 | |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3619 | defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">; |
Nate Begeman | fea2be5 | 2008-02-09 23:46:37 +0000 | [diff] [blame] | 3620 | |
Dan Gohman | d9ced09 | 2008-08-08 18:30:21 +0000 | [diff] [blame] | 3621 | // Also match an EXTRACTPS store when the store is done as f32 instead of i32. |
| 3622 | def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)), |
| 3623 | imm:$src2))), |
| 3624 | addr:$dst), |
| 3625 | (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>, |
| 3626 | Requires<[HasSSE41]>; |
| 3627 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 3628 | let Constraints = "$src1 = $dst" in { |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3629 | multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> { |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3630 | def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst), |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3631 | (ins VR128:$src1, GR32:$src2, i32i8imm:$src3), |
| 3632 | !strconcat(OpcodeStr, |
| 3633 | "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), |
| 3634 | [(set VR128:$dst, |
| 3635 | (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize; |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3636 | def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst), |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3637 | (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3), |
| 3638 | !strconcat(OpcodeStr, |
| 3639 | "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), |
| 3640 | [(set VR128:$dst, |
| 3641 | (X86pinsrb VR128:$src1, (extloadi8 addr:$src2), |
| 3642 | imm:$src3))]>, OpSize; |
| 3643 | } |
| 3644 | } |
| 3645 | |
| 3646 | defm PINSRB : SS41I_insert8<0x20, "pinsrb">; |
| 3647 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 3648 | let Constraints = "$src1 = $dst" in { |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3649 | multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> { |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3650 | def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst), |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3651 | (ins VR128:$src1, GR32:$src2, i32i8imm:$src3), |
| 3652 | !strconcat(OpcodeStr, |
| 3653 | "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), |
| 3654 | [(set VR128:$dst, |
| 3655 | (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>, |
| 3656 | OpSize; |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3657 | def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst), |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3658 | (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3), |
| 3659 | !strconcat(OpcodeStr, |
| 3660 | "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), |
| 3661 | [(set VR128:$dst, |
| 3662 | (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2), |
| 3663 | imm:$src3)))]>, OpSize; |
| 3664 | } |
| 3665 | } |
| 3666 | |
| 3667 | defm PINSRD : SS41I_insert32<0x22, "pinsrd">; |
| 3668 | |
Evan Cheng | e9083d6 | 2008-03-05 08:19:16 +0000 | [diff] [blame] | 3669 | let Constraints = "$src1 = $dst" in { |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3670 | multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> { |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3671 | def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst), |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3672 | (ins VR128:$src1, FR32:$src2, i32i8imm:$src3), |
| 3673 | !strconcat(OpcodeStr, |
| 3674 | "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), |
| 3675 | [(set VR128:$dst, |
| 3676 | (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize; |
Evan Cheng | 172b794 | 2008-03-14 07:39:27 +0000 | [diff] [blame] | 3677 | def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst), |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3678 | (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3), |
| 3679 | !strconcat(OpcodeStr, |
| 3680 | "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), |
| 3681 | [(set VR128:$dst, |
| 3682 | (X86insrtps VR128:$src1, (loadf32 addr:$src2), |
| 3683 | imm:$src3))]>, OpSize; |
| 3684 | } |
| 3685 | } |
| 3686 | |
Evan Cheng | 7aae876 | 2008-03-26 08:11:49 +0000 | [diff] [blame] | 3687 | defm INSERTPS : SS41I_insertf32<0x21, "insertps">; |
Nate Begeman | bc4efb8 | 2008-03-16 21:14:46 +0000 | [diff] [blame] | 3688 | |
| 3689 | let Defs = [EFLAGS] in { |
| 3690 | def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), |
| 3691 | "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize; |
| 3692 | def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2), |
| 3693 | "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize; |
| 3694 | } |
| 3695 | |
| 3696 | def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), |
| 3697 | "movntdqa\t{$src, $dst|$dst, $src}", |
| 3698 | [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 3699 | |
| 3700 | /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator |
| 3701 | let Constraints = "$src1 = $dst" in { |
| 3702 | multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr, |
| 3703 | Intrinsic IntId128, bit Commutable = 0> { |
| 3704 | def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst), |
| 3705 | (ins VR128:$src1, VR128:$src2), |
| 3706 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 3707 | [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, |
| 3708 | OpSize { |
| 3709 | let isCommutable = Commutable; |
| 3710 | } |
| 3711 | def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst), |
| 3712 | (ins VR128:$src1, i128mem:$src2), |
| 3713 | !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), |
| 3714 | [(set VR128:$dst, |
| 3715 | (IntId128 VR128:$src1, |
| 3716 | (bitconvert (memopv16i8 addr:$src2))))]>, OpSize; |
| 3717 | } |
| 3718 | } |
| 3719 | |
Nate Begeman | e99b255 | 2008-07-17 17:04:58 +0000 | [diff] [blame] | 3720 | defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>; |
Nate Begeman | 30a0de9 | 2008-07-17 16:51:19 +0000 | [diff] [blame] | 3721 | |
| 3722 | def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)), |
| 3723 | (PCMPGTQrr VR128:$src1, VR128:$src2)>; |
| 3724 | def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))), |
| 3725 | (PCMPGTQrm VR128:$src1, addr:$src2)>; |