blob: 9ff114e2b6f21a3fe991f669bb8de943dde0a3bb [file] [log] [blame]
Evan Cheng586f69a2009-11-12 07:35:05 +00001; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic | FileCheck %s
2; rdar://7387640
3
Dan Gohman572645c2010-02-12 10:34:29 +00004; This now reduces to a single induction variable.
5
6; TODO: It still gets a GPR shuffle at the end of the loop
7; This is because something in instruction selection has decided
8; that comparing the pre-incremented value with zero is better
9; than comparing the post-incremented value with -4.
Evan Cheng586f69a2009-11-12 07:35:05 +000010
11@G = external global i32 ; <i32*> [#uses=2]
12@array = external global i32* ; <i32**> [#uses=1]
13
Rafael Espindola1e819662010-06-17 15:18:27 +000014define void @t() nounwind optsize {
Evan Cheng586f69a2009-11-12 07:35:05 +000015; CHECK: t:
Jakob Stoklund Olesen2aa6b4c2011-07-08 00:24:06 +000016; CHECK: mov{{.*}}, #1000
Evan Cheng586f69a2009-11-12 07:35:05 +000017entry:
18 %.pre = load i32* @G, align 4 ; <i32> [#uses=1]
19 br label %bb
20
21bb: ; preds = %bb, %entry
Dan Gohman9f23dee2010-04-17 16:29:15 +000022; CHECK: LBB0_1:
Jakob Stoklund Olesen2aa6b4c2011-07-08 00:24:06 +000023; CHECK: cmp [[R2:r[0-9]+]], #0
24; CHECK: sub{{(.w)?}} [[REGISTER:(r[0-9]+)|(lr)]], [[R2]], #1
25; CHECK: mov [[R2]], [[REGISTER]]
Dan Gohman572645c2010-02-12 10:34:29 +000026
Evan Cheng586f69a2009-11-12 07:35:05 +000027 %0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; <i32> [#uses=1]
28 %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
29 %tmp5 = sub i32 1000, %indvar ; <i32> [#uses=1]
30 %1 = load i32** @array, align 4 ; <i32*> [#uses=1]
31 %scevgep = getelementptr i32* %1, i32 %tmp5 ; <i32*> [#uses=1]
32 %2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
33 %3 = add nsw i32 %2, %0 ; <i32> [#uses=2]
34 store i32 %3, i32* @G, align 4
35 %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
36 %exitcond = icmp eq i32 %indvar.next, 1001 ; <i1> [#uses=1]
37 br i1 %exitcond, label %return, label %bb
38
39return: ; preds = %bb
40 ret void
41}