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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 2ab804c60743b4e24a9277e2ef92330c31f64bc7 / . / lib / Target / Alpha / AlphaLLRP.cpp
blob: 0ad86f4bb6d872dd45585e07f3399190265f226b [file] [log] [blame]
Andrew Lenharth2ab804c2006-09-18 19:44:29 +0000[diff] [blame^]1//===-- AlphaLLRP.cpp - Alpha Load Load Replay Trap elimination pass. -- --===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by Andrew Lenharth and is distributed under the
6// University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Here we check for potential replay traps introduced by the spiller
11// We also align some branch targets if we can do so for free
12//===----------------------------------------------------------------------===//
13
14
15#include "Alpha.h"
16#include "llvm/CodeGen/MachineFunctionPass.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/ADT/SetOperations.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/Support/CommandLine.h"
21using namespace llvm;
22
23namespace {
24 Statistic<> nopintro("alpha-nops", "Number of nops inserted");
25 Statistic<> nopalign("alpha-nops-align",
26 "Number of nops inserted for alignment");
27
28 cl::opt<bool>
29 AlignAll("alpha-align-all", cl::Hidden,
30 cl::desc("Align all blocks"));
31
32 struct AlphaLLRPPass : public MachineFunctionPass {
33 /// Target machine description which we query for reg. names, data
34 /// layout, etc.
35 ///
36 AlphaTargetMachine &TM;
37
38 AlphaLLRPPass(AlphaTargetMachine &tm) : TM(tm) { }
39
40 virtual const char *getPassName() const {
41 return "Alpha NOP inserter";
42 }
43
44 bool runOnMachineFunction(MachineFunction &F) {
45 bool Changed = false;
46 MachineInstr* prev[3] = {0,0,0};
47 unsigned count = 0;
48 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
49 FI != FE; ++FI) {
50 MachineBasicBlock& MBB = *FI;
51 bool ub = false;
52 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
53 if (count%4 == 0)
54 prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
55 ++count;
56 MachineInstr *MI = I++;
57 switch (MI->getOpcode()) {
58 case Alpha::LDQ: case Alpha::LDL:
59 case Alpha::LDWU: case Alpha::LDBU:
60 case Alpha::LDT: case Alpha::LDS:
61
62 case Alpha::STQ: case Alpha::STL:
63 case Alpha::STW: case Alpha::STB:
64 case Alpha::STT: case Alpha::STS:
65 if (MI->getOperand(2).getReg() == Alpha::R30) {
66 if (prev[0]
67 && prev[0]->getOperand(2).getReg() ==
68 MI->getOperand(2).getReg()
69 && prev[0]->getOperand(1).getImmedValue() ==
70 MI->getOperand(1).getImmedValue()) {
71 prev[0] = prev[1];
72 prev[1] = prev[2];
73 prev[2] = 0;
74 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
75 .addReg(Alpha::R31);
76 Changed = true; nopintro += 1;
77 count += 1;
78 } else if (prev[1]
79 && prev[1]->getOperand(2).getReg() ==
80 MI->getOperand(2).getReg()
81 && prev[1]->getOperand(1).getImmedValue() ==
82 MI->getOperand(1).getImmedValue()) {
83 prev[0] = prev[2];
84 prev[1] = prev[2] = 0;
85 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
86 .addReg(Alpha::R31);
87 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
88 .addReg(Alpha::R31);
89 Changed = true; nopintro += 2;
90 count += 2;
91 } else if (prev[2]
92 && prev[2]->getOperand(2).getReg() ==
93 MI->getOperand(2).getReg()
94 && prev[2]->getOperand(1).getImmedValue() ==
95 MI->getOperand(1).getImmedValue()) {
96 prev[0] = prev[1] = prev[2] = 0;
97 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
98 .addReg(Alpha::R31);
99 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
100 .addReg(Alpha::R31);
101 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
102 .addReg(Alpha::R31);
103 Changed = true; nopintro += 3;
104 count += 3;
105 }
106 prev[0] = prev[1];
107 prev[1] = prev[2];
108 prev[2] = MI;
109 break;
110 }
111 //fall through
112 case Alpha::BR:
113 case Alpha::JMP:
114 ub = true;
115 //fall through
116 default:
117 prev[0] = prev[1];
118 prev[1] = prev[2];
119 prev[2] = 0;
120 break;
121 }
122 }
123 if (ub || AlignAll) {
124 //we can align stuff for free at this point
125 while (count % 4) {
126 BuildMI(MBB, MBB.end(), Alpha::BIS, 2, Alpha::R31)
127 .addReg(Alpha::R31).addReg(Alpha::R31);
128 ++count;
129 ++nopalign;
130 prev[0] = prev[1];
131 prev[1] = prev[2];
132 prev[2] = 0;
133 }
134 }
135 }
136 return Changed;
137 }
138 };
139} // end of anonymous namespace
140
141FunctionPass *llvm::createAlphaLLRPPass(AlphaTargetMachine &tm) {
142 return new AlphaLLRPPass(tm);
143}