| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 1 | ##===- lib/Target/PowerPC/Makefile -------------------------*- Makefile -*-===## |
| 2 | # |
| 3 | # The LLVM Compiler Infrastructure |
| 4 | # |
| 5 | # This file was developed by the LLVM research group and is distributed under |
| 6 | # the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | # |
| 8 | ##===----------------------------------------------------------------------===## |
| 9 | LEVEL = ../../.. |
| Chris Lattner | 017fdcb | 2004-07-15 02:33:38 +0000 | [diff] [blame] | 10 | LIBRARYNAME = powerpc |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 11 | include $(LEVEL)/Makefile.common |
| 12 | |
| Misha Brukman | 2f94786 | 2004-08-05 18:34:15 +0000 | [diff] [blame^] | 13 | TARGET = PowerPC |
| 14 | |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 15 | # Make sure that tblgen is run, first thing. |
| 16 | $(SourceDepend): PowerPCGenRegisterInfo.h.inc PowerPCGenRegisterNames.inc \ |
| 17 | PowerPCGenRegisterInfo.inc PowerPCGenInstrNames.inc \ |
| Misha Brukman | 039ba76 | 2004-07-16 20:31:13 +0000 | [diff] [blame] | 18 | PowerPCGenInstrInfo.inc |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 19 | |
| Misha Brukman | 2f94786 | 2004-08-05 18:34:15 +0000 | [diff] [blame^] | 20 | TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \ |
| 21 | $(SourceDir)/../Target.td |
| 22 | |
| 23 | $(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN) |
| 24 | @echo "Building $(TARGET).td register names with tblgen" |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 25 | $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@ |
| 26 | |
| Misha Brukman | 2f94786 | 2004-08-05 18:34:15 +0000 | [diff] [blame^] | 27 | $(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN) |
| 28 | @echo "Building $(TARGET).td register information header with tblgen" |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 29 | $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@ |
| 30 | |
| Misha Brukman | 2f94786 | 2004-08-05 18:34:15 +0000 | [diff] [blame^] | 31 | $(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN) |
| 32 | @echo "Building $(TARGET).td register information implementation with tblgen" |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 33 | $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@ |
| 34 | |
| Misha Brukman | 2f94786 | 2004-08-05 18:34:15 +0000 | [diff] [blame^] | 35 | $(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN) |
| 36 | @echo "Building $(TARGET).td instruction names with tblgen" |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 37 | $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@ |
| 38 | |
| Misha Brukman | 2f94786 | 2004-08-05 18:34:15 +0000 | [diff] [blame^] | 39 | $(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN) |
| 40 | @echo "Building $(TARGET).td instruction information with tblgen" |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 41 | $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@ |
| 42 | |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 43 | clean:: |
| 44 | $(VERB) rm -f *.inc |