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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 31d157ae1ac2cd9c787dc3c1d28e64c682803844 / . / lib / Target / Hexagon / HexagonIntrinsics.td
blob: b15e293fdfb4246881a6b4202256f6f380d23290 [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame^]1//===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is populated based on the following specs:
10// Hexagon V2 Architecture
11// Application-Level Specification
12// 80-V9418-8 Rev. B
13// March 4, 2008
14//===----------------------------------------------------------------------===//
15
16//
17// ALU 32 types.
18//
19
20class qi_ALU32_sisi<string opc, Intrinsic IntID>
21 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
22 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
23 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
24
25class qi_ALU32_sis10<string opc, Intrinsic IntID>
26 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
27 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
28 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
29
30class qi_ALU32_sis8<string opc, Intrinsic IntID>
31 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
32 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
33 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
34
35class qi_ALU32_siu8<string opc, Intrinsic IntID>
36 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
37 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
38 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
39
40class qi_ALU32_siu9<string opc, Intrinsic IntID>
41 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
42 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
43 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
44
45class si_ALU32_qisisi<string opc, Intrinsic IntID>
46 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
47 IntRegs:$src3),
48 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
49 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
50 IntRegs:$src3))]>;
51
52class si_ALU32_qis8si<string opc, Intrinsic IntID>
53 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2,
54 IntRegs:$src3),
55 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, $src3)")),
56 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
57 IntRegs:$src3))]>;
58
59class si_ALU32_qisis8<string opc, Intrinsic IntID>
60 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
61 s8Imm:$src3),
62 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
63 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
64 imm:$src3))]>;
65
66class si_ALU32_qis8s8<string opc, Intrinsic IntID>
67 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2, s8Imm:$src3),
68 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
69 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
70
71class si_ALU32_sisi<string opc, Intrinsic IntID>
72 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
73 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
74 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
75
76class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
77 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
78 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
79 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
80
81class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
82 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
83 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
84 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
85
86class si_ALU32_sis16<string opc, Intrinsic IntID>
87 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s16Imm:$src2),
88 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
89 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
90
91class si_ALU32_sis10<string opc, Intrinsic IntID>
92 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
93 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
94 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
95
96class si_ALU32_s10si<string opc, Intrinsic IntID>
97 : ALU32_rr<(outs IntRegs:$dst), (ins s10Imm:$src1, IntRegs:$src2),
98 !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
99 [(set IntRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
100
101class si_lo_ALU32_siu16<string opc, Intrinsic IntID>
102 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
103 !strconcat("$dst.l = ", !strconcat(opc , "#$src2")),
104 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
105
106class si_hi_ALU32_siu16<string opc, Intrinsic IntID>
107 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
108 !strconcat("$dst.h = ", !strconcat(opc , "#$src2")),
109 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
110
111class si_ALU32_s16<string opc, Intrinsic IntID>
112 : ALU32_rr<(outs IntRegs:$dst), (ins s16Imm:$src1),
113 !strconcat("$dst = ", !strconcat(opc , "#$src1")),
114 [(set IntRegs:$dst, (IntID imm:$src1))]>;
115
116class di_ALU32_s8<string opc, Intrinsic IntID>
117 : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1),
118 !strconcat("$dst = ", !strconcat(opc , "#$src1")),
119 [(set DoubleRegs:$dst, (IntID imm:$src1))]>;
120
121class di_ALU64_di<string opc, Intrinsic IntID>
122 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
123 !strconcat("$dst = ", !strconcat(opc , "$src")),
124 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
125
126class si_ALU32_si<string opc, Intrinsic IntID>
127 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
128 !strconcat("$dst = ", !strconcat(opc , "($src)")),
129 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
130
131class si_ALU32_si_tfr<string opc, Intrinsic IntID>
132 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
133 !strconcat("$dst = ", !strconcat(opc , "$src")),
134 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
135
136//
137// ALU 64 types.
138//
139
140class si_ALU64_si_sat<string opc, Intrinsic IntID>
141 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
142 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
143 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
144
145class si_ALU64_didi<string opc, Intrinsic IntID>
146 : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
147 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
148 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
149
150class di_ALU64_sidi<string opc, Intrinsic IntID>
151 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
152 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
153 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
154
155class di_ALU64_didi<string opc, Intrinsic IntID>
156 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
157 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
158 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
159 DoubleRegs:$src2))]>;
160
161class di_ALU64_qididi<string opc, Intrinsic IntID>
162 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
163 DoubleRegs:$src3),
164 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
165 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
166 DoubleRegs:$src3))]>;
167
168class di_ALU64_sisi<string opc, Intrinsic IntID>
169 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
170 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
171 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
172
173class di_ALU64_didi_sat<string opc, Intrinsic IntID>
174 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
175 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
176 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
177 DoubleRegs:$src2))]>;
178
179class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
180 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
181 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
182 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
183 DoubleRegs:$src2))]>;
184
185class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
186 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
187 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
188 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
189 DoubleRegs:$src2))]>;
190
191class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
192 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
193 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
194 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
195 DoubleRegs:$src2))]>;
196
197class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
198 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
199 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
200 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
201 DoubleRegs:$src2))]>;
202
203class qi_ALU64_didi<string opc, Intrinsic IntID>
204 : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
205 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
206 [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
207
208class si_ALU64_sisi<string opc, Intrinsic IntID>
209 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
210 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
211 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
212
213class si_ALU64_sisi_sat_lh<string opc, Intrinsic IntID>
214 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
215 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
216 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
217
218class si_ALU64_sisi_l16_sat_hh<string opc, Intrinsic IntID>
219 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
220 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
221 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
222
223class si_ALU64_sisi_l16_sat_lh<string opc, Intrinsic IntID>
224 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
225 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
226 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
227
228class si_ALU64_sisi_l16_sat_hl<string opc, Intrinsic IntID>
229 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
230 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
231 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
232
233class si_ALU64_sisi_l16_sat_ll<string opc, Intrinsic IntID>
234 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
235 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
236 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
237
238class si_ALU64_sisi_l16_hh<string opc, Intrinsic IntID>
239 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
240 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
241 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
242
243class si_ALU64_sisi_l16_hl<string opc, Intrinsic IntID>
244 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
245 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
246 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
247
248class si_ALU64_sisi_l16_lh<string opc, Intrinsic IntID>
249 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
250 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
251 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
252
253class si_ALU64_sisi_l16_ll<string opc, Intrinsic IntID>
254 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
255 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
256 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
257
258class si_ALU64_sisi_h16_sat_hh<string opc, Intrinsic IntID>
259 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
260 !strconcat("$dst = ", !strconcat(opc ,
261 "($src1.H, $src2.H):sat:<<16")),
262 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
263
264class si_ALU64_sisi_h16_sat_lh<string opc, Intrinsic IntID>
265 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
266 !strconcat("$dst = ", !strconcat(opc ,
267 "($src1.L, $src2.H):sat:<<16")),
268 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
269
270class si_ALU64_sisi_h16_sat_hl<string opc, Intrinsic IntID>
271 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
272 !strconcat("$dst = ", !strconcat(opc ,
273 "($src1.H, $src2.L):sat:<<16")),
274 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
275
276class si_ALU64_sisi_h16_sat_ll<string opc, Intrinsic IntID>
277 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
278 !strconcat("$dst = ", !strconcat(opc ,
279 "($src1.L, $src2.L):sat:<<16")),
280 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
281
282class si_ALU64_sisi_h16_hh<string opc, Intrinsic IntID>
283 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
284 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<16")),
285 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
286
287class si_ALU64_sisi_h16_hl<string opc, Intrinsic IntID>
288 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
289 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<16")),
290 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
291
292class si_ALU64_sisi_h16_lh<string opc, Intrinsic IntID>
293 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
294 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<16")),
295 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
296
297class si_ALU64_sisi_h16_ll<string opc, Intrinsic IntID>
298 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
299 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<16")),
300 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
301
302class si_ALU64_sisi_lh<string opc, Intrinsic IntID>
303 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
304 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
305 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
306
307class si_ALU64_sisi_ll<string opc, Intrinsic IntID>
308 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
309 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
310 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
311
312class si_ALU64_sisi_sat<string opc, Intrinsic IntID>
313 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
314 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
315 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
316
317//
318// SInst classes.
319//
320
321class qi_SInst_qi<string opc, Intrinsic IntID>
322 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
323 !strconcat("$dst = ", !strconcat(opc , "($src)")),
324 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
325
326class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
327 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
328 !strconcat("$dst = ", !strconcat(opc , "$src")),
329 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
330
331class qi_SInst_qiqi<string opc, Intrinsic IntID>
332 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
333 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
334 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
335
336class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
337 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
338 !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
339 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
340
341class di_SInst_di<string opc, Intrinsic IntID>
342 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
343 !strconcat("$dst = ", !strconcat(opc , "($src)")),
344 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
345
346class di_SInst_di_sat<string opc, Intrinsic IntID>
347 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
348 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
349 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
350
351class si_SInst_di<string opc, Intrinsic IntID>
352 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
353 !strconcat("$dst = ", !strconcat(opc , "($src)")),
354 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
355
356class si_SInst_di_sat<string opc, Intrinsic IntID>
357 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
358 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
359 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
360
361class di_SInst_disi<string opc, Intrinsic IntID>
362 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
363 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
364 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
365
366class di_SInst_didi<string opc, Intrinsic IntID>
367 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
368 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
369 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
370
371class di_SInst_si<string opc, Intrinsic IntID>
372 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
373 !strconcat("$dst = ", !strconcat(opc , "($src1)")),
374 [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
375
376class si_SInst_sisiu3<string opc, Intrinsic IntID>
377 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u3Imm:$src3),
378 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
379 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
380 imm:$src3))]>;
381
382class si_SInst_diu5<string opc, Intrinsic IntID>
383 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
384 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
385 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
386
387class si_SInst_disi<string opc, Intrinsic IntID>
388 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
389 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
390 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
391
392class si_SInst_sidi<string opc, Intrinsic IntID>
393 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
394 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
395 [(set IntRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
396
397class di_SInst_disisi<string opc, Intrinsic IntID>
398 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2,
399 IntRegs:$src3),
400 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
401 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2,
402 IntRegs:$src3))]>;
403
404class di_SInst_sisi<string opc, Intrinsic IntID>
405 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
406 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
407 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
408
409class qi_SInst_siu5<string opc, Intrinsic IntID>
410 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
411 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
412 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
413
414class qi_SInst_siu6<string opc, Intrinsic IntID>
415 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u6Imm:$src2),
416 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
417 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
418
419class qi_SInst_sisi<string opc, Intrinsic IntID>
420 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
421 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
422 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
423
424class si_SInst_si<string opc, Intrinsic IntID>
425 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
426 !strconcat("$dst = ", !strconcat(opc , "($src)")),
427 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
428
429class si_SInst_si_sat<string opc, Intrinsic IntID>
430 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
431 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
432 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
433
434class di_SInst_qi<string opc, Intrinsic IntID>
435 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
436 !strconcat("$dst = ", !strconcat(opc , "($src)")),
437 [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
438
439class si_SInst_qi<string opc, Intrinsic IntID>
440 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
441 !strconcat("$dst = ", !strconcat(opc , "$src")),
442 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
443
444class si_SInst_qiqi<string opc, Intrinsic IntID>
445 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
446 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
447 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
448
449class qi_SInst_si<string opc, Intrinsic IntID>
450 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
451 !strconcat("$dst = ", !strconcat(opc , "$src")),
452 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
453
454class si_SInst_sisi<string opc, Intrinsic IntID>
455 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
456 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
457 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
458
459class di_SInst_diu6<string opc, Intrinsic IntID>
460 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
461 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
462 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
463
464class si_SInst_siu5<string opc, Intrinsic IntID>
465 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
466 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
467 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
468
469class si_SInst_siu5_rnd<string opc, Intrinsic IntID>
470 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
471 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
472 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
473
474class si_SInst_siu5u5<string opc, Intrinsic IntID>
475 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2, u5Imm:$src3),
476 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
477 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
478
479class si_SInst_sisisi_acc<string opc, Intrinsic IntID>
480 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
481 IntRegs:$src2),
482 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
483 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
484 IntRegs:$src2))],
485 "$dst2 = $dst">;
486
487class si_SInst_sisisi_nac<string opc, Intrinsic IntID>
488 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
489 IntRegs:$src2),
490 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
491 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
492 IntRegs:$src2))],
493 "$dst2 = $dst">;
494
495class di_SInst_didisi_acc<string opc, Intrinsic IntID>
496 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
497 IntRegs:$src2),
498 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
499 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
500 DoubleRegs:$src1,
501 IntRegs:$src2))],
502 "$dst2 = $dst">;
503
504class di_SInst_didisi_nac<string opc, Intrinsic IntID>
505 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
506 IntRegs:$src2),
507 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
508 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
509 DoubleRegs:$src1, IntRegs:$src2))],
510 "$dst2 = $dst">;
511
512class si_SInst_sisiu5u5<string opc, Intrinsic IntID>
513 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
514 u5Imm:$src2, u5Imm:$src3),
515 !strconcat("$dst = ", !strconcat(opc ,
516 "($src1, #$src2, #$src3)")),
517 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
518 imm:$src2, imm:$src3))],
519 "$dst2 = $dst">;
520
521class si_SInst_sisidi<string opc, Intrinsic IntID>
522 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
523 DoubleRegs:$src2),
524 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
525 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
526 DoubleRegs:$src2))],
527 "$dst2 = $dst">;
528
529class di_SInst_didiu6u6<string opc, Intrinsic IntID>
530 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
531 u6Imm:$src2, u6Imm:$src3),
532 !strconcat("$dst = ", !strconcat(opc ,
533 "($src1, #$src2, #$src3)")),
534 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
535 imm:$src2, imm:$src3))],
536 "$dst2 = $dst">;
537
538class di_SInst_dididi<string opc, Intrinsic IntID>
539 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
540 DoubleRegs:$src2),
541 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
542 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
543 DoubleRegs:$src1,
544 DoubleRegs:$src2))],
545 "$dst2 = $dst">;
546
547class di_SInst_diu6u6<string opc, Intrinsic IntID>
548 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2,
549 u6Imm:$src3),
550 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
551 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2,
552 imm:$src3))]>;
553
554class di_SInst_didisi<string opc, Intrinsic IntID>
555 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
556 IntRegs:$src3),
557 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
558 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
559 IntRegs:$src3))]>;
560
561class di_SInst_didiqi<string opc, Intrinsic IntID>
562 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
563 IntRegs:$src3),
564 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
565 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
566 IntRegs:$src3))]>;
567
568class di_SInst_didiu3<string opc, Intrinsic IntID>
569 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
570 u3Imm:$src3),
571 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
572 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
573 imm:$src3))]>;
574
575class di_SInst_didisi_or<string opc, Intrinsic IntID>
576 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
577 IntRegs:$src2),
578 !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
579 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
580 IntRegs:$src2))],
581 "$dst2 = $dst">;
582
583class di_SInst_didisi_and<string opc, Intrinsic IntID>
584 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
585 IntRegs:$src2),
586 !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
587 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
588 IntRegs:$src2))],
589 "$dst2 = $dst">;
590
591class di_SInst_didiu6_and<string opc, Intrinsic IntID>
592 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
593 u6Imm:$src2),
594 !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
595 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
596 imm:$src2))],
597 "$dst2 = $dst">;
598
599class di_SInst_didiu6_or<string opc, Intrinsic IntID>
600 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
601 u6Imm:$src2),
602 !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
603 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
604 imm:$src2))],
605 "$dst2 = $dst">;
606
607class di_SInst_didiu6_xor<string opc, Intrinsic IntID>
608 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
609 u6Imm:$src2),
610 !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
611 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
612 imm:$src2))],
613 "$dst2 = $dst">;
614
615class si_SInst_sisisi_and<string opc, Intrinsic IntID>
616 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
617 IntRegs:$src2),
618 !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
619 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
620 IntRegs:$src2))],
621 "$dst2 = $dst">;
622
623class si_SInst_sisisi_or<string opc, Intrinsic IntID>
624 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
625 IntRegs:$src2),
626 !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
627 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
628 IntRegs:$src2))],
629 "$dst2 = $dst">;
630
631
632class si_SInst_sisiu5_and<string opc, Intrinsic IntID>
633 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
634 u5Imm:$src2),
635 !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
636 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
637 imm:$src2))],
638 "$dst2 = $dst">;
639
640class si_SInst_sisiu5_or<string opc, Intrinsic IntID>
641 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
642 u5Imm:$src2),
643 !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
644 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
645 imm:$src2))],
646 "$dst2 = $dst">;
647
648class si_SInst_sisiu5_xor<string opc, Intrinsic IntID>
649 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
650 u5Imm:$src2),
651 !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
652 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
653 imm:$src2))],
654 "$dst2 = $dst">;
655
656class si_SInst_sisiu5_acc<string opc, Intrinsic IntID>
657 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
658 u5Imm:$src2),
659 !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
660 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
661 imm:$src2))],
662 "$dst2 = $dst">;
663
664class si_SInst_sisiu5_nac<string opc, Intrinsic IntID>
665 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
666 u5Imm:$src2),
667 !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
668 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
669 imm:$src2))],
670 "$dst2 = $dst">;
671
672class di_SInst_didiu6_acc<string opc, Intrinsic IntID>
673 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
674 u5Imm:$src2),
675 !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
676 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
677 DoubleRegs:$src1, imm:$src2))],
678 "$dst2 = $dst">;
679
680class di_SInst_didiu6_nac<string opc, Intrinsic IntID>
681 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
682 u5Imm:$src2),
683 !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
684 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
685 imm:$src2))],
686 "$dst2 = $dst">;
687
688
689//
690// MInst classes.
691//
692
693class di_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
694 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
695 !strconcat("$dst = ", !strconcat(opc ,
696 "($src1.H, $src2.H):<<1:rnd")),
697 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
698
699class di_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
700 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
701 !strconcat("$dst = ", !strconcat(opc ,
702 "($src1.H, $src2.H):rnd")),
703 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
704
705class di_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
706 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
707 !strconcat("$dst = ", !strconcat(opc ,
708 "($src1.H, $src2.L):<<1:rnd")),
709 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
710
711class di_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
712 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
713 !strconcat("$dst = ", !strconcat(opc ,
714 "($src1.H, $src2.L):rnd")),
715 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
716
717class di_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
718 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
719 !strconcat("$dst = ", !strconcat(opc ,
720 "($src1.L, $src2.H):<<1:rnd")),
721 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
722
723class di_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
724 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
725 !strconcat("$dst = ", !strconcat(opc ,
726 "($src1.L, $src2.H):rnd")),
727 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
728
729class di_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
730 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
731 !strconcat("$dst = ", !strconcat(opc ,
732 "($src1.L, $src2.L):<<1:rnd")),
733 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
734
735class di_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
736 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
737 !strconcat("$dst = ", !strconcat(opc ,
738 "($src1.L, $src2.L):rnd")),
739 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
740
741class di_MInst_disisi_acc<string opc, Intrinsic IntID>
742 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
743 IntRegs:$src2),
744 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
745 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
746 IntRegs:$src2))],
747 "$dst2 = $dst">;
748
749class di_MInst_disisi_nac<string opc, Intrinsic IntID>
750 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
751 IntRegs:$src2),
752 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
753 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
754 IntRegs:$src2))],
755 "$dst2 = $dst">;
756
757class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
758 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
759 IntRegs:$src2),
760 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
761 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
762 IntRegs:$src2))],
763 "$dst2 = $dst">;
764
765class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
766 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
767 IntRegs:$src2),
768 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
769 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
770 IntRegs:$src2))],
771 "$dst2 = $dst">;
772
773class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
774 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
775 IntRegs:$src2),
776 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
777 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
778 IntRegs:$src2))],
779 "$dst2 = $dst">;
780
781class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
782 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
783 IntRegs:$src2),
784 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
785 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
786 IntRegs:$src2))],
787 "$dst2 = $dst">;
788
789class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
790 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
791 IntRegs:$src2),
792 !strconcat("$dst -= ", !strconcat(opc ,
793 "($src1, $src2):<<1:sat")),
794 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
795 IntRegs:$src2))],
796 "$dst2 = $dst">;
797
798class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
799 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
800 IntRegs:$src2),
801 !strconcat("$dst += ", !strconcat(opc ,
802 "($src1, $src2*):<<1:sat")),
803 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
804 IntRegs:$src2))],
805 "$dst2 = $dst">;
806
807class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
808 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
809 IntRegs:$src2),
810 !strconcat("$dst -= ", !strconcat(opc ,
811 "($src1, $src2*):<<1:sat")),
812 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
813 IntRegs:$src2))],
814 "$dst2 = $dst">;
815
816class di_MInst_s8s8<string opc, Intrinsic IntID>
817 : MInst<(outs DoubleRegs:$dst), (ins s8Imm:$src1, s8Imm:$src2),
818 !strconcat("$dst = ", !strconcat(opc , "(#$src1, #$src2)")),
819 [(set DoubleRegs:$dst, (IntID imm:$src1, imm:$src2))]>;
820
821class si_MInst_sisi<string opc, Intrinsic IntID>
822 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
823 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
824 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
825
826class di_MInst_sisi_hh<string opc, Intrinsic IntID>
827 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
828 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
829 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
830
831class di_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
832 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
833 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
834 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
835
836class di_MInst_sisi_lh<string opc, Intrinsic IntID>
837 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
838 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
839 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
840
841class di_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
842 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
843 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
844 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
845
846class di_MInst_sisi_hl<string opc, Intrinsic IntID>
847 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
848 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
849 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
850
851class di_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
852 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
853 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
854 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
855
856class di_MInst_sisi_ll<string opc, Intrinsic IntID>
857 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
858 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
859 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
860
861class di_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
862 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
863 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
864 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
865
866
867class si_MInst_sisi_hh<string opc, Intrinsic IntID>
868 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
869 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
870 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
871
872class si_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
873 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
874 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
875 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
876
877class si_MInst_sisi_lh<string opc, Intrinsic IntID>
878 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
879 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
880 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
881
882class si_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
883 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
884 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
885 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
886
887class si_MInst_sisi_hl<string opc, Intrinsic IntID>
888 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
889 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
890 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
891
892class si_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
893 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
894 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
895 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
896
897class si_MInst_sisi_ll<string opc, Intrinsic IntID>
898 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
899 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
900 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
901
902class si_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
903 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
904 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
905 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
906
907class si_MInst_sisi_up<string opc, Intrinsic IntID>
908 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
909 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
910 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
911
912class di_MInst_didi<string opc, Intrinsic IntID>
913 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
914 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
915 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
916 DoubleRegs:$src2))]>;
917
918class di_MInst_didi_conj<string opc, Intrinsic IntID>
919 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
920 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
921 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
922 DoubleRegs:$src2))]>;
923
924class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
925 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
926 !strconcat("$dst = ", !strconcat(opc ,
927 "($src1, $src2*):<<1:sat")),
928 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
929
930class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
931 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
932 !strconcat("$dst = ", !strconcat(opc ,
933 "($src1, $src2):<<1:rnd:sat")),
934 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
935 DoubleRegs:$src2))]>;
936
937class di_MInst_didi_sat<string opc, Intrinsic IntID>
938 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
939 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
940 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
941 DoubleRegs:$src2))]>;
942
943class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
944 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
945 !strconcat("$dst = ", !strconcat(opc ,
946 "($src1, $src2):rnd:sat")),
947 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
948 DoubleRegs:$src2))]>;
949
950class si_SInst_sisi_sat<string opc, Intrinsic IntID>
951 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
952 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
953 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
954
955class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
956 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
957 !strconcat("$dst = ", !strconcat(opc ,
958 "($src1, $src2):<<1:rnd:sat")),
959 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
960
961class si_MInst_sisi_l_s1_rnd_sat<string opc, Intrinsic IntID>
962 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
963 !strconcat("$dst = ", !strconcat(opc ,
964 "($src1, $src2.L):<<1:rnd:sat")),
965 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
966
967class si_MInst_sisi_h_s1_rnd_sat<string opc, Intrinsic IntID>
968 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
969 !strconcat("$dst = ", !strconcat(opc ,
970 "($src1, $src2.H):<<1:rnd:sat")),
971 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
972
973class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
974 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
975 !strconcat("$dst = ", !strconcat(opc ,
976 "($src1, $src2*):rnd:sat")),
977 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
978
979class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
980 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
981 !strconcat("$dst = ", !strconcat(opc ,
982 "($src1, $src2*):<<1:rnd:sat")),
983 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
984
985class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
986 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
987 !strconcat("$dst = ", !strconcat(opc ,
988 "($src1, $src2):rnd:sat")),
989 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
990
991class si_MInst_sisi_rnd<string opc, Intrinsic IntID>
992 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
993 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
994 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
995
996class si_MInst_sisisi_xacc<string opc, Intrinsic IntID>
997 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
998 IntRegs:$src3),
999 !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
1000 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1001 IntRegs:$src3))],
1002 "$dst2 = $dst">;
1003
1004class si_MInst_sisisi_acc<string opc, Intrinsic IntID>
1005 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1006 IntRegs:$src3),
1007 !strconcat("$dst += ", !strconcat(opc , "($src2, $src3)")),
1008 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1009 IntRegs:$src3))],
1010 "$dst2 = $dst">;
1011
1012class si_MInst_sisisi_nac<string opc, Intrinsic IntID>
1013 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1014 IntRegs:$src3),
1015 !strconcat("$dst -= ", !strconcat(opc , "($src2, $src3)")),
1016 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1017 IntRegs:$src3))],
1018 "$dst2 = $dst">;
1019
1020class si_MInst_sisis8_acc<string opc, Intrinsic IntID>
1021 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1022 s8Imm:$src3),
1023 !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1024 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1025 imm:$src3))],
1026 "$dst2 = $dst">;
1027
1028class si_MInst_sisis8_nac<string opc, Intrinsic IntID>
1029 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1030 s8Imm:$src3),
1031 !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1032 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1033 imm:$src3))],
1034 "$dst2 = $dst">;
1035
1036class si_MInst_sisiu4u5<string opc, Intrinsic IntID>
1037 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1038 u4Imm:$src2, u5Imm:$src3),
1039 !strconcat("$dst = ", !strconcat(opc ,
1040 "($src1, #$src2, #$src3)")),
1041 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1042 imm:$src2, imm:$src3))],
1043 "$dst2 = $dst">;
1044
1045class si_MInst_sisiu8_acc<string opc, Intrinsic IntID>
1046 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1047 u8Imm:$src3),
1048 !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1049 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1050 imm:$src3))],
1051 "$dst2 = $dst">;
1052
1053class si_MInst_sisiu8_nac<string opc, Intrinsic IntID>
1054 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1055 u8Imm:$src3),
1056 !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1057 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1058 imm:$src3))],
1059 "$dst2 = $dst">;
1060
1061class si_MInst_sisisi_acc_hh<string opc, Intrinsic IntID>
1062 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1063 IntRegs:$src2),
1064 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1065 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1066 IntRegs:$src2))],
1067 "$dst2 = $dst">;
1068
1069class si_MInst_sisisi_acc_sat_lh<string opc, Intrinsic IntID>
1070 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1071 IntRegs:$src2),
1072 !strconcat("$dst += ", !strconcat(opc ,
1073 "($src1.L, $src2.H):sat")),
1074 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1075 IntRegs:$src2))],
1076 "$dst2 = $dst">;
1077
1078class si_MInst_sisisi_acc_sat_lh_s1<string opc, Intrinsic IntID>
1079 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1080 IntRegs:$src2),
1081 !strconcat("$dst += ", !strconcat(opc ,
1082 "($src1.L, $src2.H):<<1:sat")),
1083 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1084 IntRegs:$src2))],
1085 "$dst2 = $dst">;
1086
1087class si_MInst_sisisi_acc_sat_hh<string opc, Intrinsic IntID>
1088 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1089 IntRegs:$src2),
1090 !strconcat("$dst += ", !strconcat(opc ,
1091 "($src1.H, $src2.H):sat")),
1092 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1093 IntRegs:$src2))],
1094 "$dst2 = $dst">;
1095
1096class si_MInst_sisisi_acc_sat_hh_s1<string opc, Intrinsic IntID>
1097 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1098 IntRegs:$src2),
1099 !strconcat("$dst += ", !strconcat(opc ,
1100 "($src1.H, $src2.H):<<1:sat")),
1101 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1102 IntRegs:$src2))],
1103 "$dst2 = $dst">;
1104
1105class si_MInst_sisisi_acc_hh_s1<string opc, Intrinsic IntID>
1106 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1107 IntRegs:$src2),
1108 !strconcat("$dst += ", !strconcat(opc ,
1109 "($src1.H, $src2.H):<<1")),
1110 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1111 IntRegs:$src2))],
1112 "$dst2 = $dst">;
1113
1114class si_MInst_sisisi_nac_hh<string opc, Intrinsic IntID>
1115 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1116 IntRegs:$src2),
1117 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1118 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1119 IntRegs:$src2))],
1120 "$dst2 = $dst">;
1121
1122class si_MInst_sisisi_nac_sat_hh_s1<string opc, Intrinsic IntID>
1123 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1124 IntRegs:$src2),
1125 !strconcat("$dst -= ", !strconcat(opc ,
1126 "($src1.H, $src2.H):<<1:sat")),
1127 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1128 IntRegs:$src2))],
1129 "$dst2 = $dst">;
1130
1131class si_MInst_sisisi_nac_sat_hh<string opc, Intrinsic IntID>
1132 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1133 IntRegs:$src2),
1134 !strconcat("$dst -= ", !strconcat(opc ,
1135 "($src1.H, $src2.H):sat")),
1136 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1137 IntRegs:$src2))],
1138 "$dst2 = $dst">;
1139
1140class si_MInst_sisisi_nac_sat_hl_s1<string opc, Intrinsic IntID>
1141 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1142 IntRegs:$src2),
1143 !strconcat("$dst -= ", !strconcat(opc ,
1144 "($src1.H, $src2.L):<<1:sat")),
1145 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1146 IntRegs:$src2))],
1147 "$dst2 = $dst">;
1148
1149class si_MInst_sisisi_nac_sat_hl<string opc, Intrinsic IntID>
1150 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1151 IntRegs:$src2),
1152 !strconcat("$dst -= ", !strconcat(opc ,
1153 "($src1.H, $src2.L):sat")),
1154 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1155 IntRegs:$src2))],
1156 "$dst2 = $dst">;
1157
1158class si_MInst_sisisi_nac_sat_lh_s1<string opc, Intrinsic IntID>
1159 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1160 IntRegs:$src2),
1161 !strconcat("$dst -= ", !strconcat(opc ,
1162 "($src1.L, $src2.H):<<1:sat")),
1163 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1164 IntRegs:$src2))],
1165 "$dst2 = $dst">;
1166
1167class si_MInst_sisisi_nac_sat_lh<string opc, Intrinsic IntID>
1168 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1169 IntRegs:$src2),
1170 !strconcat("$dst -= ", !strconcat(opc ,
1171 "($src1.L, $src2.H):sat")),
1172 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1173 IntRegs:$src2))],
1174 "$dst2 = $dst">;
1175
1176class si_MInst_sisisi_nac_sat_ll_s1<string opc, Intrinsic IntID>
1177 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1178 IntRegs:$src2),
1179 !strconcat("$dst -= ", !strconcat(opc ,
1180 "($src1.L, $src2.L):<<1:sat")),
1181 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1182 IntRegs:$src2))],
1183 "$dst2 = $dst">;
1184
1185class si_MInst_sisisi_nac_sat_ll<string opc, Intrinsic IntID>
1186 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1187 IntRegs:$src2),
1188 !strconcat("$dst -= ", !strconcat(opc ,
1189 "($src1.L, $src2.L):sat")),
1190 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1191 IntRegs:$src2))],
1192 "$dst2 = $dst">;
1193
1194class si_MInst_sisisi_nac_hh_s1<string opc, Intrinsic IntID>
1195 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1196 IntRegs:$src2),
1197 !strconcat("$dst -= ", !strconcat(opc ,
1198 "($src1.H, $src2.H):<<1")),
1199 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1200 IntRegs:$src2))],
1201 "$dst2 = $dst">;
1202
1203class si_MInst_sisisi_acc_hl<string opc, Intrinsic IntID>
1204 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1205 IntRegs:$src2),
1206 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1207 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1208 IntRegs:$src2))],
1209 "$dst2 = $dst">;
1210
1211class si_MInst_sisisi_acc_hl_s1<string opc, Intrinsic IntID>
1212 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1213 IntRegs:$src2),
1214 !strconcat("$dst += ", !strconcat(opc ,
1215 "($src1.H, $src2.L):<<1")),
1216 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1217 IntRegs:$src2))],
1218 "$dst2 = $dst">;
1219
1220class si_MInst_sisisi_nac_hl<string opc, Intrinsic IntID>
1221 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1222 IntRegs:$src2),
1223 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1224 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1225 IntRegs:$src2))],
1226 "$dst2 = $dst">;
1227
1228class si_MInst_sisisi_nac_hl_s1<string opc, Intrinsic IntID>
1229 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1230 IntRegs:$src2),
1231 !strconcat("$dst -= ", !strconcat(opc ,
1232 "($src1.H, $src2.L):<<1")),
1233 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1234 IntRegs:$src2))],
1235 "$dst2 = $dst">;
1236
1237class si_MInst_sisisi_acc_lh<string opc, Intrinsic IntID>
1238 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1239 IntRegs:$src2),
1240 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1241 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1242 IntRegs:$src2))],
1243 "$dst2 = $dst">;
1244
1245class si_MInst_sisisi_acc_lh_s1<string opc, Intrinsic IntID>
1246 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1247 IntRegs:$src2),
1248 !strconcat("$dst += ", !strconcat(opc ,
1249 "($src1.L, $src2.H):<<1")),
1250 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1251 IntRegs:$src2))],
1252 "$dst2 = $dst">;
1253
1254class si_MInst_sisisi_nac_lh<string opc, Intrinsic IntID>
1255 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1256 IntRegs:$src2),
1257 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1258 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1259 IntRegs:$src2))],
1260 "$dst2 = $dst">;
1261
1262class si_MInst_sisisi_nac_lh_s1<string opc, Intrinsic IntID>
1263 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1264 IntRegs:$src2),
1265 !strconcat("$dst -= ", !strconcat(opc ,
1266 "($src1.L, $src2.H):<<1")),
1267 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1268 IntRegs:$src2))],
1269 "$dst2 = $dst">;
1270
1271class si_MInst_sisisi_acc_ll<string opc, Intrinsic IntID>
1272 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1273 IntRegs:$src2),
1274 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1275 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1276 IntRegs:$src2))],
1277 "$dst2 = $dst">;
1278
1279class si_MInst_sisisi_acc_ll_s1<string opc, Intrinsic IntID>
1280 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1281 IntRegs:$src2),
1282 !strconcat("$dst += ", !strconcat(opc ,
1283 "($src1.L, $src2.L):<<1")),
1284 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1285 IntRegs:$src2))],
1286 "$dst2 = $dst">;
1287
1288class si_MInst_sisisi_acc_sat_ll_s1<string opc, Intrinsic IntID>
1289 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1290 IntRegs:$src2),
1291 !strconcat("$dst += ", !strconcat(opc ,
1292 "($src1.L, $src2.L):<<1:sat")),
1293 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1294 IntRegs:$src2))],
1295 "$dst2 = $dst">;
1296
1297class si_MInst_sisisi_acc_sat_hl_s1<string opc, Intrinsic IntID>
1298 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1299 IntRegs:$src2),
1300 !strconcat("$dst += ", !strconcat(opc ,
1301 "($src1.H, $src2.L):<<1:sat")),
1302 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1303 IntRegs:$src2))],
1304 "$dst2 = $dst">;
1305
1306class si_MInst_sisisi_acc_sat_ll<string opc, Intrinsic IntID>
1307 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1308 IntRegs:$src2),
1309 !strconcat("$dst += ", !strconcat(opc ,
1310 "($src1.L, $src2.L):sat")),
1311 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1312 IntRegs:$src2))],
1313 "$dst2 = $dst">;
1314
1315class si_MInst_sisisi_acc_sat_hl<string opc, Intrinsic IntID>
1316 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1317 IntRegs:$src2),
1318 !strconcat("$dst += ", !strconcat(opc ,
1319 "($src1.H, $src2.L):sat")),
1320 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1321 IntRegs:$src2))],
1322 "$dst2 = $dst">;
1323
1324class si_MInst_sisisi_nac_ll<string opc, Intrinsic IntID>
1325 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1326 IntRegs:$src2),
1327 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1328 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1329 IntRegs:$src2))],
1330 "$dst2 = $dst">;
1331
1332class si_MInst_sisisi_nac_ll_s1<string opc, Intrinsic IntID>
1333 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1334 IntRegs:$src2),
1335 !strconcat("$dst -= ", !strconcat(opc ,
1336 "($src1.L, $src2.L):<<1")),
1337 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1338 IntRegs:$src2))],
1339 "$dst2 = $dst">;
1340
1341class si_MInst_sisisi_nac_hh_sat<string opc, Intrinsic IntID>
1342 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1343 IntRegs:$src2),
1344 !strconcat("$dst -= ", !strconcat(opc ,
1345 "($src1.H, $src2.H):sat")),
1346 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1347 IntRegs:$src2))],
1348 "$dst2 = $dst">;
1349
1350class si_MInst_sisisi_nac_hh_s1_sat<string opc, Intrinsic IntID>
1351 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1352 IntRegs:$src2),
1353 !strconcat("$dst -= ", !strconcat(opc ,
1354 "($src1.H, $src2.H):<<1:sat")),
1355 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1356 IntRegs:$src2))],
1357 "$dst2 = $dst">;
1358
1359class si_MInst_sisisi_nac_hl_sat<string opc, Intrinsic IntID>
1360 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1361 IntRegs:$src2),
1362 !strconcat("$dst -= ", !strconcat(opc ,
1363 "($src1.H, $src2.L):sat")),
1364 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1365 IntRegs:$src2))],
1366 "$dst2 = $dst">;
1367
1368class si_MInst_sisisi_nac_hl_s1_sat<string opc, Intrinsic IntID>
1369 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1370 IntRegs:$src2),
1371 !strconcat("$dst -= ", !strconcat(opc ,
1372 "($src1.H, $src2.L):<<1:sat")),
1373 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1374 IntRegs:$src2))],
1375 "$dst2 = $dst">;
1376
1377class si_MInst_sisisi_nac_lh_sat<string opc, Intrinsic IntID>
1378 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1379 IntRegs:$src2),
1380 !strconcat("$dst -= ", !strconcat(opc ,
1381 "($src1.L, $src2.H):sat")),
1382 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1383 IntRegs:$src2))],
1384 "$dst2 = $dst">;
1385
1386class si_MInst_sisisi_nac_lh_s1_sat<string opc, Intrinsic IntID>
1387 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1388 IntRegs:$src2),
1389 !strconcat("$dst -= ", !strconcat(opc ,
1390 "($src1.L, $src2.H):<<1:sat")),
1391 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1392 IntRegs:$src2))],
1393 "$dst2 = $dst">;
1394
1395class si_MInst_sisisi_nac_ll_sat<string opc, Intrinsic IntID>
1396 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1397 IntRegs:$src2),
1398 !strconcat("$dst -= ", !strconcat(opc ,
1399 "($src1.L, $src2.L):sat")),
1400 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1401 IntRegs:$src2))],
1402 "$dst2 = $dst">;
1403
1404class si_MInst_sisisi_nac_ll_s1_sat<string opc, Intrinsic IntID>
1405 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1406 IntRegs:$src2),
1407 !strconcat("$dst -= ", !strconcat(opc ,
1408 "($src1.L, $src2.L):<<1:sat")),
1409 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1410 IntRegs:$src2))],
1411 "$dst2 = $dst">;
1412
1413class di_ALU32_sisi<string opc, Intrinsic IntID>
1414 : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1415 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1416 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1417
1418class di_MInst_sisi<string opc, Intrinsic IntID>
1419 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1420 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1421 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1422
1423class di_MInst_sisi_sat<string opc, Intrinsic IntID>
1424 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1425 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1426 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1427
1428class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
1429 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1430 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
1431 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1432
1433class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
1434 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1435 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1436 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1437
1438class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
1439 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1440 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1441 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1442 DoubleRegs:$src2))]>;
1443
1444class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1445 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1446 !strconcat("$dst = ", !strconcat(opc ,
1447 "($src1, $src2):<<1:rnd:sat")),
1448 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1449
1450class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1451 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1452 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1453 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1454
1455class si_MInst_sisi_sat_hh<string opc, Intrinsic IntID>
1456 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1457 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
1458 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1459
1460class si_MInst_sisi_sat_hh_s1<string opc, Intrinsic IntID>
1461 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1462 !strconcat("$dst = ", !strconcat(opc ,
1463 "($src1.H, $src2.H):<<1:sat")),
1464 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1465
1466class si_MInst_sisi_sat_hl<string opc, Intrinsic IntID>
1467 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1468 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
1469 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1470
1471class si_MInst_sisi_sat_hl_s1<string opc, Intrinsic IntID>
1472 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1473 !strconcat("$dst = ", !strconcat(opc ,
1474 "($src1.H, $src2.L):<<1:sat")),
1475 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1476
1477class si_MInst_sisi_sat_lh<string opc, Intrinsic IntID>
1478 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1479 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
1480 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1481
1482class si_MInst_sisi_sat_lh_s1<string opc, Intrinsic IntID>
1483 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1484 !strconcat("$dst = ", !strconcat(opc ,
1485 "($src1.L, $src2.H):<<1:sat")),
1486 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1487
1488class si_MInst_sisi_sat_ll<string opc, Intrinsic IntID>
1489 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1490 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
1491 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1492
1493class si_MInst_sisi_sat_ll_s1<string opc, Intrinsic IntID>
1494 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1495 !strconcat("$dst = ", !strconcat(opc ,
1496 "($src1.L, $src2.L):<<1:sat")),
1497 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1498
1499class si_MInst_sisi_sat_rnd_hh<string opc, Intrinsic IntID>
1500 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1501 !strconcat("$dst = ", !strconcat(opc ,
1502 "($src1.H, $src2.H):rnd:sat")),
1503 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1504
1505class si_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1506 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1507 !strconcat("$dst = ", !strconcat(opc ,
1508 "($src1.H, $src2.H):rnd")),
1509 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1510
1511class si_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1512 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1513 !strconcat("$dst = ", !strconcat(opc ,
1514 "($src1.H, $src2.H):<<1:rnd")),
1515 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1516
1517class si_MInst_sisi_sat_rnd_hh_s1<string opc, Intrinsic IntID>
1518 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1519 !strconcat("$dst = ",
1520 !strconcat(opc ,
1521 "($src1.H, $src2.H):<<1:rnd:sat")),
1522 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1523
1524class si_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1525 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1526 !strconcat("$dst = ",
1527 !strconcat(opc , "($src1.H, $src2.L):rnd")),
1528 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1529
1530class si_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1531 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1532 !strconcat("$dst = ",
1533 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")),
1534 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1535
1536class si_MInst_sisi_sat_rnd_hl<string opc, Intrinsic IntID>
1537 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1538 !strconcat("$dst = ",
1539 !strconcat(opc , "($src1.H, $src2.L):rnd:sat")),
1540 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1541
1542class si_MInst_sisi_sat_rnd_hl_s1<string opc, Intrinsic IntID>
1543 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1544 !strconcat("$dst = ",
1545 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")),
1546 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1547
1548class si_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1549 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1550 !strconcat("$dst = ",
1551 !strconcat(opc , "($src1.L, $src2.H):rnd")),
1552 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1553
1554class si_MInst_sisi_sat_rnd_lh<string opc, Intrinsic IntID>
1555 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1556 !strconcat("$dst = ",
1557 !strconcat(opc , "($src1.L, $src2.H):rnd:sat")),
1558 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1559
1560class si_MInst_sisi_sat_rnd_lh_s1<string opc, Intrinsic IntID>
1561 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1562 !strconcat("$dst = ",
1563 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")),
1564 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1565
1566class si_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1567 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1568 !strconcat("$dst = ",
1569 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")),
1570 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1571
1572class si_MInst_sisi_sat_rnd_ll<string opc, Intrinsic IntID>
1573 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1574 !strconcat("$dst = ",
1575 !strconcat(opc , "($src1.L, $src2.L):rnd:sat")),
1576 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1577
1578class si_MInst_sisi_sat_rnd_ll_s1<string opc, Intrinsic IntID>
1579 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1580 !strconcat("$dst = ",
1581 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")),
1582 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1583
1584class si_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1585 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1586 !strconcat("$dst = ",
1587 !strconcat(opc , "($src1.L, $src2.L):rnd")),
1588 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1589
1590class si_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1591 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1592 !strconcat("$dst = ",
1593 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")),
1594 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1595
1596class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
1597 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1598 DoubleRegs:$src1, DoubleRegs:$src2),
1599 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1600 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1601 DoubleRegs:$src1,
1602 DoubleRegs:$src2))],
1603 "$dst2 = $dst">;
1604
1605class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
1606 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1607 DoubleRegs:$src2),
1608 !strconcat("$dst += ",
1609 !strconcat(opc , "($src1, $src2):rnd:sat")),
1610 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1611 DoubleRegs:$src1,
1612 DoubleRegs:$src2))],
1613 "$dst2 = $dst">;
1614
1615class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
1616 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1617 DoubleRegs:$src1,
1618 DoubleRegs:$src2),
1619 !strconcat("$dst += ",
1620 !strconcat(opc , "($src1, $src2):<<1:sat")),
1621 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1622 DoubleRegs:$src1,
1623 DoubleRegs:$src2))],
1624 "$dst2 = $dst">;
1625
1626class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
1627 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1628 DoubleRegs:$src2),
1629 !strconcat("$dst += ",
1630 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1631 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1632 DoubleRegs:$src1,
1633 DoubleRegs:$src2))],
1634 "$dst2 = $dst">;
1635
1636class di_MInst_dididi_acc<string opc, Intrinsic IntID>
1637 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1638 DoubleRegs:$src2),
1639 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1640 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1641 DoubleRegs:$src1,
1642 DoubleRegs:$src2))],
1643 "$dst2 = $dst">;
1644
1645class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
1646 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1647 DoubleRegs:$src2),
1648 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
1649 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1650 DoubleRegs:$src1,
1651 DoubleRegs:$src2))],
1652 "$dst2 = $dst">;
1653
1654class di_MInst_disisi_acc_hh<string opc, Intrinsic IntID>
1655 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1656 IntRegs:$src2),
1657 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1658 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1659 IntRegs:$src2))],
1660 "$dst2 = $dst">;
1661
1662class di_MInst_disisi_acc_hl<string opc, Intrinsic IntID>
1663 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1664 IntRegs:$src2),
1665 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1666 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1667 IntRegs:$src2))],
1668 "$dst2 = $dst">;
1669
1670class di_MInst_disisi_acc_lh<string opc, Intrinsic IntID>
1671 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1672 IntRegs:$src2),
1673 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1674 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1675 IntRegs:$src2))],
1676 "$dst2 = $dst">;
1677
1678class di_MInst_disisi_acc_ll<string opc, Intrinsic IntID>
1679 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1680 IntRegs:$src2),
1681 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1682 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1683 IntRegs:$src2))],
1684 "$dst2 = $dst">;
1685
1686class di_MInst_disisi_acc_hh_s1<string opc, Intrinsic IntID>
1687 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1688 IntRegs:$src2),
1689 !strconcat("$dst += ",
1690 !strconcat(opc , "($src1.H, $src2.H):<<1")),
1691 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1692 IntRegs:$src2))],
1693 "$dst2 = $dst">;
1694
1695class di_MInst_disisi_acc_hl_s1<string opc, Intrinsic IntID>
1696 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1697 IntRegs:$src2),
1698 !strconcat("$dst += ",
1699 !strconcat(opc , "($src1.H, $src2.L):<<1")),
1700 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1701 IntRegs:$src2))],
1702 "$dst2 = $dst">;
1703
1704class di_MInst_disisi_acc_lh_s1<string opc, Intrinsic IntID>
1705 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1706 IntRegs:$src2),
1707 !strconcat("$dst += ",
1708 !strconcat(opc , "($src1.L, $src2.H):<<1")),
1709 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1710 IntRegs:$src2))],
1711 "$dst2 = $dst">;
1712
1713class di_MInst_disisi_acc_ll_s1<string opc, Intrinsic IntID>
1714 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1715 IntRegs:$src2),
1716 !strconcat("$dst += ",
1717 !strconcat(opc , "($src1.L, $src2.L):<<1")),
1718 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1719 IntRegs:$src2))],
1720 "$dst2 = $dst">;
1721
1722class di_MInst_disisi_nac_hh<string opc, Intrinsic IntID>
1723 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1724 IntRegs:$src2),
1725 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1726 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1727 IntRegs:$src2))],
1728 "$dst2 = $dst">;
1729
1730class di_MInst_disisi_nac_hl<string opc, Intrinsic IntID>
1731 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1732 IntRegs:$src2),
1733 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1734 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1735 IntRegs:$src2))],
1736 "$dst2 = $dst">;
1737
1738class di_MInst_disisi_nac_lh<string opc, Intrinsic IntID>
1739 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1740 IntRegs:$src2),
1741 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1742 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1743 IntRegs:$src2))],
1744 "$dst2 = $dst">;
1745
1746class di_MInst_disisi_nac_ll<string opc, Intrinsic IntID>
1747 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1748 IntRegs:$src2),
1749 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1750 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1751 IntRegs:$src2))],
1752 "$dst2 = $dst">;
1753
1754class di_MInst_disisi_nac_hh_s1<string opc, Intrinsic IntID>
1755 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1756 IntRegs:$src2),
1757 !strconcat("$dst -= ",
1758 !strconcat(opc , "($src1.H, $src2.H):<<1")),
1759 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1760 IntRegs:$src2))],
1761 "$dst2 = $dst">;
1762
1763class di_MInst_disisi_nac_hl_s1<string opc, Intrinsic IntID>
1764 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1765 IntRegs:$src2),
1766 !strconcat("$dst -= ",
1767 !strconcat(opc , "($src1.H, $src2.L):<<1")),
1768 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1769 IntRegs:$src2))],
1770 "$dst2 = $dst">;
1771
1772class di_MInst_disisi_nac_lh_s1<string opc, Intrinsic IntID>
1773 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1774 IntRegs:$src2),
1775 !strconcat("$dst -= ",
1776 !strconcat(opc , "($src1.L, $src2.H):<<1")),
1777 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1778 IntRegs:$src2))],
1779 "$dst2 = $dst">;
1780
1781class di_MInst_disisi_nac_ll_s1<string opc, Intrinsic IntID>
1782 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1783 IntRegs:$src2),
1784 !strconcat("$dst -= ",
1785 !strconcat(opc , "($src1.L, $src2.L):<<1")),
1786 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1787 IntRegs:$src2))],
1788 "$dst2 = $dst">;
1789
1790class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
1791 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1792 IntRegs:$src2),
1793 !strconcat("$dst += ",
1794 !strconcat(opc , "($src1, $src2):<<1:sat")),
1795 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1796 IntRegs:$src2))],
1797 "$dst2 = $dst">;
1798
1799class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
1800 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1801 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1802 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1803
1804class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
1805 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1806 IntRegs:$src2),
1807 !strconcat("$dst += ",
1808 !strconcat(opc , "($src1, $src2):<<1:sat")),
1809 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1810 DoubleRegs:$src1,
1811 IntRegs:$src2))],
1812 "$dst2 = $dst">;
1813
1814class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1815 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1816 !strconcat("$dst = ",
1817 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1818 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1819
1820class si_MInst_didi<string opc, Intrinsic IntID>
1821 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1822 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1823 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1824
1825
1826/********************************************************************
1827* ALU32/ALU *
1828*********************************************************************/
1829
1830// ALU32 / ALU / Add.
1831def Hexagon_A2_add:
1832 si_ALU32_sisi <"add", int_hexagon_A2_add>;
1833def Hexagon_A2_addi:
1834 si_ALU32_sis16 <"add", int_hexagon_A2_addi>;
1835
1836// ALU32 / ALU / Logical operations.
1837def Hexagon_A2_and:
1838 si_ALU32_sisi <"and", int_hexagon_A2_and>;
1839def Hexagon_A2_andir:
1840 si_ALU32_sis10 <"and", int_hexagon_A2_andir>;
1841def Hexagon_A2_not:
1842 si_ALU32_si <"not", int_hexagon_A2_not>;
1843def Hexagon_A2_or:
1844 si_ALU32_sisi <"or", int_hexagon_A2_or>;
1845def Hexagon_A2_orir:
1846 si_ALU32_sis10 <"or", int_hexagon_A2_orir>;
1847def Hexagon_A2_xor:
1848 si_ALU32_sisi <"xor", int_hexagon_A2_xor>;
1849
1850// ALU32 / ALU / Negate.
1851def Hexagon_A2_neg:
1852 si_ALU32_si <"neg", int_hexagon_A2_neg>;
1853
1854// ALU32 / ALU / Subtract.
1855def Hexagon_A2_sub:
1856 si_ALU32_sisi <"sub", int_hexagon_A2_sub>;
1857def Hexagon_A2_subri:
1858 si_ALU32_s10si <"sub", int_hexagon_A2_subri>;
1859
1860// ALU32 / ALU / Transfer Immediate.
1861def Hexagon_A2_tfril:
1862 si_lo_ALU32_siu16 <"", int_hexagon_A2_tfril>;
1863def Hexagon_A2_tfrih:
1864 si_hi_ALU32_siu16 <"", int_hexagon_A2_tfrih>;
1865def Hexagon_A2_tfrsi:
1866 si_ALU32_s16 <"", int_hexagon_A2_tfrsi>;
1867def Hexagon_A2_tfrpi:
1868 di_ALU32_s8 <"", int_hexagon_A2_tfrpi>;
1869
1870// ALU32 / ALU / Transfer Register.
1871def Hexagon_A2_tfr:
1872 si_ALU32_si_tfr <"", int_hexagon_A2_tfr>;
1873
1874/********************************************************************
1875* ALU32/PERM *
1876*********************************************************************/
1877
1878// ALU32 / PERM / Combine.
1879def Hexagon_A2_combinew:
1880 di_ALU32_sisi <"combine", int_hexagon_A2_combinew>;
1881def Hexagon_A2_combine_hh:
1882 si_MInst_sisi_hh <"combine", int_hexagon_A2_combine_hh>;
1883def Hexagon_A2_combine_lh:
1884 si_MInst_sisi_lh <"combine", int_hexagon_A2_combine_lh>;
1885def Hexagon_A2_combine_hl:
1886 si_MInst_sisi_hl <"combine", int_hexagon_A2_combine_hl>;
1887def Hexagon_A2_combine_ll:
1888 si_MInst_sisi_ll <"combine", int_hexagon_A2_combine_ll>;
1889def Hexagon_A2_combineii:
1890 di_MInst_s8s8 <"combine", int_hexagon_A2_combineii>;
1891
1892// ALU32 / PERM / Mux.
1893def Hexagon_C2_mux:
1894 si_ALU32_qisisi <"mux", int_hexagon_C2_mux>;
1895def Hexagon_C2_muxri:
1896 si_ALU32_qis8si <"mux", int_hexagon_C2_muxri>;
1897def Hexagon_C2_muxir:
1898 si_ALU32_qisis8 <"mux", int_hexagon_C2_muxir>;
1899def Hexagon_C2_muxii:
1900 si_ALU32_qis8s8 <"mux", int_hexagon_C2_muxii>;
1901
1902// ALU32 / PERM / Shift halfword.
1903def Hexagon_A2_aslh:
1904 si_ALU32_si <"aslh", int_hexagon_A2_aslh>;
1905def Hexagon_A2_asrh:
1906 si_ALU32_si <"asrh", int_hexagon_A2_asrh>;
1907def SI_to_SXTHI_asrh:
1908 si_ALU32_si <"asrh", int_hexagon_SI_to_SXTHI_asrh>;
1909
1910// ALU32 / PERM / Sign/zero extend.
1911def Hexagon_A2_sxth:
1912 si_ALU32_si <"sxth", int_hexagon_A2_sxth>;
1913def Hexagon_A2_sxtb:
1914 si_ALU32_si <"sxtb", int_hexagon_A2_sxtb>;
1915def Hexagon_A2_zxth:
1916 si_ALU32_si <"zxth", int_hexagon_A2_zxth>;
1917def Hexagon_A2_zxtb:
1918 si_ALU32_si <"zxtb", int_hexagon_A2_zxtb>;
1919
1920/********************************************************************
1921* ALU32/PRED *
1922*********************************************************************/
1923
1924// ALU32 / PRED / Compare.
1925def Hexagon_C2_cmpeq:
1926 qi_ALU32_sisi <"cmp.eq", int_hexagon_C2_cmpeq>;
1927def Hexagon_C2_cmpeqi:
1928 qi_ALU32_sis10 <"cmp.eq", int_hexagon_C2_cmpeqi>;
1929def Hexagon_C2_cmpgei:
1930 qi_ALU32_sis8 <"cmp.ge", int_hexagon_C2_cmpgei>;
1931def Hexagon_C2_cmpgeui:
1932 qi_ALU32_siu8 <"cmp.geu", int_hexagon_C2_cmpgeui>;
1933def Hexagon_C2_cmpgt:
1934 qi_ALU32_sisi <"cmp.gt", int_hexagon_C2_cmpgt>;
1935def Hexagon_C2_cmpgti:
1936 qi_ALU32_sis10 <"cmp.gt", int_hexagon_C2_cmpgti>;
1937def Hexagon_C2_cmpgtu:
1938 qi_ALU32_sisi <"cmp.gtu", int_hexagon_C2_cmpgtu>;
1939def Hexagon_C2_cmpgtui:
1940 qi_ALU32_siu9 <"cmp.gtu", int_hexagon_C2_cmpgtui>;
1941def Hexagon_C2_cmplt:
1942 qi_ALU32_sisi <"cmp.lt", int_hexagon_C2_cmplt>;
1943def Hexagon_C2_cmpltu:
1944 qi_ALU32_sisi <"cmp.ltu", int_hexagon_C2_cmpltu>;
1945
1946/********************************************************************
1947* ALU32/VH *
1948*********************************************************************/
1949
1950// ALU32 / VH / Vector add halfwords.
1951// Rd32=vadd[u]h(Rs32,Rt32:sat]
1952def Hexagon_A2_svaddh:
1953 si_ALU32_sisi <"vaddh", int_hexagon_A2_svaddh>;
1954def Hexagon_A2_svaddhs:
1955 si_ALU32_sisi_sat <"vaddh", int_hexagon_A2_svaddhs>;
1956def Hexagon_A2_svadduhs:
1957 si_ALU32_sisi_sat <"vadduh", int_hexagon_A2_svadduhs>;
1958
1959// ALU32 / VH / Vector average halfwords.
1960def Hexagon_A2_svavgh:
1961 si_ALU32_sisi <"vavgh", int_hexagon_A2_svavgh>;
1962def Hexagon_A2_svavghs:
1963 si_ALU32_sisi_rnd <"vavgh", int_hexagon_A2_svavghs>;
1964def Hexagon_A2_svnavgh:
1965 si_ALU32_sisi <"vnavgh", int_hexagon_A2_svnavgh>;
1966
1967// ALU32 / VH / Vector subtract halfwords.
1968def Hexagon_A2_svsubh:
1969 si_ALU32_sisi <"vsubh", int_hexagon_A2_svsubh>;
1970def Hexagon_A2_svsubhs:
1971 si_ALU32_sisi_sat <"vsubh", int_hexagon_A2_svsubhs>;
1972def Hexagon_A2_svsubuhs:
1973 si_ALU32_sisi_sat <"vsubuh", int_hexagon_A2_svsubuhs>;
1974
1975/********************************************************************
1976* ALU64/ALU *
1977*********************************************************************/
1978
1979// ALU64 / ALU / Add.
1980def Hexagon_A2_addp:
1981 di_ALU64_didi <"add", int_hexagon_A2_addp>;
1982def Hexagon_A2_addsat:
1983 si_ALU64_sisi_sat <"add", int_hexagon_A2_addsat>;
1984
1985// ALU64 / ALU / Add halfword.
1986// Even though the definition says hl, it should be lh -
1987//so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
1988def Hexagon_A2_addh_l16_hl:
1989 si_ALU64_sisi_l16_lh <"add", int_hexagon_A2_addh_l16_hl>;
1990def Hexagon_A2_addh_l16_ll:
1991 si_ALU64_sisi_l16_ll <"add", int_hexagon_A2_addh_l16_ll>;
1992
1993def Hexagon_A2_addh_l16_sat_hl:
1994 si_ALU64_sisi_l16_sat_lh <"add", int_hexagon_A2_addh_l16_sat_hl>;
1995def Hexagon_A2_addh_l16_sat_ll:
1996 si_ALU64_sisi_l16_sat_ll <"add", int_hexagon_A2_addh_l16_sat_ll>;
1997
1998def Hexagon_A2_addh_h16_hh:
1999 si_ALU64_sisi_h16_hh <"add", int_hexagon_A2_addh_h16_hh>;
2000def Hexagon_A2_addh_h16_hl:
2001 si_ALU64_sisi_h16_hl <"add", int_hexagon_A2_addh_h16_hl>;
2002def Hexagon_A2_addh_h16_lh:
2003 si_ALU64_sisi_h16_lh <"add", int_hexagon_A2_addh_h16_lh>;
2004def Hexagon_A2_addh_h16_ll:
2005 si_ALU64_sisi_h16_ll <"add", int_hexagon_A2_addh_h16_ll>;
2006
2007def Hexagon_A2_addh_h16_sat_hh:
2008 si_ALU64_sisi_h16_sat_hh <"add", int_hexagon_A2_addh_h16_sat_hh>;
2009def Hexagon_A2_addh_h16_sat_hl:
2010 si_ALU64_sisi_h16_sat_hl <"add", int_hexagon_A2_addh_h16_sat_hl>;
2011def Hexagon_A2_addh_h16_sat_lh:
2012 si_ALU64_sisi_h16_sat_lh <"add", int_hexagon_A2_addh_h16_sat_lh>;
2013def Hexagon_A2_addh_h16_sat_ll:
2014 si_ALU64_sisi_h16_sat_ll <"add", int_hexagon_A2_addh_h16_sat_ll>;
2015
2016// ALU64 / ALU / Compare.
2017def Hexagon_C2_cmpeqp:
2018 qi_ALU64_didi <"cmp.eq", int_hexagon_C2_cmpeqp>;
2019def Hexagon_C2_cmpgtp:
2020 qi_ALU64_didi <"cmp.gt", int_hexagon_C2_cmpgtp>;
2021def Hexagon_C2_cmpgtup:
2022 qi_ALU64_didi <"cmp.gtu", int_hexagon_C2_cmpgtup>;
2023
2024// ALU64 / ALU / Logical operations.
2025def Hexagon_A2_andp:
2026 di_ALU64_didi <"and", int_hexagon_A2_andp>;
2027def Hexagon_A2_orp:
2028 di_ALU64_didi <"or", int_hexagon_A2_orp>;
2029def Hexagon_A2_xorp:
2030 di_ALU64_didi <"xor", int_hexagon_A2_xorp>;
2031
2032// ALU64 / ALU / Maximum.
2033def Hexagon_A2_max:
2034 si_ALU64_sisi <"max", int_hexagon_A2_max>;
2035def Hexagon_A2_maxu:
2036 si_ALU64_sisi <"maxu", int_hexagon_A2_maxu>;
2037
2038// ALU64 / ALU / Minimum.
2039def Hexagon_A2_min:
2040 si_ALU64_sisi <"min", int_hexagon_A2_min>;
2041def Hexagon_A2_minu:
2042 si_ALU64_sisi <"minu", int_hexagon_A2_minu>;
2043
2044// ALU64 / ALU / Subtract.
2045def Hexagon_A2_subp:
2046 di_ALU64_didi <"sub", int_hexagon_A2_subp>;
2047def Hexagon_A2_subsat:
2048 si_ALU64_sisi_sat <"sub", int_hexagon_A2_subsat>;
2049
2050// ALU64 / ALU / Subtract halfword.
2051// Even though the definition says hl, it should be lh -
2052//so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2053def Hexagon_A2_subh_l16_hl:
2054 si_ALU64_sisi_l16_lh <"sub", int_hexagon_A2_subh_l16_hl>;
2055def Hexagon_A2_subh_l16_ll:
2056 si_ALU64_sisi_l16_ll <"sub", int_hexagon_A2_subh_l16_ll>;
2057
2058def Hexagon_A2_subh_l16_sat_hl:
2059 si_ALU64_sisi_l16_sat_lh <"sub", int_hexagon_A2_subh_l16_sat_hl>;
2060def Hexagon_A2_subh_l16_sat_ll:
2061 si_ALU64_sisi_l16_sat_ll <"sub", int_hexagon_A2_subh_l16_sat_ll>;
2062
2063def Hexagon_A2_subh_h16_hh:
2064 si_ALU64_sisi_h16_hh <"sub", int_hexagon_A2_subh_h16_hh>;
2065def Hexagon_A2_subh_h16_hl:
2066 si_ALU64_sisi_h16_hl <"sub", int_hexagon_A2_subh_h16_hl>;
2067def Hexagon_A2_subh_h16_lh:
2068 si_ALU64_sisi_h16_lh <"sub", int_hexagon_A2_subh_h16_lh>;
2069def Hexagon_A2_subh_h16_ll:
2070 si_ALU64_sisi_h16_ll <"sub", int_hexagon_A2_subh_h16_ll>;
2071
2072def Hexagon_A2_subh_h16_sat_hh:
2073 si_ALU64_sisi_h16_sat_hh <"sub", int_hexagon_A2_subh_h16_sat_hh>;
2074def Hexagon_A2_subh_h16_sat_hl:
2075 si_ALU64_sisi_h16_sat_hl <"sub", int_hexagon_A2_subh_h16_sat_hl>;
2076def Hexagon_A2_subh_h16_sat_lh:
2077 si_ALU64_sisi_h16_sat_lh <"sub", int_hexagon_A2_subh_h16_sat_lh>;
2078def Hexagon_A2_subh_h16_sat_ll:
2079 si_ALU64_sisi_h16_sat_ll <"sub", int_hexagon_A2_subh_h16_sat_ll>;
2080
2081// ALU64 / ALU / Transfer register.
2082def Hexagon_A2_tfrp:
2083 di_ALU64_di <"", int_hexagon_A2_tfrp>;
2084
2085/********************************************************************
2086* ALU64/BIT *
2087*********************************************************************/
2088
2089// ALU64 / BIT / Masked parity.
2090def Hexagon_S2_parityp:
2091 si_ALU64_didi <"parity", int_hexagon_S2_parityp>;
2092
2093/********************************************************************
2094* ALU64/PERM *
2095*********************************************************************/
2096
2097// ALU64 / PERM / Vector pack high and low halfwords.
2098def Hexagon_S2_packhl:
2099 di_ALU64_sisi <"packhl", int_hexagon_S2_packhl>;
2100
2101/********************************************************************
2102* ALU64/VB *
2103*********************************************************************/
2104
2105// ALU64 / VB / Vector add unsigned bytes.
2106def Hexagon_A2_vaddub:
2107 di_ALU64_didi <"vaddub", int_hexagon_A2_vaddub>;
2108def Hexagon_A2_vaddubs:
2109 di_ALU64_didi_sat <"vaddub", int_hexagon_A2_vaddubs>;
2110
2111// ALU64 / VB / Vector average unsigned bytes.
2112def Hexagon_A2_vavgub:
2113 di_ALU64_didi <"vavgub", int_hexagon_A2_vavgub>;
2114def Hexagon_A2_vavgubr:
2115 di_ALU64_didi_rnd <"vavgub", int_hexagon_A2_vavgubr>;
2116
2117// ALU64 / VB / Vector compare unsigned bytes.
2118def Hexagon_A2_vcmpbeq:
2119 qi_ALU64_didi <"vcmpb.eq", int_hexagon_A2_vcmpbeq>;
2120def Hexagon_A2_vcmpbgtu:
2121 qi_ALU64_didi <"vcmpb.gtu",int_hexagon_A2_vcmpbgtu>;
2122
2123// ALU64 / VB / Vector maximum/minimum unsigned bytes.
2124def Hexagon_A2_vmaxub:
2125 di_ALU64_didi <"vmaxub", int_hexagon_A2_vmaxub>;
2126def Hexagon_A2_vminub:
2127 di_ALU64_didi <"vminub", int_hexagon_A2_vminub>;
2128
2129// ALU64 / VB / Vector subtract unsigned bytes.
2130def Hexagon_A2_vsubub:
2131 di_ALU64_didi <"vsubub", int_hexagon_A2_vsubub>;
2132def Hexagon_A2_vsububs:
2133 di_ALU64_didi_sat <"vsubub", int_hexagon_A2_vsububs>;
2134
2135// ALU64 / VB / Vector mux.
2136def Hexagon_C2_vmux:
2137 di_ALU64_qididi <"vmux", int_hexagon_C2_vmux>;
2138
2139
2140/********************************************************************
2141* ALU64/VH *
2142*********************************************************************/
2143
2144// ALU64 / VH / Vector add halfwords.
2145// Rdd64=vadd[u]h(Rss64,Rtt64:sat]
2146def Hexagon_A2_vaddh:
2147 di_ALU64_didi <"vaddh", int_hexagon_A2_vaddh>;
2148def Hexagon_A2_vaddhs:
2149 di_ALU64_didi_sat <"vaddh", int_hexagon_A2_vaddhs>;
2150def Hexagon_A2_vadduhs:
2151 di_ALU64_didi_sat <"vadduh", int_hexagon_A2_vadduhs>;
2152
2153// ALU64 / VH / Vector average halfwords.
2154// Rdd64=v[n]avg[u]h(Rss64,Rtt64:rnd/:crnd][:sat]
2155def Hexagon_A2_vavgh:
2156 di_ALU64_didi <"vavgh", int_hexagon_A2_vavgh>;
2157def Hexagon_A2_vavghcr:
2158 di_ALU64_didi_crnd <"vavgh", int_hexagon_A2_vavghcr>;
2159def Hexagon_A2_vavghr:
2160 di_ALU64_didi_rnd <"vavgh", int_hexagon_A2_vavghr>;
2161def Hexagon_A2_vavguh:
2162 di_ALU64_didi <"vavguh", int_hexagon_A2_vavguh>;
2163def Hexagon_A2_vavguhr:
2164 di_ALU64_didi_rnd <"vavguh", int_hexagon_A2_vavguhr>;
2165def Hexagon_A2_vnavgh:
2166 di_ALU64_didi <"vnavgh", int_hexagon_A2_vnavgh>;
2167def Hexagon_A2_vnavghcr:
2168 di_ALU64_didi_crnd_sat <"vnavgh", int_hexagon_A2_vnavghcr>;
2169def Hexagon_A2_vnavghr:
2170 di_ALU64_didi_rnd_sat <"vnavgh", int_hexagon_A2_vnavghr>;
2171
2172// ALU64 / VH / Vector compare halfwords.
2173def Hexagon_A2_vcmpheq:
2174 qi_ALU64_didi <"vcmph.eq", int_hexagon_A2_vcmpheq>;
2175def Hexagon_A2_vcmphgt:
2176 qi_ALU64_didi <"vcmph.gt", int_hexagon_A2_vcmphgt>;
2177def Hexagon_A2_vcmphgtu:
2178 qi_ALU64_didi <"vcmph.gtu",int_hexagon_A2_vcmphgtu>;
2179
2180// ALU64 / VH / Vector maximum halfwords.
2181def Hexagon_A2_vmaxh:
2182 di_ALU64_didi <"vmaxh", int_hexagon_A2_vmaxh>;
2183def Hexagon_A2_vmaxuh:
2184 di_ALU64_didi <"vmaxuh", int_hexagon_A2_vmaxuh>;
2185
2186// ALU64 / VH / Vector minimum halfwords.
2187def Hexagon_A2_vminh:
2188 di_ALU64_didi <"vminh", int_hexagon_A2_vminh>;
2189def Hexagon_A2_vminuh:
2190 di_ALU64_didi <"vminuh", int_hexagon_A2_vminuh>;
2191
2192// ALU64 / VH / Vector subtract halfwords.
2193def Hexagon_A2_vsubh:
2194 di_ALU64_didi <"vsubh", int_hexagon_A2_vsubh>;
2195def Hexagon_A2_vsubhs:
2196 di_ALU64_didi_sat <"vsubh", int_hexagon_A2_vsubhs>;
2197def Hexagon_A2_vsubuhs:
2198 di_ALU64_didi_sat <"vsubuh", int_hexagon_A2_vsubuhs>;
2199
2200
2201/********************************************************************
2202* ALU64/VW *
2203*********************************************************************/
2204
2205// ALU64 / VW / Vector add words.
2206// Rdd32=vaddw(Rss32,Rtt32)[:sat]
2207def Hexagon_A2_vaddw:
2208 di_ALU64_didi <"vaddw", int_hexagon_A2_vaddw>;
2209def Hexagon_A2_vaddws:
2210 di_ALU64_didi_sat <"vaddw", int_hexagon_A2_vaddws>;
2211
2212// ALU64 / VW / Vector average words.
2213def Hexagon_A2_vavguw:
2214 di_ALU64_didi <"vavguw", int_hexagon_A2_vavguw>;
2215def Hexagon_A2_vavguwr:
2216 di_ALU64_didi_rnd <"vavguw", int_hexagon_A2_vavguwr>;
2217def Hexagon_A2_vavgw:
2218 di_ALU64_didi <"vavgw", int_hexagon_A2_vavgw>;
2219def Hexagon_A2_vavgwcr:
2220 di_ALU64_didi_crnd <"vavgw", int_hexagon_A2_vavgwcr>;
2221def Hexagon_A2_vavgwr:
2222 di_ALU64_didi_rnd <"vavgw", int_hexagon_A2_vavgwr>;
2223def Hexagon_A2_vnavgw:
2224 di_ALU64_didi <"vnavgw", int_hexagon_A2_vnavgw>;
2225def Hexagon_A2_vnavgwcr:
2226 di_ALU64_didi_crnd_sat <"vnavgw", int_hexagon_A2_vnavgwcr>;
2227def Hexagon_A2_vnavgwr:
2228 di_ALU64_didi_rnd_sat <"vnavgw", int_hexagon_A2_vnavgwr>;
2229
2230// ALU64 / VW / Vector compare words.
2231def Hexagon_A2_vcmpweq:
2232 qi_ALU64_didi <"vcmpw.eq", int_hexagon_A2_vcmpweq>;
2233def Hexagon_A2_vcmpwgt:
2234 qi_ALU64_didi <"vcmpw.gt", int_hexagon_A2_vcmpwgt>;
2235def Hexagon_A2_vcmpwgtu:
2236 qi_ALU64_didi <"vcmpw.gtu",int_hexagon_A2_vcmpwgtu>;
2237
2238// ALU64 / VW / Vector maximum words.
2239def Hexagon_A2_vmaxw:
2240 di_ALU64_didi <"vmaxw", int_hexagon_A2_vmaxw>;
2241def Hexagon_A2_vmaxuw:
2242 di_ALU64_didi <"vmaxuw", int_hexagon_A2_vmaxuw>;
2243
2244// ALU64 / VW / Vector minimum words.
2245def Hexagon_A2_vminw:
2246 di_ALU64_didi <"vminw", int_hexagon_A2_vminw>;
2247def Hexagon_A2_vminuw:
2248 di_ALU64_didi <"vminuw", int_hexagon_A2_vminuw>;
2249
2250// ALU64 / VW / Vector subtract words.
2251def Hexagon_A2_vsubw:
2252 di_ALU64_didi <"vsubw", int_hexagon_A2_vsubw>;
2253def Hexagon_A2_vsubws:
2254 di_ALU64_didi_sat <"vsubw", int_hexagon_A2_vsubws>;
2255
2256
2257/********************************************************************
2258* CR *
2259*********************************************************************/
2260
2261// CR / Logical reductions on predicates.
2262def Hexagon_C2_all8:
2263 qi_SInst_qi <"all8", int_hexagon_C2_all8>;
2264def Hexagon_C2_any8:
2265 qi_SInst_qi <"any8", int_hexagon_C2_any8>;
2266
2267// CR / Logical operations on predicates.
2268def Hexagon_C2_pxfer_map:
2269 qi_SInst_qi_pxfer <"", int_hexagon_C2_pxfer_map>;
2270def Hexagon_C2_and:
2271 qi_SInst_qiqi <"and", int_hexagon_C2_and>;
2272def Hexagon_C2_andn:
2273 qi_SInst_qiqi_neg <"and", int_hexagon_C2_andn>;
2274def Hexagon_C2_not:
2275 qi_SInst_qi <"not", int_hexagon_C2_not>;
2276def Hexagon_C2_or:
2277 qi_SInst_qiqi <"or", int_hexagon_C2_or>;
2278def Hexagon_C2_orn:
2279 qi_SInst_qiqi_neg <"or", int_hexagon_C2_orn>;
2280def Hexagon_C2_xor:
2281 qi_SInst_qiqi <"xor", int_hexagon_C2_xor>;
2282
2283
2284/********************************************************************
2285* MTYPE/ALU *
2286*********************************************************************/
2287
2288// MTYPE / ALU / Add and accumulate.
2289def Hexagon_M2_acci:
2290 si_MInst_sisisi_acc <"add", int_hexagon_M2_acci>;
2291def Hexagon_M2_accii:
2292 si_MInst_sisis8_acc <"add", int_hexagon_M2_accii>;
2293def Hexagon_M2_nacci:
2294 si_MInst_sisisi_nac <"add", int_hexagon_M2_nacci>;
2295def Hexagon_M2_naccii:
2296 si_MInst_sisis8_nac <"add", int_hexagon_M2_naccii>;
2297
2298// MTYPE / ALU / Subtract and accumulate.
2299def Hexagon_M2_subacc:
2300 si_MInst_sisisi_acc <"sub", int_hexagon_M2_subacc>;
2301
2302// MTYPE / ALU / Vector absolute difference.
2303def Hexagon_M2_vabsdiffh:
2304 di_MInst_didi <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
2305def Hexagon_M2_vabsdiffw:
2306 di_MInst_didi <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
2307
2308// MTYPE / ALU / XOR and xor with destination.
2309def Hexagon_M2_xor_xacc:
2310 si_MInst_sisisi_xacc <"xor", int_hexagon_M2_xor_xacc>;
2311
2312
2313/********************************************************************
2314* MTYPE/COMPLEX *
2315*********************************************************************/
2316
2317// MTYPE / COMPLEX / Complex multiply.
2318// Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
2319def Hexagon_M2_cmpys_s1:
2320 di_MInst_sisi_s1_sat <"cmpy", int_hexagon_M2_cmpys_s1>;
2321def Hexagon_M2_cmpys_s0:
2322 di_MInst_sisi_sat <"cmpy", int_hexagon_M2_cmpys_s0>;
2323def Hexagon_M2_cmpysc_s1:
2324 di_MInst_sisi_s1_sat_conj <"cmpy", int_hexagon_M2_cmpysc_s1>;
2325def Hexagon_M2_cmpysc_s0:
2326 di_MInst_sisi_sat_conj <"cmpy", int_hexagon_M2_cmpysc_s0>;
2327
2328def Hexagon_M2_cmacs_s1:
2329 di_MInst_disisi_acc_s1_sat <"cmpy", int_hexagon_M2_cmacs_s1>;
2330def Hexagon_M2_cmacs_s0:
2331 di_MInst_disisi_acc_sat <"cmpy", int_hexagon_M2_cmacs_s0>;
2332def Hexagon_M2_cmacsc_s1:
2333 di_MInst_disisi_acc_s1_sat_conj <"cmpy", int_hexagon_M2_cmacsc_s1>;
2334def Hexagon_M2_cmacsc_s0:
2335 di_MInst_disisi_acc_sat_conj <"cmpy", int_hexagon_M2_cmacsc_s0>;
2336
2337def Hexagon_M2_cnacs_s1:
2338 di_MInst_disisi_nac_s1_sat <"cmpy", int_hexagon_M2_cnacs_s1>;
2339def Hexagon_M2_cnacs_s0:
2340 di_MInst_disisi_nac_sat <"cmpy", int_hexagon_M2_cnacs_s0>;
2341def Hexagon_M2_cnacsc_s1:
2342 di_MInst_disisi_nac_s1_sat_conj <"cmpy", int_hexagon_M2_cnacsc_s1>;
2343def Hexagon_M2_cnacsc_s0:
2344 di_MInst_disisi_nac_sat_conj <"cmpy", int_hexagon_M2_cnacsc_s0>;
2345
2346// MTYPE / COMPLEX / Complex multiply real or imaginary.
2347def Hexagon_M2_cmpyr_s0:
2348 di_MInst_sisi <"cmpyr", int_hexagon_M2_cmpyr_s0>;
2349def Hexagon_M2_cmacr_s0:
2350 di_MInst_disisi_acc <"cmpyr", int_hexagon_M2_cmacr_s0>;
2351
2352def Hexagon_M2_cmpyi_s0:
2353 di_MInst_sisi <"cmpyi", int_hexagon_M2_cmpyi_s0>;
2354def Hexagon_M2_cmaci_s0:
2355 di_MInst_disisi_acc <"cmpyi", int_hexagon_M2_cmaci_s0>;
2356
2357// MTYPE / COMPLEX / Complex multiply with round and pack.
2358// Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
2359def Hexagon_M2_cmpyrs_s0:
2360 si_MInst_sisi_rnd_sat <"cmpy", int_hexagon_M2_cmpyrs_s0>;
2361def Hexagon_M2_cmpyrs_s1:
2362 si_MInst_sisi_s1_rnd_sat <"cmpy", int_hexagon_M2_cmpyrs_s1>;
2363
2364def Hexagon_M2_cmpyrsc_s0:
2365 si_MInst_sisi_rnd_sat_conj <"cmpy", int_hexagon_M2_cmpyrsc_s0>;
2366def Hexagon_M2_cmpyrsc_s1:
2367 si_MInst_sisi_s1_rnd_sat_conj <"cmpy", int_hexagon_M2_cmpyrsc_s1>;
2368
2369//MTYPE / COMPLEX / Vector complex multiply real or imaginary.
2370def Hexagon_M2_vcmpy_s0_sat_i:
2371 di_MInst_didi_sat <"vcmpyi", int_hexagon_M2_vcmpy_s0_sat_i>;
2372def Hexagon_M2_vcmpy_s1_sat_i:
2373 di_MInst_didi_s1_sat <"vcmpyi", int_hexagon_M2_vcmpy_s1_sat_i>;
2374
2375def Hexagon_M2_vcmpy_s0_sat_r:
2376 di_MInst_didi_sat <"vcmpyr", int_hexagon_M2_vcmpy_s0_sat_r>;
2377def Hexagon_M2_vcmpy_s1_sat_r:
2378 di_MInst_didi_s1_sat <"vcmpyr", int_hexagon_M2_vcmpy_s1_sat_r>;
2379
2380def Hexagon_M2_vcmac_s0_sat_i:
2381 di_MInst_dididi_acc_sat <"vcmpyi", int_hexagon_M2_vcmac_s0_sat_i>;
2382def Hexagon_M2_vcmac_s0_sat_r:
2383 di_MInst_dididi_acc_sat <"vcmpyr", int_hexagon_M2_vcmac_s0_sat_r>;
2384
2385//MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
2386def Hexagon_M2_vrcmpyi_s0:
2387 di_MInst_didi <"vrcmpyi", int_hexagon_M2_vrcmpyi_s0>;
2388def Hexagon_M2_vrcmpyr_s0:
2389 di_MInst_didi <"vrcmpyr", int_hexagon_M2_vrcmpyr_s0>;
2390
2391def Hexagon_M2_vrcmpyi_s0c:
2392 di_MInst_didi_conj <"vrcmpyi", int_hexagon_M2_vrcmpyi_s0c>;
2393def Hexagon_M2_vrcmpyr_s0c:
2394 di_MInst_didi_conj <"vrcmpyr", int_hexagon_M2_vrcmpyr_s0c>;
2395
2396def Hexagon_M2_vrcmaci_s0:
2397 di_MInst_dididi_acc <"vrcmpyi", int_hexagon_M2_vrcmaci_s0>;
2398def Hexagon_M2_vrcmacr_s0:
2399 di_MInst_dididi_acc <"vrcmpyr", int_hexagon_M2_vrcmacr_s0>;
2400
2401def Hexagon_M2_vrcmaci_s0c:
2402 di_MInst_dididi_acc_conj <"vrcmpyi", int_hexagon_M2_vrcmaci_s0c>;
2403def Hexagon_M2_vrcmacr_s0c:
2404 di_MInst_dididi_acc_conj <"vrcmpyr", int_hexagon_M2_vrcmacr_s0c>;
2405
2406
2407/********************************************************************
2408* MTYPE/MPYH *
2409*********************************************************************/
2410
2411// MTYPE / MPYH / Multiply and use lower result.
2412//def Hexagon_M2_mpysmi:
2413// si_MInst_sim9 <"mpyi", int_hexagon_M2_mpysmi>;
2414def Hexagon_M2_mpyi:
2415 si_MInst_sisi <"mpyi", int_hexagon_M2_mpyi>;
2416def Hexagon_M2_mpyui:
2417 si_MInst_sisi <"mpyui", int_hexagon_M2_mpyui>;
2418def Hexagon_M2_macsip:
2419 si_MInst_sisiu8_acc <"mpyi", int_hexagon_M2_macsip>;
2420def Hexagon_M2_maci:
2421 si_MInst_sisisi_acc <"mpyi", int_hexagon_M2_maci>;
2422def Hexagon_M2_macsin:
2423 si_MInst_sisiu8_nac <"mpyi", int_hexagon_M2_macsin>;
2424
2425// MTYPE / MPYH / Multiply word by half (32x16).
2426//Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
2427//Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
2428def Hexagon_M2_mmpyl_rs1:
2429 di_MInst_didi_s1_rnd_sat <"vmpyweh", int_hexagon_M2_mmpyl_rs1>;
2430def Hexagon_M2_mmpyl_s1:
2431 di_MInst_didi_s1_sat <"vmpyweh", int_hexagon_M2_mmpyl_s1>;
2432def Hexagon_M2_mmpyl_rs0:
2433 di_MInst_didi_rnd_sat <"vmpyweh", int_hexagon_M2_mmpyl_rs0>;
2434def Hexagon_M2_mmpyl_s0:
2435 di_MInst_didi_sat <"vmpyweh", int_hexagon_M2_mmpyl_s0>;
2436def Hexagon_M2_mmpyh_rs1:
2437 di_MInst_didi_s1_rnd_sat <"vmpywoh", int_hexagon_M2_mmpyh_rs1>;
2438def Hexagon_M2_mmpyh_s1:
2439 di_MInst_didi_s1_sat <"vmpywoh", int_hexagon_M2_mmpyh_s1>;
2440def Hexagon_M2_mmpyh_rs0:
2441 di_MInst_didi_rnd_sat <"vmpywoh", int_hexagon_M2_mmpyh_rs0>;
2442def Hexagon_M2_mmpyh_s0:
2443 di_MInst_didi_sat <"vmpywoh", int_hexagon_M2_mmpyh_s0>;
2444def Hexagon_M2_mmacls_rs1:
2445 di_MInst_dididi_acc_s1_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs1>;
2446def Hexagon_M2_mmacls_s1:
2447 di_MInst_dididi_acc_s1_sat <"vmpyweh", int_hexagon_M2_mmacls_s1>;
2448def Hexagon_M2_mmacls_rs0:
2449 di_MInst_dididi_acc_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs0>;
2450def Hexagon_M2_mmacls_s0:
2451 di_MInst_dididi_acc_sat <"vmpyweh", int_hexagon_M2_mmacls_s0>;
2452def Hexagon_M2_mmachs_rs1:
2453 di_MInst_dididi_acc_s1_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs1>;
2454def Hexagon_M2_mmachs_s1:
2455 di_MInst_dididi_acc_s1_sat <"vmpywoh", int_hexagon_M2_mmachs_s1>;
2456def Hexagon_M2_mmachs_rs0:
2457 di_MInst_dididi_acc_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs0>;
2458def Hexagon_M2_mmachs_s0:
2459 di_MInst_dididi_acc_sat <"vmpywoh", int_hexagon_M2_mmachs_s0>;
2460
2461// MTYPE / MPYH / Multiply word by unsigned half (32x16).
2462//Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
2463//Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
2464def Hexagon_M2_mmpyul_rs1:
2465 di_MInst_didi_s1_rnd_sat <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
2466def Hexagon_M2_mmpyul_s1:
2467 di_MInst_didi_s1_sat <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
2468def Hexagon_M2_mmpyul_rs0:
2469 di_MInst_didi_rnd_sat <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
2470def Hexagon_M2_mmpyul_s0:
2471 di_MInst_didi_sat <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
2472def Hexagon_M2_mmpyuh_rs1:
2473 di_MInst_didi_s1_rnd_sat <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
2474def Hexagon_M2_mmpyuh_s1:
2475 di_MInst_didi_s1_sat <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
2476def Hexagon_M2_mmpyuh_rs0:
2477 di_MInst_didi_rnd_sat <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
2478def Hexagon_M2_mmpyuh_s0:
2479 di_MInst_didi_sat <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
2480def Hexagon_M2_mmaculs_rs1:
2481 di_MInst_dididi_acc_s1_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
2482def Hexagon_M2_mmaculs_s1:
2483 di_MInst_dididi_acc_s1_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
2484def Hexagon_M2_mmaculs_rs0:
2485 di_MInst_dididi_acc_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
2486def Hexagon_M2_mmaculs_s0:
2487 di_MInst_dididi_acc_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
2488def Hexagon_M2_mmacuhs_rs1:
2489 di_MInst_dididi_acc_s1_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
2490def Hexagon_M2_mmacuhs_s1:
2491 di_MInst_dididi_acc_s1_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
2492def Hexagon_M2_mmacuhs_rs0:
2493 di_MInst_dididi_acc_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
2494def Hexagon_M2_mmacuhs_s0:
2495 di_MInst_dididi_acc_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
2496
2497// MTYPE / MPYH / Multiply and use upper result.
2498def Hexagon_M2_hmmpyh_rs1:
2499 si_MInst_sisi_h_s1_rnd_sat <"mpy", int_hexagon_M2_hmmpyh_rs1>;
2500def Hexagon_M2_hmmpyl_rs1:
2501 si_MInst_sisi_l_s1_rnd_sat <"mpy", int_hexagon_M2_hmmpyl_rs1>;
2502def Hexagon_M2_mpy_up:
2503 si_MInst_sisi <"mpy", int_hexagon_M2_mpy_up>;
2504def Hexagon_M2_dpmpyss_rnd_s0:
2505 si_MInst_sisi_rnd <"mpy", int_hexagon_M2_dpmpyss_rnd_s0>;
2506def Hexagon_M2_mpyu_up:
2507 si_MInst_sisi <"mpyu", int_hexagon_M2_mpyu_up>;
2508
2509// MTYPE / MPYH / Multiply and use full result.
2510def Hexagon_M2_dpmpyuu_s0:
2511 di_MInst_sisi <"mpyu", int_hexagon_M2_dpmpyuu_s0>;
2512def Hexagon_M2_dpmpyuu_acc_s0:
2513 di_MInst_disisi_acc <"mpyu", int_hexagon_M2_dpmpyuu_acc_s0>;
2514def Hexagon_M2_dpmpyuu_nac_s0:
2515 di_MInst_disisi_nac <"mpyu", int_hexagon_M2_dpmpyuu_nac_s0>;
2516def Hexagon_M2_dpmpyss_s0:
2517 di_MInst_sisi <"mpy", int_hexagon_M2_dpmpyss_s0>;
2518def Hexagon_M2_dpmpyss_acc_s0:
2519 di_MInst_disisi_acc <"mpy", int_hexagon_M2_dpmpyss_acc_s0>;
2520def Hexagon_M2_dpmpyss_nac_s0:
2521 di_MInst_disisi_nac <"mpy", int_hexagon_M2_dpmpyss_nac_s0>;
2522
2523
2524/********************************************************************
2525* MTYPE/MPYS *
2526*********************************************************************/
2527
2528// MTYPE / MPYS / Scalar 16x16 multiply signed.
2529//Rd=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]|
2530// [:<<0[:rnd|:sat|:rnd:sat]|:<<1[:rnd|:sat|:rnd:sat]]]
2531def Hexagon_M2_mpy_hh_s0:
2532 si_MInst_sisi_hh <"mpy", int_hexagon_M2_mpy_hh_s0>;
2533def Hexagon_M2_mpy_hh_s1:
2534 si_MInst_sisi_hh_s1 <"mpy", int_hexagon_M2_mpy_hh_s1>;
2535def Hexagon_M2_mpy_rnd_hh_s1:
2536 si_MInst_sisi_rnd_hh_s1 <"mpy", int_hexagon_M2_mpy_rnd_hh_s1>;
2537def Hexagon_M2_mpy_sat_rnd_hh_s1:
2538 si_MInst_sisi_sat_rnd_hh_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_hh_s1>;
2539def Hexagon_M2_mpy_sat_hh_s1:
2540 si_MInst_sisi_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_sat_hh_s1>;
2541def Hexagon_M2_mpy_rnd_hh_s0:
2542 si_MInst_sisi_rnd_hh <"mpy", int_hexagon_M2_mpy_rnd_hh_s0>;
2543def Hexagon_M2_mpy_sat_rnd_hh_s0:
2544 si_MInst_sisi_sat_rnd_hh <"mpy", int_hexagon_M2_mpy_sat_rnd_hh_s0>;
2545def Hexagon_M2_mpy_sat_hh_s0:
2546 si_MInst_sisi_sat_hh <"mpy", int_hexagon_M2_mpy_sat_hh_s0>;
2547
2548def Hexagon_M2_mpy_hl_s0:
2549 si_MInst_sisi_hl <"mpy", int_hexagon_M2_mpy_hl_s0>;
2550def Hexagon_M2_mpy_hl_s1:
2551 si_MInst_sisi_hl_s1 <"mpy", int_hexagon_M2_mpy_hl_s1>;
2552def Hexagon_M2_mpy_rnd_hl_s1:
2553 si_MInst_sisi_rnd_hl_s1 <"mpy", int_hexagon_M2_mpy_rnd_hl_s1>;
2554def Hexagon_M2_mpy_sat_rnd_hl_s1:
2555 si_MInst_sisi_sat_rnd_hl_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_hl_s1>;
2556def Hexagon_M2_mpy_sat_hl_s1:
2557 si_MInst_sisi_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_sat_hl_s1>;
2558def Hexagon_M2_mpy_rnd_hl_s0:
2559 si_MInst_sisi_rnd_hl <"mpy", int_hexagon_M2_mpy_rnd_hl_s0>;
2560def Hexagon_M2_mpy_sat_rnd_hl_s0:
2561 si_MInst_sisi_sat_rnd_hl <"mpy", int_hexagon_M2_mpy_sat_rnd_hl_s0>;
2562def Hexagon_M2_mpy_sat_hl_s0:
2563 si_MInst_sisi_sat_hl <"mpy", int_hexagon_M2_mpy_sat_hl_s0>;
2564
2565def Hexagon_M2_mpy_lh_s0:
2566 si_MInst_sisi_lh <"mpy", int_hexagon_M2_mpy_lh_s0>;
2567def Hexagon_M2_mpy_lh_s1:
2568 si_MInst_sisi_lh_s1 <"mpy", int_hexagon_M2_mpy_lh_s1>;
2569def Hexagon_M2_mpy_rnd_lh_s1:
2570 si_MInst_sisi_rnd_lh_s1 <"mpy", int_hexagon_M2_mpy_rnd_lh_s1>;
2571def Hexagon_M2_mpy_sat_rnd_lh_s1:
2572 si_MInst_sisi_sat_rnd_lh_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_lh_s1>;
2573def Hexagon_M2_mpy_sat_lh_s1:
2574 si_MInst_sisi_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_sat_lh_s1>;
2575def Hexagon_M2_mpy_rnd_lh_s0:
2576 si_MInst_sisi_rnd_lh <"mpy", int_hexagon_M2_mpy_rnd_lh_s0>;
2577def Hexagon_M2_mpy_sat_rnd_lh_s0:
2578 si_MInst_sisi_sat_rnd_lh <"mpy", int_hexagon_M2_mpy_sat_rnd_lh_s0>;
2579def Hexagon_M2_mpy_sat_lh_s0:
2580 si_MInst_sisi_sat_lh <"mpy", int_hexagon_M2_mpy_sat_lh_s0>;
2581
2582def Hexagon_M2_mpy_ll_s0:
2583 si_MInst_sisi_ll <"mpy", int_hexagon_M2_mpy_ll_s0>;
2584def Hexagon_M2_mpy_ll_s1:
2585 si_MInst_sisi_ll_s1 <"mpy", int_hexagon_M2_mpy_ll_s1>;
2586def Hexagon_M2_mpy_rnd_ll_s1:
2587 si_MInst_sisi_rnd_ll_s1 <"mpy", int_hexagon_M2_mpy_rnd_ll_s1>;
2588def Hexagon_M2_mpy_sat_rnd_ll_s1:
2589 si_MInst_sisi_sat_rnd_ll_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_ll_s1>;
2590def Hexagon_M2_mpy_sat_ll_s1:
2591 si_MInst_sisi_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_sat_ll_s1>;
2592def Hexagon_M2_mpy_rnd_ll_s0:
2593 si_MInst_sisi_rnd_ll <"mpy", int_hexagon_M2_mpy_rnd_ll_s0>;
2594def Hexagon_M2_mpy_sat_rnd_ll_s0:
2595 si_MInst_sisi_sat_rnd_ll <"mpy", int_hexagon_M2_mpy_sat_rnd_ll_s0>;
2596def Hexagon_M2_mpy_sat_ll_s0:
2597 si_MInst_sisi_sat_ll <"mpy", int_hexagon_M2_mpy_sat_ll_s0>;
2598
2599//Rdd=mpy(Rs.[H|L],Rt.[H|L])[[:<<0|:<<1]|[:<<0:rnd|:<<1:rnd]]
2600def Hexagon_M2_mpyd_hh_s0:
2601 di_MInst_sisi_hh <"mpy", int_hexagon_M2_mpyd_hh_s0>;
2602def Hexagon_M2_mpyd_hh_s1:
2603 di_MInst_sisi_hh_s1 <"mpy", int_hexagon_M2_mpyd_hh_s1>;
2604def Hexagon_M2_mpyd_rnd_hh_s1:
2605 di_MInst_sisi_rnd_hh_s1 <"mpy", int_hexagon_M2_mpyd_rnd_hh_s1>;
2606def Hexagon_M2_mpyd_rnd_hh_s0:
2607 di_MInst_sisi_rnd_hh <"mpy", int_hexagon_M2_mpyd_rnd_hh_s0>;
2608
2609def Hexagon_M2_mpyd_hl_s0:
2610 di_MInst_sisi_hl <"mpy", int_hexagon_M2_mpyd_hl_s0>;
2611def Hexagon_M2_mpyd_hl_s1:
2612 di_MInst_sisi_hl_s1 <"mpy", int_hexagon_M2_mpyd_hl_s1>;
2613def Hexagon_M2_mpyd_rnd_hl_s1:
2614 di_MInst_sisi_rnd_hl_s1 <"mpy", int_hexagon_M2_mpyd_rnd_hl_s1>;
2615def Hexagon_M2_mpyd_rnd_hl_s0:
2616 di_MInst_sisi_rnd_hl <"mpy", int_hexagon_M2_mpyd_rnd_hl_s0>;
2617
2618def Hexagon_M2_mpyd_lh_s0:
2619 di_MInst_sisi_lh <"mpy", int_hexagon_M2_mpyd_lh_s0>;
2620def Hexagon_M2_mpyd_lh_s1:
2621 di_MInst_sisi_lh_s1 <"mpy", int_hexagon_M2_mpyd_lh_s1>;
2622def Hexagon_M2_mpyd_rnd_lh_s1:
2623 di_MInst_sisi_rnd_lh_s1 <"mpy", int_hexagon_M2_mpyd_rnd_lh_s1>;
2624def Hexagon_M2_mpyd_rnd_lh_s0:
2625 di_MInst_sisi_rnd_lh <"mpy", int_hexagon_M2_mpyd_rnd_lh_s0>;
2626
2627def Hexagon_M2_mpyd_ll_s0:
2628 di_MInst_sisi_ll <"mpy", int_hexagon_M2_mpyd_ll_s0>;
2629def Hexagon_M2_mpyd_ll_s1:
2630 di_MInst_sisi_ll_s1 <"mpy", int_hexagon_M2_mpyd_ll_s1>;
2631def Hexagon_M2_mpyd_rnd_ll_s1:
2632 di_MInst_sisi_rnd_ll_s1 <"mpy", int_hexagon_M2_mpyd_rnd_ll_s1>;
2633def Hexagon_M2_mpyd_rnd_ll_s0:
2634 di_MInst_sisi_rnd_ll <"mpy", int_hexagon_M2_mpyd_rnd_ll_s0>;
2635
2636//Rx+=mpy(Rs.[H|L],Rt.[H|L])[[[:<<0|:<<1]|[:<<0:sat|:<<1:sat]]
2637def Hexagon_M2_mpy_acc_hh_s0:
2638 si_MInst_sisisi_acc_hh <"mpy", int_hexagon_M2_mpy_acc_hh_s0>;
2639def Hexagon_M2_mpy_acc_hh_s1:
2640 si_MInst_sisisi_acc_hh_s1 <"mpy", int_hexagon_M2_mpy_acc_hh_s1>;
2641def Hexagon_M2_mpy_acc_sat_hh_s1:
2642 si_MInst_sisisi_acc_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_hh_s1>;
2643def Hexagon_M2_mpy_acc_sat_hh_s0:
2644 si_MInst_sisisi_acc_sat_hh <"mpy", int_hexagon_M2_mpy_acc_sat_hh_s0>;
2645
2646def Hexagon_M2_mpy_acc_hl_s0:
2647 si_MInst_sisisi_acc_hl <"mpy", int_hexagon_M2_mpy_acc_hl_s0>;
2648def Hexagon_M2_mpy_acc_hl_s1:
2649 si_MInst_sisisi_acc_hl_s1 <"mpy", int_hexagon_M2_mpy_acc_hl_s1>;
2650def Hexagon_M2_mpy_acc_sat_hl_s1:
2651 si_MInst_sisisi_acc_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_hl_s1>;
2652def Hexagon_M2_mpy_acc_sat_hl_s0:
2653 si_MInst_sisisi_acc_sat_hl <"mpy", int_hexagon_M2_mpy_acc_sat_hl_s0>;
2654
2655def Hexagon_M2_mpy_acc_lh_s0:
2656 si_MInst_sisisi_acc_lh <"mpy", int_hexagon_M2_mpy_acc_lh_s0>;
2657def Hexagon_M2_mpy_acc_lh_s1:
2658 si_MInst_sisisi_acc_lh_s1 <"mpy", int_hexagon_M2_mpy_acc_lh_s1>;
2659def Hexagon_M2_mpy_acc_sat_lh_s1:
2660 si_MInst_sisisi_acc_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_lh_s1>;
2661def Hexagon_M2_mpy_acc_sat_lh_s0:
2662 si_MInst_sisisi_acc_sat_lh <"mpy", int_hexagon_M2_mpy_acc_sat_lh_s0>;
2663
2664def Hexagon_M2_mpy_acc_ll_s0:
2665 si_MInst_sisisi_acc_ll <"mpy", int_hexagon_M2_mpy_acc_ll_s0>;
2666def Hexagon_M2_mpy_acc_ll_s1:
2667 si_MInst_sisisi_acc_ll_s1 <"mpy", int_hexagon_M2_mpy_acc_ll_s1>;
2668def Hexagon_M2_mpy_acc_sat_ll_s1:
2669 si_MInst_sisisi_acc_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_ll_s1>;
2670def Hexagon_M2_mpy_acc_sat_ll_s0:
2671 si_MInst_sisisi_acc_sat_ll <"mpy", int_hexagon_M2_mpy_acc_sat_ll_s0>;
2672
2673//Rx-=mpy(Rs.[H|L],Rt.[H|L])[[[:<<0|:<<1]|[:<<0:sat|:<<1:sat]]
2674def Hexagon_M2_mpy_nac_hh_s0:
2675 si_MInst_sisisi_nac_hh <"mpy", int_hexagon_M2_mpy_nac_hh_s0>;
2676def Hexagon_M2_mpy_nac_hh_s1:
2677 si_MInst_sisisi_nac_hh_s1 <"mpy", int_hexagon_M2_mpy_nac_hh_s1>;
2678def Hexagon_M2_mpy_nac_sat_hh_s1:
2679 si_MInst_sisisi_nac_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_hh_s1>;
2680def Hexagon_M2_mpy_nac_sat_hh_s0:
2681 si_MInst_sisisi_nac_sat_hh <"mpy", int_hexagon_M2_mpy_nac_sat_hh_s0>;
2682
2683def Hexagon_M2_mpy_nac_hl_s0:
2684 si_MInst_sisisi_nac_hl <"mpy", int_hexagon_M2_mpy_nac_hl_s0>;
2685def Hexagon_M2_mpy_nac_hl_s1:
2686 si_MInst_sisisi_nac_hl_s1 <"mpy", int_hexagon_M2_mpy_nac_hl_s1>;
2687def Hexagon_M2_mpy_nac_sat_hl_s1:
2688 si_MInst_sisisi_nac_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_hl_s1>;
2689def Hexagon_M2_mpy_nac_sat_hl_s0:
2690 si_MInst_sisisi_nac_sat_hl <"mpy", int_hexagon_M2_mpy_nac_sat_hl_s0>;
2691
2692def Hexagon_M2_mpy_nac_lh_s0:
2693 si_MInst_sisisi_nac_lh <"mpy", int_hexagon_M2_mpy_nac_lh_s0>;
2694def Hexagon_M2_mpy_nac_lh_s1:
2695 si_MInst_sisisi_nac_lh_s1 <"mpy", int_hexagon_M2_mpy_nac_lh_s1>;
2696def Hexagon_M2_mpy_nac_sat_lh_s1:
2697 si_MInst_sisisi_nac_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_lh_s1>;
2698def Hexagon_M2_mpy_nac_sat_lh_s0:
2699 si_MInst_sisisi_nac_sat_lh <"mpy", int_hexagon_M2_mpy_nac_sat_lh_s0>;
2700
2701def Hexagon_M2_mpy_nac_ll_s0:
2702 si_MInst_sisisi_nac_ll <"mpy", int_hexagon_M2_mpy_nac_ll_s0>;
2703def Hexagon_M2_mpy_nac_ll_s1:
2704 si_MInst_sisisi_nac_ll_s1 <"mpy", int_hexagon_M2_mpy_nac_ll_s1>;
2705def Hexagon_M2_mpy_nac_sat_ll_s1:
2706 si_MInst_sisisi_nac_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_ll_s1>;
2707def Hexagon_M2_mpy_nac_sat_ll_s0:
2708 si_MInst_sisisi_nac_sat_ll <"mpy", int_hexagon_M2_mpy_nac_sat_ll_s0>;
2709
2710//Rx+=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]
2711def Hexagon_M2_mpyd_acc_hh_s0:
2712 di_MInst_disisi_acc_hh <"mpy", int_hexagon_M2_mpyd_acc_hh_s0>;
2713def Hexagon_M2_mpyd_acc_hh_s1:
2714 di_MInst_disisi_acc_hh_s1 <"mpy", int_hexagon_M2_mpyd_acc_hh_s1>;
2715
2716def Hexagon_M2_mpyd_acc_hl_s0:
2717 di_MInst_disisi_acc_hl <"mpy", int_hexagon_M2_mpyd_acc_hl_s0>;
2718def Hexagon_M2_mpyd_acc_hl_s1:
2719 di_MInst_disisi_acc_hl_s1 <"mpy", int_hexagon_M2_mpyd_acc_hl_s1>;
2720
2721def Hexagon_M2_mpyd_acc_lh_s0:
2722 di_MInst_disisi_acc_lh <"mpy", int_hexagon_M2_mpyd_acc_lh_s0>;
2723def Hexagon_M2_mpyd_acc_lh_s1:
2724 di_MInst_disisi_acc_lh_s1 <"mpy", int_hexagon_M2_mpyd_acc_lh_s1>;
2725
2726def Hexagon_M2_mpyd_acc_ll_s0:
2727 di_MInst_disisi_acc_ll <"mpy", int_hexagon_M2_mpyd_acc_ll_s0>;
2728def Hexagon_M2_mpyd_acc_ll_s1:
2729 di_MInst_disisi_acc_ll_s1 <"mpy", int_hexagon_M2_mpyd_acc_ll_s1>;
2730
2731//Rx-=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]
2732def Hexagon_M2_mpyd_nac_hh_s0:
2733 di_MInst_disisi_nac_hh <"mpy", int_hexagon_M2_mpyd_nac_hh_s0>;
2734def Hexagon_M2_mpyd_nac_hh_s1:
2735 di_MInst_disisi_nac_hh_s1 <"mpy", int_hexagon_M2_mpyd_nac_hh_s1>;
2736
2737def Hexagon_M2_mpyd_nac_hl_s0:
2738 di_MInst_disisi_nac_hl <"mpy", int_hexagon_M2_mpyd_nac_hl_s0>;
2739def Hexagon_M2_mpyd_nac_hl_s1:
2740 di_MInst_disisi_nac_hl_s1 <"mpy", int_hexagon_M2_mpyd_nac_hl_s1>;
2741
2742def Hexagon_M2_mpyd_nac_lh_s0:
2743 di_MInst_disisi_nac_lh <"mpy", int_hexagon_M2_mpyd_nac_lh_s0>;
2744def Hexagon_M2_mpyd_nac_lh_s1:
2745 di_MInst_disisi_nac_lh_s1 <"mpy", int_hexagon_M2_mpyd_nac_lh_s1>;
2746
2747def Hexagon_M2_mpyd_nac_ll_s0:
2748 di_MInst_disisi_nac_ll <"mpy", int_hexagon_M2_mpyd_nac_ll_s0>;
2749def Hexagon_M2_mpyd_nac_ll_s1:
2750 di_MInst_disisi_nac_ll_s1 <"mpy", int_hexagon_M2_mpyd_nac_ll_s1>;
2751
2752// MTYPE / MPYS / Scalar 16x16 multiply unsigned.
2753//Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2754def Hexagon_M2_mpyu_hh_s0:
2755 si_MInst_sisi_hh <"mpyu", int_hexagon_M2_mpyu_hh_s0>;
2756def Hexagon_M2_mpyu_hh_s1:
2757 si_MInst_sisi_hh_s1 <"mpyu", int_hexagon_M2_mpyu_hh_s1>;
2758def Hexagon_M2_mpyu_hl_s0:
2759 si_MInst_sisi_hl <"mpyu", int_hexagon_M2_mpyu_hl_s0>;
2760def Hexagon_M2_mpyu_hl_s1:
2761 si_MInst_sisi_hl_s1 <"mpyu", int_hexagon_M2_mpyu_hl_s1>;
2762def Hexagon_M2_mpyu_lh_s0:
2763 si_MInst_sisi_lh <"mpyu", int_hexagon_M2_mpyu_lh_s0>;
2764def Hexagon_M2_mpyu_lh_s1:
2765 si_MInst_sisi_lh_s1 <"mpyu", int_hexagon_M2_mpyu_lh_s1>;
2766def Hexagon_M2_mpyu_ll_s0:
2767 si_MInst_sisi_ll <"mpyu", int_hexagon_M2_mpyu_ll_s0>;
2768def Hexagon_M2_mpyu_ll_s1:
2769 si_MInst_sisi_ll_s1 <"mpyu", int_hexagon_M2_mpyu_ll_s1>;
2770
2771//Rdd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2772def Hexagon_M2_mpyud_hh_s0:
2773 di_MInst_sisi_hh <"mpyu", int_hexagon_M2_mpyud_hh_s0>;
2774def Hexagon_M2_mpyud_hh_s1:
2775 di_MInst_sisi_hh_s1 <"mpyu", int_hexagon_M2_mpyud_hh_s1>;
2776def Hexagon_M2_mpyud_hl_s0:
2777 di_MInst_sisi_hl <"mpyu", int_hexagon_M2_mpyud_hl_s0>;
2778def Hexagon_M2_mpyud_hl_s1:
2779 di_MInst_sisi_hl_s1 <"mpyu", int_hexagon_M2_mpyud_hl_s1>;
2780def Hexagon_M2_mpyud_lh_s0:
2781 di_MInst_sisi_lh <"mpyu", int_hexagon_M2_mpyud_lh_s0>;
2782def Hexagon_M2_mpyud_lh_s1:
2783 di_MInst_sisi_lh_s1 <"mpyu", int_hexagon_M2_mpyud_lh_s1>;
2784def Hexagon_M2_mpyud_ll_s0:
2785 di_MInst_sisi_ll <"mpyu", int_hexagon_M2_mpyud_ll_s0>;
2786def Hexagon_M2_mpyud_ll_s1:
2787 di_MInst_sisi_ll_s1 <"mpyu", int_hexagon_M2_mpyud_ll_s1>;
2788
2789//Rd+=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2790def Hexagon_M2_mpyu_acc_hh_s0:
2791 si_MInst_sisisi_acc_hh <"mpyu", int_hexagon_M2_mpyu_acc_hh_s0>;
2792def Hexagon_M2_mpyu_acc_hh_s1:
2793 si_MInst_sisisi_acc_hh_s1 <"mpyu", int_hexagon_M2_mpyu_acc_hh_s1>;
2794def Hexagon_M2_mpyu_acc_hl_s0:
2795 si_MInst_sisisi_acc_hl <"mpyu", int_hexagon_M2_mpyu_acc_hl_s0>;
2796def Hexagon_M2_mpyu_acc_hl_s1:
2797 si_MInst_sisisi_acc_hl_s1 <"mpyu", int_hexagon_M2_mpyu_acc_hl_s1>;
2798def Hexagon_M2_mpyu_acc_lh_s0:
2799 si_MInst_sisisi_acc_lh <"mpyu", int_hexagon_M2_mpyu_acc_lh_s0>;
2800def Hexagon_M2_mpyu_acc_lh_s1:
2801 si_MInst_sisisi_acc_lh_s1 <"mpyu", int_hexagon_M2_mpyu_acc_lh_s1>;
2802def Hexagon_M2_mpyu_acc_ll_s0:
2803 si_MInst_sisisi_acc_ll <"mpyu", int_hexagon_M2_mpyu_acc_ll_s0>;
2804def Hexagon_M2_mpyu_acc_ll_s1:
2805 si_MInst_sisisi_acc_ll_s1 <"mpyu", int_hexagon_M2_mpyu_acc_ll_s1>;
2806
2807//Rd+=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2808def Hexagon_M2_mpyu_nac_hh_s0:
2809 si_MInst_sisisi_nac_hh <"mpyu", int_hexagon_M2_mpyu_nac_hh_s0>;
2810def Hexagon_M2_mpyu_nac_hh_s1:
2811 si_MInst_sisisi_nac_hh_s1 <"mpyu", int_hexagon_M2_mpyu_nac_hh_s1>;
2812def Hexagon_M2_mpyu_nac_hl_s0:
2813 si_MInst_sisisi_nac_hl <"mpyu", int_hexagon_M2_mpyu_nac_hl_s0>;
2814def Hexagon_M2_mpyu_nac_hl_s1:
2815 si_MInst_sisisi_nac_hl_s1 <"mpyu", int_hexagon_M2_mpyu_nac_hl_s1>;
2816def Hexagon_M2_mpyu_nac_lh_s0:
2817 si_MInst_sisisi_nac_lh <"mpyu", int_hexagon_M2_mpyu_nac_lh_s0>;
2818def Hexagon_M2_mpyu_nac_lh_s1:
2819 si_MInst_sisisi_nac_lh_s1 <"mpyu", int_hexagon_M2_mpyu_nac_lh_s1>;
2820def Hexagon_M2_mpyu_nac_ll_s0:
2821 si_MInst_sisisi_nac_ll <"mpyu", int_hexagon_M2_mpyu_nac_ll_s0>;
2822def Hexagon_M2_mpyu_nac_ll_s1:
2823 si_MInst_sisisi_nac_ll_s1 <"mpyu", int_hexagon_M2_mpyu_nac_ll_s1>;
2824
2825//Rdd+=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2826def Hexagon_M2_mpyud_acc_hh_s0:
2827 di_MInst_disisi_acc_hh <"mpyu", int_hexagon_M2_mpyud_acc_hh_s0>;
2828def Hexagon_M2_mpyud_acc_hh_s1:
2829 di_MInst_disisi_acc_hh_s1 <"mpyu", int_hexagon_M2_mpyud_acc_hh_s1>;
2830def Hexagon_M2_mpyud_acc_hl_s0:
2831 di_MInst_disisi_acc_hl <"mpyu", int_hexagon_M2_mpyud_acc_hl_s0>;
2832def Hexagon_M2_mpyud_acc_hl_s1:
2833 di_MInst_disisi_acc_hl_s1 <"mpyu", int_hexagon_M2_mpyud_acc_hl_s1>;
2834def Hexagon_M2_mpyud_acc_lh_s0:
2835 di_MInst_disisi_acc_lh <"mpyu", int_hexagon_M2_mpyud_acc_lh_s0>;
2836def Hexagon_M2_mpyud_acc_lh_s1:
2837 di_MInst_disisi_acc_lh_s1 <"mpyu", int_hexagon_M2_mpyud_acc_lh_s1>;
2838def Hexagon_M2_mpyud_acc_ll_s0:
2839 di_MInst_disisi_acc_ll <"mpyu", int_hexagon_M2_mpyud_acc_ll_s0>;
2840def Hexagon_M2_mpyud_acc_ll_s1:
2841 di_MInst_disisi_acc_ll_s1 <"mpyu", int_hexagon_M2_mpyud_acc_ll_s1>;
2842
2843//Rdd-=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2844def Hexagon_M2_mpyud_nac_hh_s0:
2845 di_MInst_disisi_nac_hh <"mpyu", int_hexagon_M2_mpyud_nac_hh_s0>;
2846def Hexagon_M2_mpyud_nac_hh_s1:
2847 di_MInst_disisi_nac_hh_s1 <"mpyu", int_hexagon_M2_mpyud_nac_hh_s1>;
2848def Hexagon_M2_mpyud_nac_hl_s0:
2849 di_MInst_disisi_nac_hl <"mpyu", int_hexagon_M2_mpyud_nac_hl_s0>;
2850def Hexagon_M2_mpyud_nac_hl_s1:
2851 di_MInst_disisi_nac_hl_s1 <"mpyu", int_hexagon_M2_mpyud_nac_hl_s1>;
2852def Hexagon_M2_mpyud_nac_lh_s0:
2853 di_MInst_disisi_nac_lh <"mpyu", int_hexagon_M2_mpyud_nac_lh_s0>;
2854def Hexagon_M2_mpyud_nac_lh_s1:
2855 di_MInst_disisi_nac_lh_s1 <"mpyu", int_hexagon_M2_mpyud_nac_lh_s1>;
2856def Hexagon_M2_mpyud_nac_ll_s0:
2857 di_MInst_disisi_nac_ll <"mpyu", int_hexagon_M2_mpyud_nac_ll_s0>;
2858def Hexagon_M2_mpyud_nac_ll_s1:
2859 di_MInst_disisi_nac_ll_s1 <"mpyu", int_hexagon_M2_mpyud_nac_ll_s1>;
2860
2861
2862/********************************************************************
2863* MTYPE/VB *
2864*********************************************************************/
2865
2866// MTYPE / VB / Vector reduce add unsigned bytes.
2867def Hexagon_A2_vraddub:
2868 di_MInst_didi <"vraddub", int_hexagon_A2_vraddub>;
2869def Hexagon_A2_vraddub_acc:
2870 di_MInst_dididi_acc <"vraddub", int_hexagon_A2_vraddub_acc>;
2871
2872// MTYPE / VB / Vector sum of absolute differences unsigned bytes.
2873def Hexagon_A2_vrsadub:
2874 di_MInst_didi <"vrsadub", int_hexagon_A2_vrsadub>;
2875def Hexagon_A2_vrsadub_acc:
2876 di_MInst_dididi_acc <"vrsadub", int_hexagon_A2_vrsadub_acc>;
2877
2878/********************************************************************
2879* MTYPE/VH *
2880*********************************************************************/
2881
2882// MTYPE / VH / Vector dual multiply.
2883def Hexagon_M2_vdmpys_s1:
2884 di_MInst_didi_s1_sat <"vdmpy", int_hexagon_M2_vdmpys_s1>;
2885def Hexagon_M2_vdmpys_s0:
2886 di_MInst_didi_sat <"vdmpy", int_hexagon_M2_vdmpys_s0>;
2887def Hexagon_M2_vdmacs_s1:
2888 di_MInst_dididi_acc_s1_sat <"vdmpy", int_hexagon_M2_vdmacs_s1>;
2889def Hexagon_M2_vdmacs_s0:
2890 di_MInst_dididi_acc_sat <"vdmpy", int_hexagon_M2_vdmacs_s0>;
2891
2892// MTYPE / VH / Vector dual multiply with round and pack.
2893def Hexagon_M2_vdmpyrs_s0:
2894 si_MInst_didi_rnd_sat <"vdmpy", int_hexagon_M2_vdmpyrs_s0>;
2895def Hexagon_M2_vdmpyrs_s1:
2896 si_MInst_didi_s1_rnd_sat <"vdmpy", int_hexagon_M2_vdmpyrs_s1>;
2897
2898// MTYPE / VH / Vector multiply even halfwords.
2899def Hexagon_M2_vmpy2es_s1:
2900 di_MInst_didi_s1_sat <"vmpyeh", int_hexagon_M2_vmpy2es_s1>;
2901def Hexagon_M2_vmpy2es_s0:
2902 di_MInst_didi_sat <"vmpyeh", int_hexagon_M2_vmpy2es_s0>;
2903def Hexagon_M2_vmac2es:
2904 di_MInst_dididi_acc <"vmpyeh", int_hexagon_M2_vmac2es>;
2905def Hexagon_M2_vmac2es_s1:
2906 di_MInst_dididi_acc_s1_sat <"vmpyeh", int_hexagon_M2_vmac2es_s1>;
2907def Hexagon_M2_vmac2es_s0:
2908 di_MInst_dididi_acc_sat <"vmpyeh", int_hexagon_M2_vmac2es_s0>;
2909
2910// MTYPE / VH / Vector multiply halfwords.
2911def Hexagon_M2_vmpy2s_s0:
2912 di_MInst_sisi_sat <"vmpyh", int_hexagon_M2_vmpy2s_s0>;
2913def Hexagon_M2_vmpy2s_s1:
2914 di_MInst_sisi_s1_sat <"vmpyh", int_hexagon_M2_vmpy2s_s1>;
2915def Hexagon_M2_vmac2:
2916 di_MInst_disisi_acc <"vmpyh", int_hexagon_M2_vmac2>;
2917def Hexagon_M2_vmac2s_s0:
2918 di_MInst_disisi_acc_sat <"vmpyh", int_hexagon_M2_vmac2s_s0>;
2919def Hexagon_M2_vmac2s_s1:
2920 di_MInst_disisi_acc_s1_sat <"vmpyh", int_hexagon_M2_vmac2s_s1>;
2921
2922// MTYPE / VH / Vector multiply halfwords with round and pack.
2923def Hexagon_M2_vmpy2s_s0pack:
2924 si_MInst_sisi_rnd_sat <"vmpyh", int_hexagon_M2_vmpy2s_s0pack>;
2925def Hexagon_M2_vmpy2s_s1pack:
2926 si_MInst_sisi_s1_rnd_sat <"vmpyh", int_hexagon_M2_vmpy2s_s1pack>;
2927
2928// MTYPE / VH / Vector reduce multiply halfwords.
2929// Rxx32+=vrmpyh(Rss32,Rtt32)
2930def Hexagon_M2_vrmpy_s0:
2931 di_MInst_didi <"vrmpyh", int_hexagon_M2_vrmpy_s0>;
2932def Hexagon_M2_vrmac_s0:
2933 di_MInst_dididi_acc <"vrmpyh", int_hexagon_M2_vrmac_s0>;
2934
2935
2936/********************************************************************
2937* STYPE/ALU *
2938*********************************************************************/
2939
2940// STYPE / ALU / Absolute value.
2941def Hexagon_A2_abs:
2942 si_SInst_si <"abs", int_hexagon_A2_abs>;
2943def Hexagon_A2_absp:
2944 di_SInst_di <"abs", int_hexagon_A2_absp>;
2945def Hexagon_A2_abssat:
2946 si_SInst_si_sat <"abs", int_hexagon_A2_abssat>;
2947
2948// STYPE / ALU / Negate.
2949def Hexagon_A2_negp:
2950 di_SInst_di <"neg", int_hexagon_A2_negp>;
2951def Hexagon_A2_negsat:
2952 si_SInst_si_sat <"neg", int_hexagon_A2_negsat>;
2953
2954// STYPE / ALU / Logical Not.
2955def Hexagon_A2_notp:
2956 di_SInst_di <"not", int_hexagon_A2_notp>;
2957
2958// STYPE / ALU / Sign extend word to doubleword.
2959def Hexagon_A2_sxtw:
2960 di_SInst_si <"sxtw", int_hexagon_A2_sxtw>;
2961
2962
2963/********************************************************************
2964* STYPE/BIT *
2965*********************************************************************/
2966
2967// STYPE / BIT / Count leading.
2968def Hexagon_S2_cl0:
2969 si_SInst_si <"cl0", int_hexagon_S2_cl0>;
2970def Hexagon_S2_cl0p:
2971 si_SInst_di <"cl0", int_hexagon_S2_cl0p>;
2972def Hexagon_S2_cl1:
2973 si_SInst_si <"cl1", int_hexagon_S2_cl1>;
2974def Hexagon_S2_cl1p:
2975 si_SInst_di <"cl1", int_hexagon_S2_cl1p>;
2976def Hexagon_S2_clb:
2977 si_SInst_si <"clb", int_hexagon_S2_clb>;
2978def Hexagon_S2_clbp:
2979 si_SInst_di <"clb", int_hexagon_S2_clbp>;
2980def Hexagon_S2_clbnorm:
2981 si_SInst_si <"normamt", int_hexagon_S2_clbnorm>;
2982
2983// STYPE / BIT / Count trailing.
2984def Hexagon_S2_ct0:
2985 si_SInst_si <"ct0", int_hexagon_S2_ct0>;
2986def Hexagon_S2_ct1:
2987 si_SInst_si <"ct1", int_hexagon_S2_ct1>;
2988
2989// STYPE / BIT / Compare bit mask.
2990def HEXAGON_C2_bitsclr:
2991 qi_SInst_sisi <"bitsclr", int_hexagon_C2_bitsclr>;
2992def HEXAGON_C2_bitsclri:
2993 qi_SInst_siu6 <"bitsclr", int_hexagon_C2_bitsclri>;
2994def HEXAGON_C2_bitsset:
2995 qi_SInst_sisi <"bitsset", int_hexagon_C2_bitsset>;
2996
2997// STYPE / BIT / Extract unsigned.
2998// Rd[d][32/64]=extractu(Rs[s],Rt[t],[imm])
2999def Hexagon_S2_extractu:
3000 si_SInst_siu5u5 <"extractu",int_hexagon_S2_extractu>;
3001def Hexagon_S2_extractu_rp:
3002 si_SInst_sidi <"extractu",int_hexagon_S2_extractu_rp>;
3003def Hexagon_S2_extractup:
3004 di_SInst_diu6u6 <"extractu",int_hexagon_S2_extractup>;
3005def Hexagon_S2_extractup_rp:
3006 di_SInst_didi <"extractu",int_hexagon_S2_extractup_rp>;
3007
3008// STYPE / BIT / Insert bitfield.
3009def HEXAGON_S2_insert:
3010 si_SInst_sisiu5u5 <"insert", int_hexagon_S2_insert>;
3011def HEXAGON_S2_insert_rp:
3012 si_SInst_sisidi <"insert", int_hexagon_S2_insert_rp>;
3013def HEXAGON_S2_insertp:
3014 di_SInst_didiu6u6 <"insert", int_hexagon_S2_insertp>;
3015def HEXAGON_S2_insertp_rp:
3016 di_SInst_dididi <"insert", int_hexagon_S2_insertp_rp>;
3017
3018// STYPE / BIT / Innterleave/deinterleave.
3019def HEXAGON_S2_interleave:
3020 di_SInst_di <"interleave", int_hexagon_S2_interleave>;
3021def HEXAGON_S2_deinterleave:
3022 di_SInst_di <"deinterleave", int_hexagon_S2_deinterleave>;
3023
3024// STYPE / BIT / Linear feedback-shift Iteration.
3025def HEXAGON_S2_lfsp:
3026 di_SInst_didi <"lfs", int_hexagon_S2_lfsp>;
3027
3028// STYPE / BIT / Bit reverse.
3029def HEXAGON_S2_brev:
3030 si_SInst_si <"brev", int_hexagon_S2_brev>;
3031
3032// STYPE / BIT / Set/Clear/Toggle Bit.
3033def Hexagon_S2_setbit_i:
3034 si_SInst_siu5 <"setbit", int_hexagon_S2_setbit_i>;
3035def Hexagon_S2_togglebit_i:
3036 si_SInst_siu5 <"togglebit", int_hexagon_S2_togglebit_i>;
3037def Hexagon_S2_clrbit_i:
3038 si_SInst_siu5 <"clrbit", int_hexagon_S2_clrbit_i>;
3039def Hexagon_S2_setbit_r:
3040 si_SInst_sisi <"setbit", int_hexagon_S2_setbit_r>;
3041def Hexagon_S2_togglebit_r:
3042 si_SInst_sisi <"togglebit", int_hexagon_S2_togglebit_r>;
3043def Hexagon_S2_clrbit_r:
3044 si_SInst_sisi <"clrbit", int_hexagon_S2_clrbit_r>;
3045
3046// STYPE / BIT / Test Bit.
3047def Hexagon_S2_tstbit_i:
3048 qi_SInst_siu5 <"tstbit", int_hexagon_S2_tstbit_i>;
3049def Hexagon_S2_tstbit_r:
3050 qi_SInst_sisi <"tstbit", int_hexagon_S2_tstbit_r>;
3051
3052
3053/********************************************************************
3054* STYPE/COMPLEX *
3055*********************************************************************/
3056
3057// STYPE / COMPLEX / Vector Complex conjugate.
3058def Hexagon_A2_vconj:
3059 di_SInst_di_sat <"vconj", int_hexagon_A2_vconj>;
3060
3061// STYPE / COMPLEX / Vector Complex rotate.
3062def Hexagon_S2_vcrotate:
3063 di_SInst_disi <"vcrotate",int_hexagon_S2_vcrotate>;
3064
3065
3066/********************************************************************
3067* STYPE/PERM *
3068*********************************************************************/
3069
3070// STYPE / PERM / Saturate.
3071def Hexagon_A2_sat:
3072 si_SInst_di <"sat", int_hexagon_A2_sat>;
3073def Hexagon_A2_satb:
3074 si_SInst_si <"satb", int_hexagon_A2_satb>;
3075def Hexagon_A2_sath:
3076 si_SInst_si <"sath", int_hexagon_A2_sath>;
3077def Hexagon_A2_satub:
3078 si_SInst_si <"satub", int_hexagon_A2_satub>;
3079def Hexagon_A2_satuh:
3080 si_SInst_si <"satuh", int_hexagon_A2_satuh>;
3081
3082// STYPE / PERM / Swizzle bytes.
3083def Hexagon_A2_swiz:
3084 si_SInst_si <"swiz", int_hexagon_A2_swiz>;
3085
3086// STYPE / PERM / Vector align.
3087// Need custom lowering
3088def Hexagon_S2_valignib:
3089 di_SInst_didiu3 <"valignb", int_hexagon_S2_valignib>;
3090def Hexagon_S2_valignrb:
3091 di_SInst_didiqi <"valignb", int_hexagon_S2_valignrb>;
3092
3093// STYPE / PERM / Vector round and pack.
3094def Hexagon_S2_vrndpackwh:
3095 si_SInst_di <"vrndwh", int_hexagon_S2_vrndpackwh>;
3096def Hexagon_S2_vrndpackwhs:
3097 si_SInst_di_sat <"vrndwh", int_hexagon_S2_vrndpackwhs>;
3098
3099// STYPE / PERM / Vector saturate and pack.
3100def Hexagon_S2_svsathb:
3101 si_SInst_si <"vsathb", int_hexagon_S2_svsathb>;
3102def Hexagon_S2_vsathb:
3103 si_SInst_di <"vsathb", int_hexagon_S2_vsathb>;
3104def Hexagon_S2_svsathub:
3105 si_SInst_si <"vsathub", int_hexagon_S2_svsathub>;
3106def Hexagon_S2_vsathub:
3107 si_SInst_di <"vsathub", int_hexagon_S2_vsathub>;
3108def Hexagon_S2_vsatwh:
3109 si_SInst_di <"vsatwh", int_hexagon_S2_vsatwh>;
3110def Hexagon_S2_vsatwuh:
3111 si_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh>;
3112
3113// STYPE / PERM / Vector saturate without pack.
3114def Hexagon_S2_vsathb_nopack:
3115 di_SInst_di <"vsathb", int_hexagon_S2_vsathb_nopack>;
3116def Hexagon_S2_vsathub_nopack:
3117 di_SInst_di <"vsathub", int_hexagon_S2_vsathub_nopack>;
3118def Hexagon_S2_vsatwh_nopack:
3119 di_SInst_di <"vsatwh", int_hexagon_S2_vsatwh_nopack>;
3120def Hexagon_S2_vsatwuh_nopack:
3121 di_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
3122
3123// STYPE / PERM / Vector shuffle.
3124def Hexagon_S2_shuffeb:
3125 di_SInst_didi <"shuffeb", int_hexagon_S2_shuffeb>;
3126def Hexagon_S2_shuffeh:
3127 di_SInst_didi <"shuffeh", int_hexagon_S2_shuffeh>;
3128def Hexagon_S2_shuffob:
3129 di_SInst_didi <"shuffob", int_hexagon_S2_shuffob>;
3130def Hexagon_S2_shuffoh:
3131 di_SInst_didi <"shuffoh", int_hexagon_S2_shuffoh>;
3132
3133// STYPE / PERM / Vector splat bytes.
3134def Hexagon_S2_vsplatrb:
3135 si_SInst_si <"vsplatb", int_hexagon_S2_vsplatrb>;
3136
3137// STYPE / PERM / Vector splat halfwords.
3138def Hexagon_S2_vsplatrh:
3139 di_SInst_si <"vsplath", int_hexagon_S2_vsplatrh>;
3140
3141// STYPE / PERM / Vector splice.
3142def HEXAGON_S2_vsplicerb:
3143 di_SInst_didiqi <"vspliceb",int_hexagon_S2_vsplicerb>;
3144def HEXAGON_S2_vspliceib:
3145 di_SInst_didiu3 <"vspliceb",int_hexagon_S2_vspliceib>;
3146
3147// STYPE / PERM / Sign extend.
3148def Hexagon_S2_vsxtbh:
3149 di_SInst_si <"vsxtbh", int_hexagon_S2_vsxtbh>;
3150def Hexagon_S2_vsxthw:
3151 di_SInst_si <"vsxthw", int_hexagon_S2_vsxthw>;
3152
3153// STYPE / PERM / Truncate.
3154def Hexagon_S2_vtrunehb:
3155 si_SInst_di <"vtrunehb",int_hexagon_S2_vtrunehb>;
3156def Hexagon_S2_vtrunohb:
3157 si_SInst_di <"vtrunohb",int_hexagon_S2_vtrunohb>;
3158def Hexagon_S2_vtrunewh:
3159 di_SInst_didi <"vtrunewh",int_hexagon_S2_vtrunewh>;
3160def Hexagon_S2_vtrunowh:
3161 di_SInst_didi <"vtrunowh",int_hexagon_S2_vtrunowh>;
3162
3163// STYPE / PERM / Zero extend.
3164def Hexagon_S2_vzxtbh:
3165 di_SInst_si <"vzxtbh", int_hexagon_S2_vzxtbh>;
3166def Hexagon_S2_vzxthw:
3167 di_SInst_si <"vzxthw", int_hexagon_S2_vzxthw>;
3168
3169
3170/********************************************************************
3171* STYPE/PRED *
3172*********************************************************************/
3173
3174// STYPE / PRED / Mask generate from predicate.
3175def Hexagon_C2_mask:
3176 di_SInst_qi <"mask", int_hexagon_C2_mask>;
3177
3178// STYPE / PRED / Predicate transfer.
3179def Hexagon_C2_tfrpr:
3180 si_SInst_qi <"", int_hexagon_C2_tfrpr>;
3181def Hexagon_C2_tfrrp:
3182 qi_SInst_si <"", int_hexagon_C2_tfrrp>;
3183
3184// STYPE / PRED / Viterbi pack even and odd predicate bits.
3185def Hexagon_C2_vitpack:
3186 si_SInst_qiqi <"vitpack",int_hexagon_C2_vitpack>;
3187
3188
3189/********************************************************************
3190* STYPE/SHIFT *
3191*********************************************************************/
3192
3193// STYPE / SHIFT / Shift by immediate.
3194def Hexagon_S2_asl_i_r:
3195 si_SInst_siu5 <"asl", int_hexagon_S2_asl_i_r>;
3196def Hexagon_S2_asr_i_r:
3197 si_SInst_siu5 <"asr", int_hexagon_S2_asr_i_r>;
3198def Hexagon_S2_lsr_i_r:
3199 si_SInst_siu5 <"lsr", int_hexagon_S2_lsr_i_r>;
3200def Hexagon_S2_asl_i_p:
3201 di_SInst_diu6 <"asl", int_hexagon_S2_asl_i_p>;
3202def Hexagon_S2_asr_i_p:
3203 di_SInst_diu6 <"asr", int_hexagon_S2_asr_i_p>;
3204def Hexagon_S2_lsr_i_p:
3205 di_SInst_diu6 <"lsr", int_hexagon_S2_lsr_i_p>;
3206
3207// STYPE / SHIFT / Shift by immediate and accumulate.
3208def Hexagon_S2_asl_i_r_acc:
3209 si_SInst_sisiu5_acc <"asl", int_hexagon_S2_asl_i_r_acc>;
3210def Hexagon_S2_asr_i_r_acc:
3211 si_SInst_sisiu5_acc <"asr", int_hexagon_S2_asr_i_r_acc>;
3212def Hexagon_S2_lsr_i_r_acc:
3213 si_SInst_sisiu5_acc <"lsr", int_hexagon_S2_lsr_i_r_acc>;
3214def Hexagon_S2_asl_i_r_nac:
3215 si_SInst_sisiu5_nac <"asl", int_hexagon_S2_asl_i_r_nac>;
3216def Hexagon_S2_asr_i_r_nac:
3217 si_SInst_sisiu5_nac <"asr", int_hexagon_S2_asr_i_r_nac>;
3218def Hexagon_S2_lsr_i_r_nac:
3219 si_SInst_sisiu5_nac <"lsr", int_hexagon_S2_lsr_i_r_nac>;
3220def Hexagon_S2_asl_i_p_acc:
3221 di_SInst_didiu6_acc <"asl", int_hexagon_S2_asl_i_p_acc>;
3222def Hexagon_S2_asr_i_p_acc:
3223 di_SInst_didiu6_acc <"asr", int_hexagon_S2_asr_i_p_acc>;
3224def Hexagon_S2_lsr_i_p_acc:
3225 di_SInst_didiu6_acc <"lsr", int_hexagon_S2_lsr_i_p_acc>;
3226def Hexagon_S2_asl_i_p_nac:
3227 di_SInst_didiu6_nac <"asl", int_hexagon_S2_asl_i_p_nac>;
3228def Hexagon_S2_asr_i_p_nac:
3229 di_SInst_didiu6_nac <"asr", int_hexagon_S2_asr_i_p_nac>;
3230def Hexagon_S2_lsr_i_p_nac:
3231 di_SInst_didiu6_nac <"lsr", int_hexagon_S2_lsr_i_p_nac>;
3232
3233// STYPE / SHIFT / Shift by immediate and add.
3234def Hexagon_S2_addasl_rrri:
3235 si_SInst_sisiu3 <"addasl", int_hexagon_S2_addasl_rrri>;
3236
3237// STYPE / SHIFT / Shift by immediate and logical.
3238def Hexagon_S2_asl_i_r_and:
3239 si_SInst_sisiu5_and <"asl", int_hexagon_S2_asl_i_r_and>;
3240def Hexagon_S2_asr_i_r_and:
3241 si_SInst_sisiu5_and <"asr", int_hexagon_S2_asr_i_r_and>;
3242def Hexagon_S2_lsr_i_r_and:
3243 si_SInst_sisiu5_and <"lsr", int_hexagon_S2_lsr_i_r_and>;
3244
3245def Hexagon_S2_asl_i_r_xacc:
3246 si_SInst_sisiu5_xor <"asl", int_hexagon_S2_asl_i_r_xacc>;
3247def Hexagon_S2_lsr_i_r_xacc:
3248 si_SInst_sisiu5_xor <"lsr", int_hexagon_S2_lsr_i_r_xacc>;
3249
3250def Hexagon_S2_asl_i_r_or:
3251 si_SInst_sisiu5_or <"asl", int_hexagon_S2_asl_i_r_or>;
3252def Hexagon_S2_asr_i_r_or:
3253 si_SInst_sisiu5_or <"asr", int_hexagon_S2_asr_i_r_or>;
3254def Hexagon_S2_lsr_i_r_or:
3255 si_SInst_sisiu5_or <"lsr", int_hexagon_S2_lsr_i_r_or>;
3256
3257def Hexagon_S2_asl_i_p_and:
3258 di_SInst_didiu6_and <"asl", int_hexagon_S2_asl_i_p_and>;
3259def Hexagon_S2_asr_i_p_and:
3260 di_SInst_didiu6_and <"asr", int_hexagon_S2_asr_i_p_and>;
3261def Hexagon_S2_lsr_i_p_and:
3262 di_SInst_didiu6_and <"lsr", int_hexagon_S2_lsr_i_p_and>;
3263
3264def Hexagon_S2_asl_i_p_xacc:
3265 di_SInst_didiu6_xor <"asl", int_hexagon_S2_asl_i_p_xacc>;
3266def Hexagon_S2_lsr_i_p_xacc:
3267 di_SInst_didiu6_xor <"lsr", int_hexagon_S2_lsr_i_p_xacc>;
3268
3269def Hexagon_S2_asl_i_p_or:
3270 di_SInst_didiu6_or <"asl", int_hexagon_S2_asl_i_p_or>;
3271def Hexagon_S2_asr_i_p_or:
3272 di_SInst_didiu6_or <"asr", int_hexagon_S2_asr_i_p_or>;
3273def Hexagon_S2_lsr_i_p_or:
3274 di_SInst_didiu6_or <"lsr", int_hexagon_S2_lsr_i_p_or>;
3275
3276// STYPE / SHIFT / Shift right by immediate with rounding.
3277def Hexagon_S2_asr_i_r_rnd:
3278 si_SInst_siu5_rnd <"asr", int_hexagon_S2_asr_i_r_rnd>;
3279def Hexagon_S2_asr_i_r_rnd_goodsyntax:
3280 si_SInst_siu5 <"asrrnd", int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
3281
3282// STYPE / SHIFT / Shift left by immediate with saturation.
3283def Hexagon_S2_asl_i_r_sat:
3284 si_SInst_sisi_sat <"asl", int_hexagon_S2_asl_i_r_sat>;
3285
3286// STYPE / SHIFT / Shift by register.
3287def Hexagon_S2_asl_r_r:
3288 si_SInst_sisi <"asl", int_hexagon_S2_asl_r_r>;
3289def Hexagon_S2_asr_r_r:
3290 si_SInst_sisi <"asr", int_hexagon_S2_asr_r_r>;
3291def Hexagon_S2_lsl_r_r:
3292 si_SInst_sisi <"lsl", int_hexagon_S2_lsl_r_r>;
3293def Hexagon_S2_lsr_r_r:
3294 si_SInst_sisi <"lsr", int_hexagon_S2_lsr_r_r>;
3295def Hexagon_S2_asl_r_p:
3296 di_SInst_disi <"asl", int_hexagon_S2_asl_r_p>;
3297def Hexagon_S2_asr_r_p:
3298 di_SInst_disi <"asr", int_hexagon_S2_asr_r_p>;
3299def Hexagon_S2_lsl_r_p:
3300 di_SInst_disi <"lsl", int_hexagon_S2_lsl_r_p>;
3301def Hexagon_S2_lsr_r_p:
3302 di_SInst_disi <"lsr", int_hexagon_S2_lsr_r_p>;
3303
3304// STYPE / SHIFT / Shift by register and accumulate.
3305def Hexagon_S2_asl_r_r_acc:
3306 si_SInst_sisisi_acc <"asl", int_hexagon_S2_asl_r_r_acc>;
3307def Hexagon_S2_asr_r_r_acc:
3308 si_SInst_sisisi_acc <"asr", int_hexagon_S2_asr_r_r_acc>;
3309def Hexagon_S2_lsl_r_r_acc:
3310 si_SInst_sisisi_acc <"lsl", int_hexagon_S2_lsl_r_r_acc>;
3311def Hexagon_S2_lsr_r_r_acc:
3312 si_SInst_sisisi_acc <"lsr", int_hexagon_S2_lsr_r_r_acc>;
3313def Hexagon_S2_asl_r_p_acc:
3314 di_SInst_didisi_acc <"asl", int_hexagon_S2_asl_r_p_acc>;
3315def Hexagon_S2_asr_r_p_acc:
3316 di_SInst_didisi_acc <"asr", int_hexagon_S2_asr_r_p_acc>;
3317def Hexagon_S2_lsl_r_p_acc:
3318 di_SInst_didisi_acc <"lsl", int_hexagon_S2_lsl_r_p_acc>;
3319def Hexagon_S2_lsr_r_p_acc:
3320 di_SInst_didisi_acc <"lsr", int_hexagon_S2_lsr_r_p_acc>;
3321
3322def Hexagon_S2_asl_r_r_nac:
3323 si_SInst_sisisi_nac <"asl", int_hexagon_S2_asl_r_r_nac>;
3324def Hexagon_S2_asr_r_r_nac:
3325 si_SInst_sisisi_nac <"asr", int_hexagon_S2_asr_r_r_nac>;
3326def Hexagon_S2_lsl_r_r_nac:
3327 si_SInst_sisisi_nac <"lsl", int_hexagon_S2_lsl_r_r_nac>;
3328def Hexagon_S2_lsr_r_r_nac:
3329 si_SInst_sisisi_nac <"lsr", int_hexagon_S2_lsr_r_r_nac>;
3330def Hexagon_S2_asl_r_p_nac:
3331 di_SInst_didisi_nac <"asl", int_hexagon_S2_asl_r_p_nac>;
3332def Hexagon_S2_asr_r_p_nac:
3333 di_SInst_didisi_nac <"asr", int_hexagon_S2_asr_r_p_nac>;
3334def Hexagon_S2_lsl_r_p_nac:
3335 di_SInst_didisi_nac <"lsl", int_hexagon_S2_lsl_r_p_nac>;
3336def Hexagon_S2_lsr_r_p_nac:
3337 di_SInst_didisi_nac <"lsr", int_hexagon_S2_lsr_r_p_nac>;
3338
3339// STYPE / SHIFT / Shift by register and logical.
3340def Hexagon_S2_asl_r_r_and:
3341 si_SInst_sisisi_and <"asl", int_hexagon_S2_asl_r_r_and>;
3342def Hexagon_S2_asr_r_r_and:
3343 si_SInst_sisisi_and <"asr", int_hexagon_S2_asr_r_r_and>;
3344def Hexagon_S2_lsl_r_r_and:
3345 si_SInst_sisisi_and <"lsl", int_hexagon_S2_lsl_r_r_and>;
3346def Hexagon_S2_lsr_r_r_and:
3347 si_SInst_sisisi_and <"lsr", int_hexagon_S2_lsr_r_r_and>;
3348
3349def Hexagon_S2_asl_r_r_or:
3350 si_SInst_sisisi_or <"asl", int_hexagon_S2_asl_r_r_or>;
3351def Hexagon_S2_asr_r_r_or:
3352 si_SInst_sisisi_or <"asr", int_hexagon_S2_asr_r_r_or>;
3353def Hexagon_S2_lsl_r_r_or:
3354 si_SInst_sisisi_or <"lsl", int_hexagon_S2_lsl_r_r_or>;
3355def Hexagon_S2_lsr_r_r_or:
3356 si_SInst_sisisi_or <"lsr", int_hexagon_S2_lsr_r_r_or>;
3357
3358def Hexagon_S2_asl_r_p_and:
3359 di_SInst_didisi_and <"asl", int_hexagon_S2_asl_r_p_and>;
3360def Hexagon_S2_asr_r_p_and:
3361 di_SInst_didisi_and <"asr", int_hexagon_S2_asr_r_p_and>;
3362def Hexagon_S2_lsl_r_p_and:
3363 di_SInst_didisi_and <"lsl", int_hexagon_S2_lsl_r_p_and>;
3364def Hexagon_S2_lsr_r_p_and:
3365 di_SInst_didisi_and <"lsr", int_hexagon_S2_lsr_r_p_and>;
3366
3367def Hexagon_S2_asl_r_p_or:
3368 di_SInst_didisi_or <"asl", int_hexagon_S2_asl_r_p_or>;
3369def Hexagon_S2_asr_r_p_or:
3370 di_SInst_didisi_or <"asr", int_hexagon_S2_asr_r_p_or>;
3371def Hexagon_S2_lsl_r_p_or:
3372 di_SInst_didisi_or <"lsl", int_hexagon_S2_lsl_r_p_or>;
3373def Hexagon_S2_lsr_r_p_or:
3374 di_SInst_didisi_or <"lsr", int_hexagon_S2_lsr_r_p_or>;
3375
3376// STYPE / SHIFT / Shift by register with saturation.
3377def Hexagon_S2_asl_r_r_sat:
3378 si_SInst_sisi_sat <"asl", int_hexagon_S2_asl_r_r_sat>;
3379def Hexagon_S2_asr_r_r_sat:
3380 si_SInst_sisi_sat <"asr", int_hexagon_S2_asr_r_r_sat>;
3381
3382// STYPE / SHIFT / Table Index.
3383def HEXAGON_S2_tableidxb_goodsyntax:
3384 si_MInst_sisiu4u5 <"tableidxb",int_hexagon_S2_tableidxb_goodsyntax>;
3385def HEXAGON_S2_tableidxd_goodsyntax:
3386 si_MInst_sisiu4u5 <"tableidxd",int_hexagon_S2_tableidxd_goodsyntax>;
3387def HEXAGON_S2_tableidxh_goodsyntax:
3388 si_MInst_sisiu4u5 <"tableidxh",int_hexagon_S2_tableidxh_goodsyntax>;
3389def HEXAGON_S2_tableidxw_goodsyntax:
3390 si_MInst_sisiu4u5 <"tableidxw",int_hexagon_S2_tableidxw_goodsyntax>;
3391
3392
3393/********************************************************************
3394* STYPE/VH *
3395*********************************************************************/
3396
3397// STYPE / VH / Vector absolute value halfwords.
3398// Rdd64=vabsh(Rss64)
3399def Hexagon_A2_vabsh:
3400 di_SInst_di <"vabsh", int_hexagon_A2_vabsh>;
3401def Hexagon_A2_vabshsat:
3402 di_SInst_di_sat <"vabsh", int_hexagon_A2_vabshsat>;
3403
3404// STYPE / VH / Vector shift halfwords by immediate.
3405// Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
3406def Hexagon_S2_asl_i_vh:
3407 di_SInst_disi <"vaslh", int_hexagon_S2_asl_i_vh>;
3408def Hexagon_S2_asr_i_vh:
3409 di_SInst_disi <"vasrh", int_hexagon_S2_asr_i_vh>;
3410def Hexagon_S2_lsr_i_vh:
3411 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_i_vh>;
3412
3413// STYPE / VH / Vector shift halfwords by register.
3414// Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
3415def Hexagon_S2_asl_r_vh:
3416 di_SInst_disi <"vaslh", int_hexagon_S2_asl_r_vh>;
3417def Hexagon_S2_asr_r_vh:
3418 di_SInst_disi <"vasrh", int_hexagon_S2_asr_r_vh>;
3419def Hexagon_S2_lsl_r_vh:
3420 di_SInst_disi <"vlslh", int_hexagon_S2_lsl_r_vh>;
3421def Hexagon_S2_lsr_r_vh:
3422 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_r_vh>;
3423
3424
3425/********************************************************************
3426* STYPE/VW *
3427*********************************************************************/
3428
3429// STYPE / VW / Vector absolute value words.
3430def Hexagon_A2_vabsw:
3431 di_SInst_di <"vabsw", int_hexagon_A2_vabsw>;
3432def Hexagon_A2_vabswsat:
3433 di_SInst_di_sat <"vabsw", int_hexagon_A2_vabswsat>;
3434
3435// STYPE / VW / Vector shift words by immediate.
3436// Rdd64=v[asl/vsl]w(Rss64,Rt32)
3437def Hexagon_S2_asl_i_vw:
3438 di_SInst_disi <"vaslw", int_hexagon_S2_asl_i_vw>;
3439def Hexagon_S2_asr_i_vw:
3440 di_SInst_disi <"vasrw", int_hexagon_S2_asr_i_vw>;
3441def Hexagon_S2_lsr_i_vw:
3442 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_i_vw>;
3443
3444// STYPE / VW / Vector shift words by register.
3445// Rdd64=v[asl/vsl]w(Rss64,Rt32)
3446def Hexagon_S2_asl_r_vw:
3447 di_SInst_disi <"vaslw", int_hexagon_S2_asl_r_vw>;
3448def Hexagon_S2_asr_r_vw:
3449 di_SInst_disi <"vasrw", int_hexagon_S2_asr_r_vw>;
3450def Hexagon_S2_lsl_r_vw:
3451 di_SInst_disi <"vlslw", int_hexagon_S2_lsl_r_vw>;
3452def Hexagon_S2_lsr_r_vw:
3453 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_r_vw>;
3454
3455// STYPE / VW / Vector shift words with truncate and pack.
3456def Hexagon_S2_asr_r_svw_trun:
3457 si_SInst_disi <"vasrw", int_hexagon_S2_asr_r_svw_trun>;
3458def Hexagon_S2_asr_i_svw_trun:
3459 si_SInst_diu5 <"vasrw", int_hexagon_S2_asr_i_svw_trun>;
3460
3461include "HexagonIntrinsicsV3.td"
3462include "HexagonIntrinsicsV4.td"