Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 334c26473bba3ad8b88341bb0d25d0ac2008bb8d / . / lib / Target / ARM / ARMBaseInstrInfo.h
blob: f263967dfb091aeb2b7b69ead3244b045137c7b4 [file] [log] [blame]
David Goodwin334c2642009-07-08 16:09:28 +0000[diff] [blame^]1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information -------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "ARMRegisterInfo.h"
19#include "ARM.h"
20
21namespace llvm {
22 class ARMSubtarget;
23
24/// ARMII - This namespace holds all of the target specific flags that
25/// instruction info tracks.
26///
27namespace ARMII {
28 enum {
29 //===------------------------------------------------------------------===//
30 // Instruction Flags.
31
32 //===------------------------------------------------------------------===//
33 // This four-bit field describes the addressing mode used.
34
35 AddrModeMask = 0xf,
36 AddrModeNone = 0,
37 AddrMode1 = 1,
38 AddrMode2 = 2,
39 AddrMode3 = 3,
40 AddrMode4 = 4,
41 AddrMode5 = 5,
42 AddrMode6 = 6,
43 AddrModeT1_1 = 7,
44 AddrModeT1_2 = 8,
45 AddrModeT1_4 = 9,
46 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
47 AddrModeT2_i12 = 11,
48 AddrModeT2_i8 = 12,
49 AddrModeT2_so = 13,
50 AddrModeT2_pc = 14, // +/- i12 for pc relative data
51 AddrModeT2_i8s4 = 15, // i8 * 4
52
53 // Size* - Flags to keep track of the size of an instruction.
54 SizeShift = 4,
55 SizeMask = 7 << SizeShift,
56 SizeSpecial = 1, // 0 byte pseudo or special case.
57 Size8Bytes = 2,
58 Size4Bytes = 3,
59 Size2Bytes = 4,
60
61 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
62 // and store ops
63 IndexModeShift = 7,
64 IndexModeMask = 3 << IndexModeShift,
65 IndexModePre = 1,
66 IndexModePost = 2,
67
68 //===------------------------------------------------------------------===//
69 // Instruction encoding formats.
70 //
71 FormShift = 9,
72 FormMask = 0x3f << FormShift,
73
74 // Pseudo instructions
75 Pseudo = 0 << FormShift,
76
77 // Multiply instructions
78 MulFrm = 1 << FormShift,
79
80 // Branch instructions
81 BrFrm = 2 << FormShift,
82 BrMiscFrm = 3 << FormShift,
83
84 // Data Processing instructions
85 DPFrm = 4 << FormShift,
86 DPSoRegFrm = 5 << FormShift,
87
88 // Load and Store
89 LdFrm = 6 << FormShift,
90 StFrm = 7 << FormShift,
91 LdMiscFrm = 8 << FormShift,
92 StMiscFrm = 9 << FormShift,
93 LdStMulFrm = 10 << FormShift,
94
95 // Miscellaneous arithmetic instructions
96 ArithMiscFrm = 11 << FormShift,
97
98 // Extend instructions
99 ExtFrm = 12 << FormShift,
100
101 // VFP formats
102 VFPUnaryFrm = 13 << FormShift,
103 VFPBinaryFrm = 14 << FormShift,
104 VFPConv1Frm = 15 << FormShift,
105 VFPConv2Frm = 16 << FormShift,
106 VFPConv3Frm = 17 << FormShift,
107 VFPConv4Frm = 18 << FormShift,
108 VFPConv5Frm = 19 << FormShift,
109 VFPLdStFrm = 20 << FormShift,
110 VFPLdStMulFrm = 21 << FormShift,
111 VFPMiscFrm = 22 << FormShift,
112
113 // Thumb format
114 ThumbFrm = 23 << FormShift,
115
116 // NEON format
117 NEONFrm = 24 << FormShift,
118 NEONGetLnFrm = 25 << FormShift,
119 NEONSetLnFrm = 26 << FormShift,
120 NEONDupFrm = 27 << FormShift,
121
122 //===------------------------------------------------------------------===//
123 // Misc flags.
124
125 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
126 // it doesn't have a Rn operand.
127 UnaryDP = 1 << 15,
128
129 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
130 // a 16-bit Thumb instruction if certain conditions are met.
131 Xform16Bit = 1 << 16,
132
133 //===------------------------------------------------------------------===//
134 // Field shifts - such shifts are used to set field while generating
135 // machine instructions.
136 M_BitShift = 5,
137 ShiftImmShift = 5,
138 ShiftShift = 7,
139 N_BitShift = 7,
140 ImmHiShift = 8,
141 SoRotImmShift = 8,
142 RegRsShift = 8,
143 ExtRotImmShift = 10,
144 RegRdLoShift = 12,
145 RegRdShift = 12,
146 RegRdHiShift = 16,
147 RegRnShift = 16,
148 S_BitShift = 20,
149 W_BitShift = 21,
150 AM3_I_BitShift = 22,
151 D_BitShift = 22,
152 U_BitShift = 23,
153 P_BitShift = 24,
154 I_BitShift = 25,
155 CondShift = 28
156 };
157
158 /// ARMII::Op - Holds all of the instruction types required by
159 /// target specific instruction and register code. ARMBaseInstrInfo
160 /// and subclasses should return a specific opcode that implements
161 /// the instruction type.
162 ///
163 enum Op {
164 ADDri,
165 ADDrs,
166 ADDrr,
167 B,
168 Bcc,
169 BR_JTr,
170 BR_JTm,
171 BR_JTadd,
172 FCPYS,
173 FCPYD,
174 FLDD,
175 FLDS,
176 FSTD,
177 FSTS,
178 LDR,
179 MOVr,
180 STR,
181 SUBri,
182 SUBrs,
183 SUBrr,
184 VMOVD,
185 VMOVQ
186 };
187}
188
189class ARMBaseInstrInfo : public TargetInstrInfoImpl {
190protected:
191 // Can be only subclassed.
192 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
193public:
194 // Return the non-pre/post incrementing version of 'Opc'. Return 0
195 // if there is not such an opcode.
196 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
197
198 // Return the opcode that implements 'Op', or 0 if no opcode
199 virtual unsigned getOpcode(ARMII::Op Op) const =0;
200
201 // Return true if the block does not fall through.
202 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0;
203
204 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
205 MachineBasicBlock::iterator &MBBI,
206 LiveVariables *LV) const;
207
208 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
209
210 // Branch analysis.
211 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
212 MachineBasicBlock *&FBB,
213 SmallVectorImpl<MachineOperand> &Cond,
214 bool AllowModify) const;
215 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
216 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
217 MachineBasicBlock *FBB,
218 const SmallVectorImpl<MachineOperand> &Cond) const;
219
220 virtual
221 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
222
223 // Predication support.
224 virtual bool isPredicated(const MachineInstr *MI) const;
225
226 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
227 int PIdx = MI->findFirstPredOperandIdx();
228 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
229 : ARMCC::AL;
230 }
231
232 virtual
233 bool PredicateInstruction(MachineInstr *MI,
234 const SmallVectorImpl<MachineOperand> &Pred) const;
235
236 virtual
237 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
238 const SmallVectorImpl<MachineOperand> &Pred2) const;
239
240 virtual bool DefinesPredicate(MachineInstr *MI,
241 std::vector<MachineOperand> &Pred) const;
242
243 /// GetInstSize - Returns the size of the specified MachineInstr.
244 ///
245 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
246
247 /// Return true if the instruction is a register to register move and return
248 /// the source and dest operands and their sub-register indices by reference.
249 virtual bool isMoveInstr(const MachineInstr &MI,
250 unsigned &SrcReg, unsigned &DstReg,
251 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
252
253 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
254 int &FrameIndex) const;
255 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
256 int &FrameIndex) const;
257
258 virtual bool copyRegToReg(MachineBasicBlock &MBB,
259 MachineBasicBlock::iterator I,
260 unsigned DestReg, unsigned SrcReg,
261 const TargetRegisterClass *DestRC,
262 const TargetRegisterClass *SrcRC) const;
263 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
264 MachineBasicBlock::iterator MBBI,
265 unsigned SrcReg, bool isKill, int FrameIndex,
266 const TargetRegisterClass *RC) const;
267
268 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
269 SmallVectorImpl<MachineOperand> &Addr,
270 const TargetRegisterClass *RC,
271 SmallVectorImpl<MachineInstr*> &NewMIs) const;
272
273 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
274 MachineBasicBlock::iterator MBBI,
275 unsigned DestReg, int FrameIndex,
276 const TargetRegisterClass *RC) const;
277
278 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
279 SmallVectorImpl<MachineOperand> &Addr,
280 const TargetRegisterClass *RC,
281 SmallVectorImpl<MachineInstr*> &NewMIs) const;
282
283 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
284 const SmallVectorImpl<unsigned> &Ops) const;
285
286 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
287 MachineInstr* MI,
288 const SmallVectorImpl<unsigned> &Ops,
289 int FrameIndex) const;
290
291 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
292 MachineInstr* MI,
293 const SmallVectorImpl<unsigned> &Ops,
294 MachineInstr* LoadMI) const;
295};
296}
297
298#endif