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Dan Gohmanf17a25c2007-07-18 16:29:46 +00001//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the pass which converts floating point instructions from
11// virtual registers into register stack instructions. This pass uses live
12// variable information to indicate where the FPn registers are used and their
13// lifetimes.
14//
15// This pass is hampered by the lack of decent CFG manipulation routines for
16// machine code. In particular, this wants to be able to split critical edges
17// as necessary, traverse the machine basic block CFG in depth-first order, and
18// allow there to be multiple machine basic blocks for each LLVM basicblock
19// (needed for critical edge splitting).
20//
21// In particular, this pass currently barfs on critical edges. Because of this,
22// it requires the instruction selector to insert FP_REG_KILL instructions on
23// the exits of any basic block that has critical edges going from it, or which
24// branch to a critical basic block.
25//
26// FIXME: this is not implemented yet. The stackifier pass only works on local
27// basic blocks.
28//
29//===----------------------------------------------------------------------===//
30
31#define DEBUG_TYPE "x86-codegen"
32#include "X86.h"
33#include "X86InstrInfo.h"
34#include "llvm/CodeGen/MachineFunctionPass.h"
35#include "llvm/CodeGen/MachineInstrBuilder.h"
36#include "llvm/CodeGen/LiveVariables.h"
37#include "llvm/CodeGen/Passes.h"
38#include "llvm/Target/TargetInstrInfo.h"
39#include "llvm/Target/TargetMachine.h"
40#include "llvm/Support/Debug.h"
41#include "llvm/Support/Compiler.h"
42#include "llvm/ADT/DepthFirstIterator.h"
43#include "llvm/ADT/SmallVector.h"
44#include "llvm/ADT/Statistic.h"
45#include "llvm/ADT/STLExtras.h"
46#include <algorithm>
47#include <set>
48using namespace llvm;
49
50STATISTIC(NumFXCH, "Number of fxch instructions inserted");
51STATISTIC(NumFP , "Number of floating point instructions");
52
53namespace {
54 struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
55 static char ID;
56 FPS() : MachineFunctionPass((intptr_t)&ID) {}
57
58 virtual bool runOnMachineFunction(MachineFunction &MF);
59
60 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
61
62 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
63 AU.addRequired<LiveVariables>();
64 MachineFunctionPass::getAnalysisUsage(AU);
65 }
66 private:
67 const TargetInstrInfo *TII; // Machine instruction info.
68 LiveVariables *LV; // Live variable info for current function...
69 MachineBasicBlock *MBB; // Current basic block
70 unsigned Stack[8]; // FP<n> Registers in each stack slot...
71 unsigned RegMap[8]; // Track which stack slot contains each register
72 unsigned StackTop; // The current top of the FP stack.
73
74 void dumpStack() const {
75 cerr << "Stack contents:";
76 for (unsigned i = 0; i != StackTop; ++i) {
77 cerr << " FP" << Stack[i];
78 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
79 }
80 cerr << "\n";
81 }
82 private:
83 // getSlot - Return the stack slot number a particular register number is
84 // in...
85 unsigned getSlot(unsigned RegNo) const {
86 assert(RegNo < 8 && "Regno out of range!");
87 return RegMap[RegNo];
88 }
89
90 // getStackEntry - Return the X86::FP<n> register in register ST(i)
91 unsigned getStackEntry(unsigned STi) const {
92 assert(STi < StackTop && "Access past stack top!");
93 return Stack[StackTop-1-STi];
94 }
95
96 // getSTReg - Return the X86::ST(i) register which contains the specified
97 // FP<RegNo> register
98 unsigned getSTReg(unsigned RegNo) const {
99 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
100 }
101
102 // pushReg - Push the specified FP<n> register onto the stack
103 void pushReg(unsigned Reg) {
104 assert(Reg < 8 && "Register number out of range!");
105 assert(StackTop < 8 && "Stack overflow!");
106 Stack[StackTop] = Reg;
107 RegMap[Reg] = StackTop++;
108 }
109
110 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
111 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
112 if (!isAtTop(RegNo)) {
113 unsigned STReg = getSTReg(RegNo);
114 unsigned RegOnTop = getStackEntry(0);
115
116 // Swap the slots the regs are in
117 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
118
119 // Swap stack slot contents
120 assert(RegMap[RegOnTop] < StackTop);
121 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
122
123 // Emit an fxch to update the runtime processors version of the state
124 BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(STReg);
125 NumFXCH++;
126 }
127 }
128
129 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
130 unsigned STReg = getSTReg(RegNo);
131 pushReg(AsReg); // New register on top of stack
132
133 BuildMI(*MBB, I, TII->get(X86::LD_Frr)).addReg(STReg);
134 }
135
136 // popStackAfter - Pop the current value off of the top of the FP stack
137 // after the specified instruction.
138 void popStackAfter(MachineBasicBlock::iterator &I);
139
140 // freeStackSlotAfter - Free the specified register from the register stack,
141 // so that it is no longer in a register. If the register is currently at
142 // the top of the stack, we just pop the current instruction, otherwise we
143 // store the current top-of-stack into the specified slot, then pop the top
144 // of stack.
145 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
146
147 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
148
149 void handleZeroArgFP(MachineBasicBlock::iterator &I);
150 void handleOneArgFP(MachineBasicBlock::iterator &I);
151 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
152 void handleTwoArgFP(MachineBasicBlock::iterator &I);
153 void handleCompareFP(MachineBasicBlock::iterator &I);
154 void handleCondMovFP(MachineBasicBlock::iterator &I);
155 void handleSpecialFP(MachineBasicBlock::iterator &I);
156 };
157 char FPS::ID = 0;
158}
159
160FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
161
162/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
163/// register references into FP stack references.
164///
165bool FPS::runOnMachineFunction(MachineFunction &MF) {
166 // We only need to run this pass if there are any FP registers used in this
167 // function. If it is all integer, there is nothing for us to do!
168 bool FPIsUsed = false;
169
170 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
171 for (unsigned i = 0; i <= 6; ++i)
172 if (MF.isPhysRegUsed(X86::FP0+i)) {
173 FPIsUsed = true;
174 break;
175 }
176
177 // Early exit.
178 if (!FPIsUsed) return false;
179
180 TII = MF.getTarget().getInstrInfo();
181 LV = &getAnalysis<LiveVariables>();
182 StackTop = 0;
183
184 // Process the function in depth first order so that we process at least one
185 // of the predecessors for every reachable block in the function.
186 std::set<MachineBasicBlock*> Processed;
187 MachineBasicBlock *Entry = MF.begin();
188
189 bool Changed = false;
190 for (df_ext_iterator<MachineBasicBlock*, std::set<MachineBasicBlock*> >
191 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
192 I != E; ++I)
193 Changed |= processBasicBlock(MF, **I);
194
195 return Changed;
196}
197
198/// processBasicBlock - Loop over all of the instructions in the basic block,
199/// transforming FP instructions into their stack form.
200///
201bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
202 bool Changed = false;
203 MBB = &BB;
204
205 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
206 MachineInstr *MI = I;
207 unsigned Flags = MI->getInstrDescriptor()->TSFlags;
208 if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
209 continue; // Efficiently ignore non-fp insts!
210
211 MachineInstr *PrevMI = 0;
212 if (I != BB.begin())
213 PrevMI = prior(I);
214
215 ++NumFP; // Keep track of # of pseudo instrs
216 DOUT << "\nFPInst:\t" << *MI;
217
218 // Get dead variables list now because the MI pointer may be deleted as part
219 // of processing!
220 SmallVector<unsigned, 8> DeadRegs;
221 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
222 const MachineOperand &MO = MI->getOperand(i);
Dan Gohman38a9a9f2007-09-14 20:33:02 +0000223 if (MO.isRegister() && MO.isDead())
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000224 DeadRegs.push_back(MO.getReg());
225 }
226
227 switch (Flags & X86II::FPTypeMask) {
228 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
229 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
230 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
231 case X86II::TwoArgFP: handleTwoArgFP(I); break;
232 case X86II::CompareFP: handleCompareFP(I); break;
233 case X86II::CondMovFP: handleCondMovFP(I); break;
234 case X86II::SpecialFP: handleSpecialFP(I); break;
235 default: assert(0 && "Unknown FP Type!");
236 }
237
238 // Check to see if any of the values defined by this instruction are dead
239 // after definition. If so, pop them.
240 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
241 unsigned Reg = DeadRegs[i];
242 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
243 DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
244 freeStackSlotAfter(I, Reg-X86::FP0);
245 }
246 }
247
248 // Print out all of the instructions expanded to if -debug
249 DEBUG(
250 MachineBasicBlock::iterator PrevI(PrevMI);
251 if (I == PrevI) {
252 cerr << "Just deleted pseudo instruction\n";
253 } else {
254 MachineBasicBlock::iterator Start = I;
255 // Rewind to first instruction newly inserted.
256 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
257 cerr << "Inserted instructions:\n\t";
258 Start->print(*cerr.stream(), &MF.getTarget());
Duncan Sandsfe279782007-09-11 12:30:25 +0000259 while (++Start != next(I)) {}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000260 }
261 dumpStack();
262 );
263
264 Changed = true;
265 }
266
267 assert(StackTop == 0 && "Stack not empty at end of basic block?");
268 return Changed;
269}
270
271//===----------------------------------------------------------------------===//
272// Efficient Lookup Table Support
273//===----------------------------------------------------------------------===//
274
275namespace {
276 struct TableEntry {
277 unsigned from;
278 unsigned to;
279 bool operator<(const TableEntry &TE) const { return from < TE.from; }
280 friend bool operator<(const TableEntry &TE, unsigned V) {
281 return TE.from < V;
282 }
283 friend bool operator<(unsigned V, const TableEntry &TE) {
284 return V < TE.from;
285 }
286 };
287}
288
289static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
290 for (unsigned i = 0; i != NumEntries-1; ++i)
291 if (!(Table[i] < Table[i+1])) return false;
292 return true;
293}
294
295static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
296 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
297 if (I != Table+N && I->from == Opcode)
298 return I->to;
299 return -1;
300}
301
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000302#ifdef NDEBUG
303#define ASSERT_SORTED(TABLE)
304#else
305#define ASSERT_SORTED(TABLE) \
306 { static bool TABLE##Checked = false; \
307 if (!TABLE##Checked) { \
Owen Anderson1636de92007-09-07 04:06:50 +0000308 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000309 "All lookup tables must be sorted for efficient access!"); \
310 TABLE##Checked = true; \
311 } \
312 }
313#endif
314
315//===----------------------------------------------------------------------===//
316// Register File -> Register Stack Mapping Methods
317//===----------------------------------------------------------------------===//
318
319// OpcodeTable - Sorted map of register instructions to their stack version.
320// The first element is an register file pseudo instruction, the second is the
321// concrete X86 instruction which uses the register stack.
322//
323static const TableEntry OpcodeTable[] = {
324 { X86::ABS_Fp32 , X86::ABS_F },
325 { X86::ABS_Fp64 , X86::ABS_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000326 { X86::ABS_Fp80 , X86::ABS_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000327 { X86::ADD_Fp32m , X86::ADD_F32m },
328 { X86::ADD_Fp64m , X86::ADD_F64m },
329 { X86::ADD_Fp64m32 , X86::ADD_F32m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000330 { X86::ADD_Fp80m32 , X86::ADD_F32m },
331 { X86::ADD_Fp80m64 , X86::ADD_F64m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000332 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
333 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000334 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000335 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
336 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000337 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000338 { X86::CHS_Fp32 , X86::CHS_F },
339 { X86::CHS_Fp64 , X86::CHS_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000340 { X86::CHS_Fp80 , X86::CHS_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000341 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
342 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000343 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000344 { X86::CMOVB_Fp32 , X86::CMOVB_F },
345 { X86::CMOVB_Fp64 , X86::CMOVB_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000346 { X86::CMOVB_Fp80 , X86::CMOVB_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000347 { X86::CMOVE_Fp32 , X86::CMOVE_F },
348 { X86::CMOVE_Fp64 , X86::CMOVE_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000349 { X86::CMOVE_Fp80 , X86::CMOVE_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000350 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
351 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000352 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000353 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
354 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000355 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000356 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
357 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000358 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000359 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
360 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000361 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000362 { X86::CMOVP_Fp32 , X86::CMOVP_F },
363 { X86::CMOVP_Fp64 , X86::CMOVP_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000364 { X86::CMOVP_Fp80 , X86::CMOVP_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000365 { X86::COS_Fp32 , X86::COS_F },
366 { X86::COS_Fp64 , X86::COS_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000367 { X86::COS_Fp80 , X86::COS_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000368 { X86::DIVR_Fp32m , X86::DIVR_F32m },
369 { X86::DIVR_Fp64m , X86::DIVR_F64m },
370 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000371 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
372 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000373 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
374 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000375 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000376 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
377 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000378 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000379 { X86::DIV_Fp32m , X86::DIV_F32m },
380 { X86::DIV_Fp64m , X86::DIV_F64m },
381 { X86::DIV_Fp64m32 , X86::DIV_F32m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000382 { X86::DIV_Fp80m32 , X86::DIV_F32m },
383 { X86::DIV_Fp80m64 , X86::DIV_F64m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000384 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
385 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000386 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000387 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
388 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000389 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000390 { X86::ILD_Fp16m32 , X86::ILD_F16m },
391 { X86::ILD_Fp16m64 , X86::ILD_F16m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000392 { X86::ILD_Fp16m80 , X86::ILD_F16m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000393 { X86::ILD_Fp32m32 , X86::ILD_F32m },
394 { X86::ILD_Fp32m64 , X86::ILD_F32m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000395 { X86::ILD_Fp32m80 , X86::ILD_F32m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000396 { X86::ILD_Fp64m32 , X86::ILD_F64m },
397 { X86::ILD_Fp64m64 , X86::ILD_F64m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000398 { X86::ILD_Fp64m80 , X86::ILD_F64m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000399 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
400 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
Dale Johannesen6d0e36a2007-08-07 01:17:37 +0000401 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000402 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
403 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
Dale Johannesen6d0e36a2007-08-07 01:17:37 +0000404 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000405 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
406 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
Dale Johannesen6d0e36a2007-08-07 01:17:37 +0000407 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000408 { X86::IST_Fp16m32 , X86::IST_F16m },
409 { X86::IST_Fp16m64 , X86::IST_F16m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000410 { X86::IST_Fp16m80 , X86::IST_F16m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000411 { X86::IST_Fp32m32 , X86::IST_F32m },
412 { X86::IST_Fp32m64 , X86::IST_F32m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000413 { X86::IST_Fp32m80 , X86::IST_F32m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000414 { X86::IST_Fp64m32 , X86::IST_FP64m },
415 { X86::IST_Fp64m64 , X86::IST_FP64m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000416 { X86::IST_Fp64m80 , X86::IST_FP64m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000417 { X86::LD_Fp032 , X86::LD_F0 },
418 { X86::LD_Fp064 , X86::LD_F0 },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000419 { X86::LD_Fp080 , X86::LD_F0 },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000420 { X86::LD_Fp132 , X86::LD_F1 },
421 { X86::LD_Fp164 , X86::LD_F1 },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000422 { X86::LD_Fp180 , X86::LD_F1 },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000423 { X86::LD_Fp32m , X86::LD_F32m },
Dale Johannesenc428e0f2007-08-07 20:29:26 +0000424 { X86::LD_Fp32m64 , X86::LD_F32m },
425 { X86::LD_Fp32m80 , X86::LD_F32m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000426 { X86::LD_Fp64m , X86::LD_F64m },
Dale Johannesenc428e0f2007-08-07 20:29:26 +0000427 { X86::LD_Fp64m80 , X86::LD_F64m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000428 { X86::LD_Fp80m , X86::LD_F80m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000429 { X86::MUL_Fp32m , X86::MUL_F32m },
430 { X86::MUL_Fp64m , X86::MUL_F64m },
431 { X86::MUL_Fp64m32 , X86::MUL_F32m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000432 { X86::MUL_Fp80m32 , X86::MUL_F32m },
433 { X86::MUL_Fp80m64 , X86::MUL_F64m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000434 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
435 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000436 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000437 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
438 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000439 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000440 { X86::SIN_Fp32 , X86::SIN_F },
441 { X86::SIN_Fp64 , X86::SIN_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000442 { X86::SIN_Fp80 , X86::SIN_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000443 { X86::SQRT_Fp32 , X86::SQRT_F },
444 { X86::SQRT_Fp64 , X86::SQRT_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000445 { X86::SQRT_Fp80 , X86::SQRT_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000446 { X86::ST_Fp32m , X86::ST_F32m },
447 { X86::ST_Fp64m , X86::ST_F64m },
448 { X86::ST_Fp64m32 , X86::ST_F32m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000449 { X86::ST_Fp80m32 , X86::ST_F32m },
450 { X86::ST_Fp80m64 , X86::ST_F64m },
451 { X86::ST_FpP80m , X86::ST_FP80m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000452 { X86::SUBR_Fp32m , X86::SUBR_F32m },
453 { X86::SUBR_Fp64m , X86::SUBR_F64m },
454 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000455 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
456 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000457 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
458 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000459 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000460 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
461 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000462 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000463 { X86::SUB_Fp32m , X86::SUB_F32m },
464 { X86::SUB_Fp64m , X86::SUB_F64m },
465 { X86::SUB_Fp64m32 , X86::SUB_F32m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000466 { X86::SUB_Fp80m32 , X86::SUB_F32m },
467 { X86::SUB_Fp80m64 , X86::SUB_F64m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000468 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
469 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000470 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000471 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
472 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000473 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000474 { X86::TST_Fp32 , X86::TST_F },
475 { X86::TST_Fp64 , X86::TST_F },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000476 { X86::TST_Fp80 , X86::TST_F },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000477 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
478 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000479 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000480 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
481 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000482 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000483};
484
485static unsigned getConcreteOpcode(unsigned Opcode) {
486 ASSERT_SORTED(OpcodeTable);
Owen Anderson1636de92007-09-07 04:06:50 +0000487 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000488 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
489 return Opc;
490}
491
492//===----------------------------------------------------------------------===//
493// Helper Methods
494//===----------------------------------------------------------------------===//
495
496// PopTable - Sorted map of instructions to their popping version. The first
497// element is an instruction, the second is the version which pops.
498//
499static const TableEntry PopTable[] = {
500 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
501
502 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
503 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
504
505 { X86::IST_F16m , X86::IST_FP16m },
506 { X86::IST_F32m , X86::IST_FP32m },
507
508 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
509
510 { X86::ST_F32m , X86::ST_FP32m },
511 { X86::ST_F64m , X86::ST_FP64m },
512 { X86::ST_Frr , X86::ST_FPrr },
513
514 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
515 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
516
517 { X86::UCOM_FIr , X86::UCOM_FIPr },
518
519 { X86::UCOM_FPr , X86::UCOM_FPPr },
520 { X86::UCOM_Fr , X86::UCOM_FPr },
521};
522
523/// popStackAfter - Pop the current value off of the top of the FP stack after
524/// the specified instruction. This attempts to be sneaky and combine the pop
525/// into the instruction itself if possible. The iterator is left pointing to
526/// the last instruction, be it a new pop instruction inserted, or the old
527/// instruction if it was modified in place.
528///
529void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
530 ASSERT_SORTED(PopTable);
531 assert(StackTop > 0 && "Cannot pop empty stack!");
532 RegMap[Stack[--StackTop]] = ~0; // Update state
533
534 // Check to see if there is a popping version of this instruction...
Owen Anderson1636de92007-09-07 04:06:50 +0000535 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000536 if (Opcode != -1) {
537 I->setInstrDescriptor(TII->get(Opcode));
538 if (Opcode == X86::UCOM_FPPr)
539 I->RemoveOperand(0);
540 } else { // Insert an explicit pop
541 I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
542 }
543}
544
545/// freeStackSlotAfter - Free the specified register from the register stack, so
546/// that it is no longer in a register. If the register is currently at the top
547/// of the stack, we just pop the current instruction, otherwise we store the
548/// current top-of-stack into the specified slot, then pop the top of stack.
549void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
550 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
551 popStackAfter(I);
552 return;
553 }
554
555 // Otherwise, store the top of stack into the dead slot, killing the operand
556 // without having to add in an explicit xchg then pop.
557 //
558 unsigned STReg = getSTReg(FPRegNo);
559 unsigned OldSlot = getSlot(FPRegNo);
560 unsigned TopReg = Stack[StackTop-1];
561 Stack[OldSlot] = TopReg;
562 RegMap[TopReg] = OldSlot;
563 RegMap[FPRegNo] = ~0;
564 Stack[--StackTop] = ~0;
565 I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(STReg);
566}
567
568
569static unsigned getFPReg(const MachineOperand &MO) {
570 assert(MO.isRegister() && "Expected an FP register!");
571 unsigned Reg = MO.getReg();
572 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
573 return Reg - X86::FP0;
574}
575
576
577//===----------------------------------------------------------------------===//
578// Instruction transformation implementation
579//===----------------------------------------------------------------------===//
580
581/// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
582///
583void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
584 MachineInstr *MI = I;
585 unsigned DestReg = getFPReg(MI->getOperand(0));
586
587 // Change from the pseudo instruction to the concrete instruction.
588 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
589 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
590
591 // Result gets pushed on the stack.
592 pushReg(DestReg);
593}
594
595/// handleOneArgFP - fst <mem>, ST(0)
596///
597void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
598 MachineInstr *MI = I;
599 unsigned NumOps = MI->getInstrDescriptor()->numOperands;
600 assert((NumOps == 5 || NumOps == 1) &&
601 "Can only handle fst* & ftst instructions!");
602
603 // Is this the last use of the source register?
604 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
605 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
606
607 // FISTP64m is strange because there isn't a non-popping versions.
608 // If we have one _and_ we don't want to pop the operand, duplicate the value
609 // on the stack instead of moving it. This ensure that popping the value is
610 // always ok.
Dale Johannesenb1064a52007-09-17 20:15:38 +0000611 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000612 //
613 if (!KillsSrc &&
614 (MI->getOpcode() == X86::IST_Fp64m32 ||
615 MI->getOpcode() == X86::ISTT_Fp16m32 ||
616 MI->getOpcode() == X86::ISTT_Fp32m32 ||
617 MI->getOpcode() == X86::ISTT_Fp64m32 ||
618 MI->getOpcode() == X86::IST_Fp64m64 ||
619 MI->getOpcode() == X86::ISTT_Fp16m64 ||
620 MI->getOpcode() == X86::ISTT_Fp32m64 ||
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000621 MI->getOpcode() == X86::ISTT_Fp64m64 ||
Dale Johannesen0a6bdef2007-09-20 01:27:54 +0000622 MI->getOpcode() == X86::IST_Fp64m80 ||
Dale Johannesen6d0e36a2007-08-07 01:17:37 +0000623 MI->getOpcode() == X86::ISTT_Fp16m80 ||
624 MI->getOpcode() == X86::ISTT_Fp32m80 ||
625 MI->getOpcode() == X86::ISTT_Fp64m80 ||
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000626 MI->getOpcode() == X86::ST_FpP80m)) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000627 duplicateToTop(Reg, 7 /*temp register*/, I);
628 } else {
629 moveToTop(Reg, I); // Move to the top of the stack...
630 }
631
632 // Convert from the pseudo instruction to the concrete instruction.
633 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
634 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
635
636 if (MI->getOpcode() == X86::IST_FP64m ||
637 MI->getOpcode() == X86::ISTT_FP16m ||
638 MI->getOpcode() == X86::ISTT_FP32m ||
Dale Johannesenb71720f2007-08-06 19:50:32 +0000639 MI->getOpcode() == X86::ISTT_FP64m ||
640 MI->getOpcode() == X86::ST_FP80m) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000641 assert(StackTop > 0 && "Stack empty??");
642 --StackTop;
643 } else if (KillsSrc) { // Last use of operand?
644 popStackAfter(I);
645 }
646}
647
648
649/// handleOneArgFPRW: Handle instructions that read from the top of stack and
650/// replace the value with a newly computed value. These instructions may have
651/// non-fp operands after their FP operands.
652///
653/// Examples:
654/// R1 = fchs R2
655/// R1 = fadd R2, [mem]
656///
657void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
658 MachineInstr *MI = I;
659 unsigned NumOps = MI->getInstrDescriptor()->numOperands;
660 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
661
662 // Is this the last use of the source register?
663 unsigned Reg = getFPReg(MI->getOperand(1));
664 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
665
666 if (KillsSrc) {
667 // If this is the last use of the source register, just make sure it's on
668 // the top of the stack.
669 moveToTop(Reg, I);
670 assert(StackTop > 0 && "Stack cannot be empty!");
671 --StackTop;
672 pushReg(getFPReg(MI->getOperand(0)));
673 } else {
674 // If this is not the last use of the source register, _copy_ it to the top
675 // of the stack.
676 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
677 }
678
679 // Change from the pseudo instruction to the concrete instruction.
680 MI->RemoveOperand(1); // Drop the source operand.
681 MI->RemoveOperand(0); // Drop the destination operand.
682 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
683}
684
685
686//===----------------------------------------------------------------------===//
687// Define tables of various ways to map pseudo instructions
688//
689
690// ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
691static const TableEntry ForwardST0Table[] = {
692 { X86::ADD_Fp32 , X86::ADD_FST0r },
693 { X86::ADD_Fp64 , X86::ADD_FST0r },
Dale Johannesen19f781d2007-08-06 21:31:06 +0000694 { X86::ADD_Fp80 , X86::ADD_FST0r },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000695 { X86::DIV_Fp32 , X86::DIV_FST0r },
696 { X86::DIV_Fp64 , X86::DIV_FST0r },
Dale Johannesen19f781d2007-08-06 21:31:06 +0000697 { X86::DIV_Fp80 , X86::DIV_FST0r },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000698 { X86::MUL_Fp32 , X86::MUL_FST0r },
699 { X86::MUL_Fp64 , X86::MUL_FST0r },
Dale Johannesen19f781d2007-08-06 21:31:06 +0000700 { X86::MUL_Fp80 , X86::MUL_FST0r },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000701 { X86::SUB_Fp32 , X86::SUB_FST0r },
702 { X86::SUB_Fp64 , X86::SUB_FST0r },
Dale Johannesen19f781d2007-08-06 21:31:06 +0000703 { X86::SUB_Fp80 , X86::SUB_FST0r },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000704};
705
706// ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
707static const TableEntry ReverseST0Table[] = {
708 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
709 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
Dale Johannesen19f781d2007-08-06 21:31:06 +0000710 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000711 { X86::DIV_Fp32 , X86::DIVR_FST0r },
712 { X86::DIV_Fp64 , X86::DIVR_FST0r },
Dale Johannesen19f781d2007-08-06 21:31:06 +0000713 { X86::DIV_Fp80 , X86::DIVR_FST0r },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000714 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
715 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
Dale Johannesen19f781d2007-08-06 21:31:06 +0000716 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000717 { X86::SUB_Fp32 , X86::SUBR_FST0r },
718 { X86::SUB_Fp64 , X86::SUBR_FST0r },
Dale Johannesen19f781d2007-08-06 21:31:06 +0000719 { X86::SUB_Fp80 , X86::SUBR_FST0r },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000720};
721
722// ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
723static const TableEntry ForwardSTiTable[] = {
724 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
725 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
Dale Johannesen19f781d2007-08-06 21:31:06 +0000726 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000727 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
728 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
Dale Johannesen19f781d2007-08-06 21:31:06 +0000729 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000730 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
731 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
Dale Johannesen19f781d2007-08-06 21:31:06 +0000732 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000733 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
734 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
Dale Johannesen19f781d2007-08-06 21:31:06 +0000735 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000736};
737
738// ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
739static const TableEntry ReverseSTiTable[] = {
740 { X86::ADD_Fp32 , X86::ADD_FrST0 },
741 { X86::ADD_Fp64 , X86::ADD_FrST0 },
Dale Johannesen19f781d2007-08-06 21:31:06 +0000742 { X86::ADD_Fp80 , X86::ADD_FrST0 },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000743 { X86::DIV_Fp32 , X86::DIV_FrST0 },
744 { X86::DIV_Fp64 , X86::DIV_FrST0 },
Dale Johannesen19f781d2007-08-06 21:31:06 +0000745 { X86::DIV_Fp80 , X86::DIV_FrST0 },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000746 { X86::MUL_Fp32 , X86::MUL_FrST0 },
747 { X86::MUL_Fp64 , X86::MUL_FrST0 },
Dale Johannesen19f781d2007-08-06 21:31:06 +0000748 { X86::MUL_Fp80 , X86::MUL_FrST0 },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000749 { X86::SUB_Fp32 , X86::SUB_FrST0 },
750 { X86::SUB_Fp64 , X86::SUB_FrST0 },
Dale Johannesen19f781d2007-08-06 21:31:06 +0000751 { X86::SUB_Fp80 , X86::SUB_FrST0 },
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000752};
753
754
755/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
756/// instructions which need to be simplified and possibly transformed.
757///
758/// Result: ST(0) = fsub ST(0), ST(i)
759/// ST(i) = fsub ST(0), ST(i)
760/// ST(0) = fsubr ST(0), ST(i)
761/// ST(i) = fsubr ST(0), ST(i)
762///
763void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
764 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
765 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
766 MachineInstr *MI = I;
767
768 unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
769 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
770 unsigned Dest = getFPReg(MI->getOperand(0));
771 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
772 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
773 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
774 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
775
776 unsigned TOS = getStackEntry(0);
777
778 // One of our operands must be on the top of the stack. If neither is yet, we
779 // need to move one.
780 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
781 // We can choose to move either operand to the top of the stack. If one of
782 // the operands is killed by this instruction, we want that one so that we
783 // can update right on top of the old version.
784 if (KillsOp0) {
785 moveToTop(Op0, I); // Move dead operand to TOS.
786 TOS = Op0;
787 } else if (KillsOp1) {
788 moveToTop(Op1, I);
789 TOS = Op1;
790 } else {
791 // All of the operands are live after this instruction executes, so we
792 // cannot update on top of any operand. Because of this, we must
793 // duplicate one of the stack elements to the top. It doesn't matter
794 // which one we pick.
795 //
796 duplicateToTop(Op0, Dest, I);
797 Op0 = TOS = Dest;
798 KillsOp0 = true;
799 }
800 } else if (!KillsOp0 && !KillsOp1) {
801 // If we DO have one of our operands at the top of the stack, but we don't
802 // have a dead operand, we must duplicate one of the operands to a new slot
803 // on the stack.
804 duplicateToTop(Op0, Dest, I);
805 Op0 = TOS = Dest;
806 KillsOp0 = true;
807 }
808
809 // Now we know that one of our operands is on the top of the stack, and at
810 // least one of our operands is killed by this instruction.
811 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
812 "Stack conditions not set up right!");
813
814 // We decide which form to use based on what is on the top of the stack, and
815 // which operand is killed by this instruction.
816 const TableEntry *InstTable;
817 bool isForward = TOS == Op0;
818 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
819 if (updateST0) {
820 if (isForward)
821 InstTable = ForwardST0Table;
822 else
823 InstTable = ReverseST0Table;
824 } else {
825 if (isForward)
826 InstTable = ForwardSTiTable;
827 else
828 InstTable = ReverseSTiTable;
829 }
830
Owen Anderson1636de92007-09-07 04:06:50 +0000831 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
832 MI->getOpcode());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000833 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
834
835 // NotTOS - The register which is not on the top of stack...
836 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
837
838 // Replace the old instruction with a new instruction
839 MBB->remove(I++);
840 I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS));
841
842 // If both operands are killed, pop one off of the stack in addition to
843 // overwriting the other one.
844 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
845 assert(!updateST0 && "Should have updated other operand!");
846 popStackAfter(I); // Pop the top of stack
847 }
848
849 // Update stack information so that we know the destination register is now on
850 // the stack.
851 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
852 assert(UpdatedSlot < StackTop && Dest < 7);
853 Stack[UpdatedSlot] = Dest;
854 RegMap[Dest] = UpdatedSlot;
855 delete MI; // Remove the old instruction
856}
857
858/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
859/// register arguments and no explicit destinations.
860///
861void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
862 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
863 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
864 MachineInstr *MI = I;
865
866 unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
867 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
868 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
869 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
870 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
871 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
872
873 // Make sure the first operand is on the top of stack, the other one can be
874 // anywhere.
875 moveToTop(Op0, I);
876
877 // Change from the pseudo instruction to the concrete instruction.
878 MI->getOperand(0).setReg(getSTReg(Op1));
879 MI->RemoveOperand(1);
880 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
881
882 // If any of the operands are killed by this instruction, free them.
883 if (KillsOp0) freeStackSlotAfter(I, Op0);
884 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
885}
886
887/// handleCondMovFP - Handle two address conditional move instructions. These
888/// instructions move a st(i) register to st(0) iff a condition is true. These
889/// instructions require that the first operand is at the top of the stack, but
890/// otherwise don't modify the stack at all.
891void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
892 MachineInstr *MI = I;
893
894 unsigned Op0 = getFPReg(MI->getOperand(0));
895 unsigned Op1 = getFPReg(MI->getOperand(2));
896 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
897
898 // The first operand *must* be on the top of the stack.
899 moveToTop(Op0, I);
900
901 // Change the second operand to the stack register that the operand is in.
902 // Change from the pseudo instruction to the concrete instruction.
903 MI->RemoveOperand(0);
904 MI->RemoveOperand(1);
905 MI->getOperand(0).setReg(getSTReg(Op1));
906 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
907
908 // If we kill the second operand, make sure to pop it from the stack.
909 if (Op0 != Op1 && KillsOp1) {
910 // Get this value off of the register stack.
911 freeStackSlotAfter(I, Op1);
912 }
913}
914
915
916/// handleSpecialFP - Handle special instructions which behave unlike other
917/// floating point instructions. This is primarily intended for use by pseudo
918/// instructions.
919///
920void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
921 MachineInstr *MI = I;
922 switch (MI->getOpcode()) {
923 default: assert(0 && "Unknown SpecialFP instruction!");
924 case X86::FpGETRESULT32: // Appears immediately after a call returning FP type!
925 case X86::FpGETRESULT64: // Appears immediately after a call returning FP type!
Dale Johannesen19f781d2007-08-06 21:31:06 +0000926 case X86::FpGETRESULT80:
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000927 assert(StackTop == 0 && "Stack should be empty after a call!");
928 pushReg(getFPReg(MI->getOperand(0)));
929 break;
930 case X86::FpSETRESULT32:
931 case X86::FpSETRESULT64:
Dale Johannesen19f781d2007-08-06 21:31:06 +0000932 case X86::FpSETRESULT80:
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000933 assert(StackTop == 1 && "Stack should have one element on it to return!");
934 --StackTop; // "Forget" we have something on the top of stack!
935 break;
936 case X86::MOV_Fp3232:
937 case X86::MOV_Fp3264:
938 case X86::MOV_Fp6432:
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000939 case X86::MOV_Fp6464:
940 case X86::MOV_Fp3280:
941 case X86::MOV_Fp6480:
942 case X86::MOV_Fp8032:
943 case X86::MOV_Fp8064:
944 case X86::MOV_Fp8080: {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000945 unsigned SrcReg = getFPReg(MI->getOperand(1));
946 unsigned DestReg = getFPReg(MI->getOperand(0));
947
948 if (LV->KillsRegister(MI, X86::FP0+SrcReg)) {
949 // If the input operand is killed, we can just change the owner of the
950 // incoming stack slot into the result.
951 unsigned Slot = getSlot(SrcReg);
952 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
953 Stack[Slot] = DestReg;
954 RegMap[DestReg] = Slot;
955
956 } else {
957 // For FMOV we just duplicate the specified value to a new stack slot.
958 // This could be made better, but would require substantial changes.
959 duplicateToTop(SrcReg, DestReg, I);
960 }
961 break;
962 }
963 }
964
965 I = MBB->erase(I); // Remove the pseudo instruction
966 --I;
967}