| Evan Cheng | fdd472e | 2009-07-21 23:54:22 +0000 | [diff] [blame] | 1 | //===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===// |
| Evan Cheng | 88e78d2 | 2009-06-19 01:51:50 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines the itinerary class data for the ARM v6 processors. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| David Goodwin | 48e1359 | 2009-08-10 15:56:13 +0000 | [diff] [blame^] | 14 | // Single issue pipeline so every itinerary starts with FU_pipe0 |
| Evan Cheng | 88e78d2 | 2009-06-19 01:51:50 +0000 | [diff] [blame] | 15 | def V6Itineraries : ProcessorItineraries<[ |
| David Goodwin | 48e1359 | 2009-08-10 15:56:13 +0000 | [diff] [blame^] | 16 | // single-cycle integer ALU |
| 17 | InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>, |
| 18 | // loads have an extra cycle of latency, but are fully pipelined |
| 19 | InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>, |
| 20 | InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>, |
| 21 | // fully-pipelined stores |
| 22 | InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>, |
| 23 | InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>, |
| 24 | // fp ALU is not pipelined |
| 25 | InstrItinData<IIC_fpALU , [InstrStage<6, [FU_Pipe0]>]>, |
| 26 | // no delay slots, so the latency of a branch is unimportant |
| 27 | InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]> |
| Evan Cheng | 88e78d2 | 2009-06-19 01:51:50 +0000 | [diff] [blame] | 28 | ]>; |