| Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 1 | //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===// | 
|  | 2 | // | 
|  | 3 | //                     The LLVM Compiler Infrastructure | 
|  | 4 | // | 
|  | 5 | // This file was developed by the "Instituto Nokia de Tecnologia" and | 
|  | 6 | // is distributed under the University of Illinois Open Source | 
|  | 7 | // License. See LICENSE.TXT for details. | 
|  | 8 | // | 
|  | 9 | //===----------------------------------------------------------------------===// | 
|  | 10 | // | 
|  | 11 | // This file contains the ARM implementation of the TargetInstrInfo class. | 
|  | 12 | // | 
|  | 13 | //===----------------------------------------------------------------------===// | 
|  | 14 |  | 
|  | 15 | #include "ARMInstrInfo.h" | 
|  | 16 | #include "ARM.h" | 
|  | 17 | #include "llvm/CodeGen/MachineInstrBuilder.h" | 
|  | 18 | #include "ARMGenInstrInfo.inc" | 
|  | 19 | using namespace llvm; | 
|  | 20 |  | 
|  | 21 | ARMInstrInfo::ARMInstrInfo() | 
|  | 22 | : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) { | 
|  | 23 | } | 
|  | 24 |  | 
|  | 25 | /// Return true if the instruction is a register to register move and | 
|  | 26 | /// leave the source and dest operands in the passed parameters. | 
|  | 27 | /// | 
|  | 28 | bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI, | 
|  | 29 | unsigned &SrcReg, unsigned &DstReg) const { | 
| Rafael Espindola | 49e4415 | 2006-06-27 21:52:45 +0000 | [diff] [blame^] | 30 | MachineOpCode oc = MI.getOpcode(); | 
|  | 31 | switch (oc) { | 
|  | 32 | default: | 
|  | 33 | return false; | 
|  | 34 | case ARM::movrr: | 
|  | 35 | assert(MI.getNumOperands() == 2 && | 
|  | 36 | MI.getOperand(0).isRegister() && | 
|  | 37 | MI.getOperand(1).isRegister() && | 
|  | 38 | "Invalid ARM MOV instruction"); | 
|  | 39 | SrcReg = MI.getOperand(1).getReg();; | 
|  | 40 | DstReg = MI.getOperand(0).getReg();; | 
|  | 41 | return true; | 
|  | 42 | } | 
| Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 43 | } | 
|  | 44 |  | 
|  | 45 | /// isLoadFromStackSlot - If the specified machine instruction is a direct | 
|  | 46 | /// load from a stack slot, return the virtual or physical register number of | 
|  | 47 | /// the destination along with the FrameIndex of the loaded stack slot.  If | 
|  | 48 | /// not, return 0.  This predicate must return 0 if the instruction has | 
|  | 49 | /// any side effects other than loading from the stack slot. | 
|  | 50 | unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, | 
|  | 51 | int &FrameIndex) const { | 
|  | 52 | assert(0 && "not implemented"); | 
|  | 53 | return 0; | 
|  | 54 | } | 
|  | 55 |  | 
|  | 56 | /// isStoreToStackSlot - If the specified machine instruction is a direct | 
|  | 57 | /// store to a stack slot, return the virtual or physical register number of | 
|  | 58 | /// the source reg along with the FrameIndex of the loaded stack slot.  If | 
|  | 59 | /// not, return 0.  This predicate must return 0 if the instruction has | 
|  | 60 | /// any side effects other than storing to the stack slot. | 
|  | 61 | unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, | 
|  | 62 | int &FrameIndex) const { | 
|  | 63 | assert(0 && "not implemented"); | 
|  | 64 | return 0; | 
|  | 65 | } |