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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 4e694c96f1c0c2d09a287ff69bab5896e04dd3fd / . / test / CodeGen / Mips / atomic.ll
blob: 2d5555bd2cb97942347c6101fbb1663615ce626e [file] [log] [blame]
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000[diff] [blame^]1; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
2
3
4declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind
5declare i32 @llvm.atomic.load.nand.i32.p0i32(i32* nocapture, i32) nounwind
6declare i32 @llvm.atomic.swap.i32.p0i32(i32* nocapture, i32) nounwind
7declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* nocapture, i32, i32) nounwind
8
9declare i8 @llvm.atomic.load.add.i8.p0i8(i8* nocapture, i8) nounwind
10declare i8 @llvm.atomic.load.sub.i8.p0i8(i8* nocapture, i8) nounwind
11declare i8 @llvm.atomic.load.nand.i8.p0i8(i8* nocapture, i8) nounwind
12declare i8 @llvm.atomic.swap.i8.p0i8(i8* nocapture, i8) nounwind
13declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* nocapture, i8, i8) nounwind
14
15
16@x = common global i32 0, align 4
17
18define i32 @AtomicLoadAdd32(i32 %incr) nounwind {
19entry:
20 %0 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* @x, i32 %incr)
21 ret i32 %0
22
23; CHECK: AtomicLoadAdd32:
24; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
25; CHECK: $[[BB0:[A-Z_0-9]+]]:
26; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
27; CHECK: or $2, $zero, $[[R1]]
28; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4
29; CHECK: sc $[[R2]], 0($[[R0]])
30; CHECK: beq $[[R2]], $zero, $[[BB0]]
31}
32
33define i32 @AtomicLoadNand32(i32 %incr) nounwind {
34entry:
35 %0 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* @x, i32 %incr)
36 ret i32 %0
37
38; CHECK: AtomicLoadNand32:
39; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
40; CHECK: $[[BB0:[A-Z_0-9]+]]:
41; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
42; CHECK: or $2, $zero, $[[R1]]
43; CHECK: and $[[R1]], $[[R1]], $4
44; CHECK: nor $[[R2:[0-9]+]], $zero, $[[R1]]
45; CHECK: sc $[[R2]], 0($[[R0]])
46; CHECK: beq $[[R2]], $zero, $[[BB0]]
47}
48
49define i32 @AtomicSwap32(i32 %oldval) nounwind {
50entry:
51 %0 = call i32 @llvm.atomic.swap.i32.p0i32(i32* @x, i32 %oldval)
52 ret i32 %0
53
54; CHECK: AtomicSwap32:
55; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
56; CHECK: sw $4, [[OFFSET:[0-9]+]]($sp)
57; CHECK: $[[BB0:[A-Z_0-9]+]]:
58; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
59; CHECK: or $2, $zero, $[[R1]]
60; CHECK: lw $[[R2:[0-9]+]], [[OFFSET]]($sp)
61; CHECK: or $[[R3:[0-9]+]], $zero, $[[R2]]
62; CHECK: sc $[[R3]], 0($[[R0]])
63; CHECK: beq $[[R3]], $zero, $[[BB0]]
64}
65
66define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind {
67entry:
68 %0 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* @x, i32 %oldval, i32 %newval)
69 ret i32 %0
70
71; CHECK: AtomicCmpSwap32:
72; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
73; CHECK: sw $5, [[OFFSET:[0-9]+]]($sp)
74; CHECK: $[[BB0:[A-Z_0-9]+]]:
75; CHECK: ll $2, 0($[[R0]])
76; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
77; CHECK: lw $[[R1:[0-9]+]], [[OFFSET]]($sp)
78; CHECK: or $[[R2:[0-9]+]], $zero, $[[R1]]
79; CHECK: sc $[[R2]], 0($[[R0]])
80; CHECK: beq $[[R2]], $zero, $[[BB0]]
81; CHECK: $[[BB1]]:
82}
83
84
85
86@y = common global i8 0, align 1
87
88define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
89entry:
90 %0 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @y, i8 %incr)
91 ret i8 %0
92
93; CHECK: AtomicLoadAdd8:
94; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
95; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
96; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
97; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
98; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
99; CHECK: ori $[[R5:[0-9]+]], $zero, 255
100; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
101; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
102; CHECK: andi $[[R8:[0-9]+]], $4, 255
103; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
104
105; CHECK: $[[BB0:[A-Z_0-9]+]]:
106; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
107; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
108; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
109; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
110; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
111; CHECK: sc $[[R14]], 0($[[R2]])
112; CHECK: beq $[[R14]], $zero, $[[BB0]]
113
114; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
115; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
116; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
117; CHECK: sra $2, $[[R17]], 24
118}
119
120define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
121entry:
122 %0 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @y, i8 %incr)
123 ret i8 %0
124
125; CHECK: AtomicLoadSub8:
126; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
127; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
128; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
129; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
130; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
131; CHECK: ori $[[R5:[0-9]+]], $zero, 255
132; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
133; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
134; CHECK: subu $[[R18:[0-9]+]], $zero, $4
135; CHECK: andi $[[R8:[0-9]+]], $[[R18]], 255
136; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
137
138; CHECK: $[[BB0:[A-Z_0-9]+]]:
139; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
140; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
141; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
142; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
143; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
144; CHECK: sc $[[R14]], 0($[[R2]])
145; CHECK: beq $[[R14]], $zero, $[[BB0]]
146
147; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
148; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
149; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
150; CHECK: sra $2, $[[R17]], 24
151}
152
153define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
154entry:
155 %0 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @y, i8 %incr)
156 ret i8 %0
157
158; CHECK: AtomicLoadNand8:
159; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
160; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
161; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
162; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
163; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
164; CHECK: ori $[[R5:[0-9]+]], $zero, 255
165; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
166; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
167; CHECK: andi $[[R8:[0-9]+]], $4, 255
168; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
169
170; CHECK: $[[BB0:[A-Z_0-9]+]]:
171; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
172; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
173; CHECK: nor $[[R11:[0-9]+]], $zero, $[[R18]]
174; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
175; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
176; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
177; CHECK: sc $[[R14]], 0($[[R2]])
178; CHECK: beq $[[R14]], $zero, $[[BB0]]
179
180; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
181; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
182; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
183; CHECK: sra $2, $[[R17]], 24
184}
185
186define signext i8 @AtomicSwap8(i8 signext %oldval) nounwind {
187entry:
188 %0 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @y, i8 %oldval)
189 ret i8 %0
190
191; CHECK: AtomicSwap8:
192; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
193; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
194; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
195; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
196; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
197; CHECK: ori $[[R5:[0-9]+]], $zero, 255
198; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
199; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
200; CHECK: andi $[[R8:[0-9]+]], $4, 255
201; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
202; CHECK: sw $[[R9]], [[OFFSET:[0-9]+]]($sp)
203
204; CHECK: $[[BB0:[A-Z_0-9]+]]:
205; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
206; CHECK: lw $[[R18:[0-9]+]], [[OFFSET]]($sp)
207; CHECK: or $[[R11:[0-9]+]], $zero, $[[R18]]
208; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
209; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
210; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
211; CHECK: sc $[[R14]], 0($[[R2]])
212; CHECK: beq $[[R14]], $zero, $[[BB0]]
213
214; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
215; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
216; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
217; CHECK: sra $2, $[[R17]], 24
218}
219
220define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
221entry:
222 %0 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @y, i8 %oldval, i8 %newval)
223 ret i8 %0
224
225; CHECK: AtomicCmpSwap8:
226; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
227; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
228; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
229; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
230; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
231; CHECK: ori $[[R5:[0-9]+]], $zero, 255
232; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
233; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
234; CHECK: andi $[[R8:[0-9]+]], $4, 255
235; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
236; CHECK: andi $[[R10:[0-9]+]], $5, 255
237; CHECK: sll $[[R11:[0-9]+]], $[[R10]], $[[R4]]
238
239; CHECK: $[[BB0:[A-Z_0-9]+]]:
240; CHECK: ll $[[R12:[0-9]+]], 0($[[R2]])
241; CHECK: and $[[R13:[0-9]+]], $[[R12]], $[[R6]]
242; CHECK: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]]
243
244; CHECK: and $[[R14:[0-9]+]], $[[R12]], $[[R7]]
245; CHECK: or $[[R15:[0-9]+]], $[[R14]], $[[R11]]
246; CHECK: sc $[[R15]], 0($[[R2]])
247; CHECK: beq $[[R15]], $zero, $[[BB0]]
248
249; CHECK: $[[BB1]]:
250; CHECK: srl $[[R16:[0-9]+]], $[[R13]], $[[R4]]
251; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
252; CHECK: sra $2, $[[R17]], 24
253}