blob: 7574687f8cde5902014bc4661a095b3fa98d0fa4 [file] [log] [blame]
Wesley Pecka70f28c2010-02-23 19:15:24 +00001; Ensure that all immediate values that are 32-bits or less can be loaded
2; using a single instruction and that immediate values 64-bits or less can
3; be loaded using two instructions.
4;
5; RUN: llc < %s -march=mblaze | FileCheck %s
6; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
7
8define i8 @retimm_i8() {
9 ; CHECK: retimm_i8:
Wesley Peck4e9141f2010-10-21 03:57:26 +000010 ; CHECK: rtsd
11 ; CHECK-NEXT: add
Wesley Pecka70f28c2010-02-23 19:15:24 +000012 ; FPU: retimm_i8:
Wesley Peck4e9141f2010-10-21 03:57:26 +000013 ; FPU: rtsd
14 ; FPU-NEXT: add
Wesley Pecka70f28c2010-02-23 19:15:24 +000015 ret i8 123
16}
17
18define i16 @retimm_i16() {
19 ; CHECK: retimm_i16:
Wesley Peck4e9141f2010-10-21 03:57:26 +000020 ; CHECK: rtsd
21 ; CHECK-NEXT: add
Wesley Pecka70f28c2010-02-23 19:15:24 +000022 ; FPU: retimm_i16:
Wesley Peck4e9141f2010-10-21 03:57:26 +000023 ; FPU: rtsd
24 ; FPU-NEXT: add
Wesley Pecka70f28c2010-02-23 19:15:24 +000025 ret i16 38212
26}
27
28define i32 @retimm_i32() {
29 ; CHECK: retimm_i32:
30 ; CHECK: add
31 ; CHECK-NEXT: rtsd
32 ; FPU: retimm_i32:
33 ; FPU: add
34 ; FPU-NEXT: rtsd
35 ret i32 2938128
36}
37
38define i64 @retimm_i64() {
39 ; CHECK: retimm_i64:
40 ; CHECK: add
Wesley Peck60e71272010-10-21 03:34:22 +000041 ; CHECK-NEXT: rtsd
Wesley Peck4e9141f2010-10-21 03:57:26 +000042 ; CHECK-NEXT: add
Wesley Pecka70f28c2010-02-23 19:15:24 +000043 ; FPU: retimm_i64:
44 ; FPU: add
Wesley Peck60e71272010-10-21 03:34:22 +000045 ; FPU-NEXT: rtsd
Wesley Peck4e9141f2010-10-21 03:57:26 +000046 ; FPU-NEXT: add
Wesley Pecka70f28c2010-02-23 19:15:24 +000047 ret i64 94581823
48}
49
50define float @retimm_float() {
51 ; CHECK: retimm_float:
52 ; CHECK: add
53 ; CHECK-NEXT: rtsd
54 ; FPU: retimm_float:
55 ; FPU: or
Wesley Peck4e9141f2010-10-21 03:57:26 +000056 ; FPU-NEXT: rtsd
Wesley Pecka70f28c2010-02-23 19:15:24 +000057 ret float 12.0
58}
59
60define double @retimm_double() {
61 ; CHECK: retimm_double:
62 ; CHECK: add
63 ; CHECK-NEXT: add
64 ; CHECK-NEXT: rtsd
65 ; FPU: retimm_double:
66 ; FPU: add
67 ; FPU-NEXT: add
68 ; FPU-NEXT: rtsd
69 ret double 598382.39283873
70}