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Dan Gohman6f0d0242008-02-10 18:45:23 +00001//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
Misha Brukmanf976c852005-04-21 22:55:34 +00002//
John Criswellb576c942003-10-20 19:43:21 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanf976c852005-04-21 22:55:34 +00007//
John Criswellb576c942003-10-20 19:43:21 +00008//===----------------------------------------------------------------------===//
Chris Lattner9208bbf2002-12-17 04:03:08 +00009//
Dan Gohman6f0d0242008-02-10 18:45:23 +000010// This file implements the TargetRegisterInfo interface.
Chris Lattner9208bbf2002-12-17 04:03:08 +000011//
12//===----------------------------------------------------------------------===//
13
Jim Laskey6b59a362006-08-03 17:27:09 +000014#include "llvm/Target/TargetMachine.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +000015#include "llvm/Target/TargetRegisterInfo.h"
Jim Laskey6b59a362006-08-03 17:27:09 +000016#include "llvm/Target/TargetFrameInfo.h"
Jim Laskeya9979182006-03-28 13:48:33 +000017#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Cheng61de82d2007-02-15 05:59:24 +000019#include "llvm/ADT/BitVector.h"
Jim Laskeya9979182006-03-28 13:48:33 +000020
Chris Lattner20ea0622006-02-01 18:10:56 +000021using namespace llvm;
Brian Gaeked0fde302003-11-11 22:41:34 +000022
Dan Gohman6f0d0242008-02-10 18:45:23 +000023TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
Chris Lattner3ad76422002-12-28 20:34:18 +000024 regclass_iterator RCB, regclass_iterator RCE,
Jakob Stoklund Olesen1fc8e752010-05-25 19:49:38 +000025 const char *const *subregindexnames,
Owen Anderson605041e2008-07-01 17:34:38 +000026 int CFSO, int CFDO,
Bill Wendling51b16f42009-05-30 01:09:53 +000027 const unsigned* subregs, const unsigned subregsize,
Bill Wendling51b16f42009-05-30 01:09:53 +000028 const unsigned* aliases, const unsigned aliasessize)
Owen Anderson7d770be2009-04-09 03:50:16 +000029 : SubregHash(subregs), SubregHashSize(subregsize),
Owen Anderson3ca15c92009-04-09 22:19:30 +000030 AliasesHash(aliases), AliasesHashSize(aliasessize),
Jakob Stoklund Olesen1fc8e752010-05-25 19:49:38 +000031 Desc(D), SubRegIndexNames(subregindexnames), NumRegs(NR),
32 RegClassBegin(RCB), RegClassEnd(RCE) {
Chris Lattner9208bbf2002-12-17 04:03:08 +000033 assert(NumRegs < FirstVirtualRegister &&
34 "Target has too many physical registers!");
35
Chris Lattner3ad76422002-12-28 20:34:18 +000036 CallFrameSetupOpcode = CFSO;
37 CallFrameDestroyOpcode = CFDO;
Chris Lattner9208bbf2002-12-17 04:03:08 +000038}
39
Dan Gohman6f0d0242008-02-10 18:45:23 +000040TargetRegisterInfo::~TargetRegisterInfo() {}
Nate Begeman0aafc322004-10-27 06:00:53 +000041
Evan Cheng42d60272007-09-26 21:36:17 +000042/// getPhysicalRegisterRegClass - Returns the Register Class of a physical
Owen Andersone50ed302009-08-10 22:56:29 +000043/// register of the given type. If type is EVT::Other, then just return any
Evan Cheng676dd7c2008-03-11 07:19:34 +000044/// register class the register belongs to.
Evan Cheng42d60272007-09-26 21:36:17 +000045const TargetRegisterClass *
Owen Andersone50ed302009-08-10 22:56:29 +000046TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const {
Evan Cheng42d60272007-09-26 21:36:17 +000047 assert(isPhysicalRegister(reg) && "reg must be a physical register");
Evan Chengfa2f7862008-03-11 07:54:14 +000048
Dan Gohman4893c062008-09-21 21:01:49 +000049 // Pick the most super register class of the right type that contains
50 // this physreg.
51 const TargetRegisterClass* BestRC = 0;
Evan Cheng682f8102008-04-25 17:21:40 +000052 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
Dan Gohman4893c062008-09-21 21:01:49 +000053 const TargetRegisterClass* RC = *I;
Owen Anderson825b72b2009-08-11 20:47:22 +000054 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
Dan Gohman4893c062008-09-21 21:01:49 +000055 (!BestRC || BestRC->hasSuperClass(RC)))
56 BestRC = RC;
Evan Chengfa2f7862008-03-11 07:54:14 +000057 }
58
Dan Gohman4893c062008-09-21 21:01:49 +000059 assert(BestRC && "Couldn't find the register class");
60 return BestRC;
Evan Cheng42d60272007-09-26 21:36:17 +000061}
62
Rafael Espindolace48c1d2010-06-02 12:39:06 +000063/// getMinimalPhysRegClass - Returns the Register Class of a physical
Dan Gohmanc2af8692010-07-06 15:31:55 +000064/// register of the given type, picking the most sub register class of
65/// the right type that contains this physreg.
Rafael Espindolace48c1d2010-06-02 12:39:06 +000066const TargetRegisterClass *
Rafael Espindolad31f9722010-06-29 14:02:34 +000067TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
Rafael Espindolace48c1d2010-06-02 12:39:06 +000068 assert(isPhysicalRegister(reg) && "reg must be a physical register");
69
70 // Pick the most sub register class of the right type that contains
71 // this physreg.
72 const TargetRegisterClass* BestRC = 0;
73 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
74 const TargetRegisterClass* RC = *I;
Rafael Espindolad31f9722010-06-29 14:02:34 +000075 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
76 (!BestRC || BestRC->hasSubClass(RC)))
Rafael Espindolace48c1d2010-06-02 12:39:06 +000077 BestRC = RC;
78 }
79
80 assert(BestRC && "Couldn't find the register class");
81 return BestRC;
82}
83
Evan Cheng7be63682007-04-17 23:33:39 +000084/// getAllocatableSetForRC - Toggle the bits that represent allocatable
85/// registers for the specific register class.
Dan Gohman769b7f82009-10-09 22:09:05 +000086static void getAllocatableSetForRC(const MachineFunction &MF,
Evan Cheng7be63682007-04-17 23:33:39 +000087 const TargetRegisterClass *RC, BitVector &R){
88 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
89 E = RC->allocation_order_end(MF); I != E; ++I)
90 R.set(*I);
91}
92
Dan Gohman769b7f82009-10-09 22:09:05 +000093BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
Dan Gohman6f0d0242008-02-10 18:45:23 +000094 const TargetRegisterClass *RC) const {
Evan Cheng61de82d2007-02-15 05:59:24 +000095 BitVector Allocatable(NumRegs);
Evan Cheng7be63682007-04-17 23:33:39 +000096 if (RC) {
97 getAllocatableSetForRC(MF, RC, Allocatable);
98 return Allocatable;
Alkis Evlogimenosbb4bdf42004-08-26 22:21:04 +000099 }
Evan Cheng7be63682007-04-17 23:33:39 +0000100
Dan Gohman6f0d0242008-02-10 18:45:23 +0000101 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
Evan Cheng7be63682007-04-17 23:33:39 +0000102 E = regclass_end(); I != E; ++I)
103 getAllocatableSetForRC(MF, *I, Allocatable);
Alkis Evlogimenosbb4bdf42004-08-26 22:21:04 +0000104 return Allocatable;
Misha Brukmanf976c852005-04-21 22:55:34 +0000105}
Jim Laskeya9979182006-03-28 13:48:33 +0000106
Evan Cheng72bebb92008-01-31 03:37:28 +0000107/// getFrameIndexOffset - Returns the displacement from the frame register to
108/// the stack frame of the specified index. This is the default implementation
Bob Wilson959b0022009-09-23 20:57:02 +0000109/// which is overridden for some targets.
Chris Lattner30c6b752010-01-26 23:15:09 +0000110int TargetRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
111 int FI) const {
Jim Laskey6b59a362006-08-03 17:27:09 +0000112 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
Chris Lattner30c6b752010-01-26 23:15:09 +0000113 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng72bebb92008-01-31 03:37:28 +0000114 return MFI->getObjectOffset(FI) + MFI->getStackSize() -
115 TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
Jim Laskeya9979182006-03-28 13:48:33 +0000116}
Jim Laskey41886992006-04-07 16:34:46 +0000117
118/// getInitialFrameState - Returns a list of machine moves that are assumed
119/// on entry to a function.
120void
Chris Lattner30c6b752010-01-26 23:15:09 +0000121TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const{
Jim Laskey41886992006-04-07 16:34:46 +0000122 // Default is to do nothing.
123}
124
Jakob Stoklund Olesenba67d872009-04-30 21:23:32 +0000125const TargetRegisterClass *
126llvm::getCommonSubClass(const TargetRegisterClass *A,
127 const TargetRegisterClass *B) {
128 // First take care of the trivial cases
129 if (A == B)
130 return A;
131 if (!A || !B)
132 return 0;
133
134 // If B is a subclass of A, it will be handled in the loop below
135 if (B->hasSubClass(A))
136 return A;
137
138 const TargetRegisterClass *Best = 0;
139 for (TargetRegisterClass::sc_iterator I = A->subclasses_begin();
140 const TargetRegisterClass *X = *I; ++I) {
141 if (X == B)
142 return B; // B is a subclass of A
143
144 // X must be a common subclass of A and B
145 if (!B->hasSubClass(X))
146 continue;
147
148 // A superclass is definitely better.
149 if (!Best || Best->hasSuperClass(X)) {
150 Best = X;
151 continue;
152 }
153
154 // A subclass is definitely worse
155 if (Best->hasSubClass(X))
156 continue;
157
158 // Best and *I have no super/sub class relation - pick the larger class, or
159 // the smaller spill size.
160 int nb = std::distance(Best->begin(), Best->end());
161 int ni = std::distance(X->begin(), X->end());
162 if (ni>nb || (ni==nb && X->getSize() < Best->getSize()))
163 Best = X;
164 }
165 return Best;
166}