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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 52d0001cfc7cc83c69f20430cf9039a798adc10b / . / lib / Target / CellSPU / SPUInstrInfo.h
blob: bc57e155e535e84f4c66f7f6882fe8e3de6a4b55 [file] [log] [blame]
Scott Michel66377522007-12-04 22:35:58 +0000[diff] [blame]1//===- SPUInstrInfo.h - Cell SPU Instruction Information --------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Scott Michel66377522007-12-04 22:35:58 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
Scott Michel2466c372007-12-05 01:40:25 +0000[diff] [blame]10// This file contains the CellSPU implementation of the TargetInstrInfo class.
Scott Michel66377522007-12-04 22:35:58 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
14#ifndef SPU_INSTRUCTIONINFO_H
15#define SPU_INSTRUCTIONINFO_H
16
17#include "SPU.h"
18#include "llvm/Target/TargetInstrInfo.h"
19#include "SPURegisterInfo.h"
20
21namespace llvm {
22 //! Cell SPU instruction information class
Chris Lattner64105522008-01-01 01:03:04 +0000[diff] [blame]23 class SPUInstrInfo : public TargetInstrInfoImpl {
Scott Michel66377522007-12-04 22:35:58 +0000[diff] [blame]24 SPUTargetMachine &TM;
25 const SPURegisterInfo RI;
Scott Michel52d00012009-01-03 00:27:53 +0000[diff] [blame^]26 protected:
27 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
28 MachineInstr* MI,
29 const SmallVectorImpl<unsigned> &Ops,
30 int FrameIndex) const;
31
32 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
33 MachineInstr* MI,
34 const SmallVectorImpl<unsigned> &Ops,
35 MachineInstr* LoadMI) const {
36 return 0;
37 }
38
Scott Michel66377522007-12-04 22:35:58 +0000[diff] [blame]39 public:
Dan Gohman950a4c42008-03-25 22:06:05 +0000[diff] [blame]40 explicit SPUInstrInfo(SPUTargetMachine &tm);
Scott Michel66377522007-12-04 22:35:58 +0000[diff] [blame]41
42 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
43 /// such, whenever a client has an instance of instruction info, it should
44 /// always be able to get register info as well (through this method).
45 ///
Dan Gohmanc9f5f3f2008-05-14 01:58:56 +0000[diff] [blame]46 virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
Scott Michel66377522007-12-04 22:35:58 +0000[diff] [blame]47
48 /// getPointerRegClass - Return the register class to use to hold pointers.
49 /// This is used for addressing modes.
Scott Michel52d00012009-01-03 00:27:53 +0000[diff] [blame^]50 virtual const TargetRegisterClass *getPointerRegClass() const;
Scott Michel66377522007-12-04 22:35:58 +0000[diff] [blame]51
52 // Return true if the instruction is a register to register move and
53 // leave the source and dest operands in the passed parameters.
54 //
55 virtual bool isMoveInstr(const MachineInstr& MI,
Scott Michel7f9ba9b2008-01-30 02:55:46 +0000[diff] [blame]56 unsigned& sourceReg,
57 unsigned& destReg) const;
Scott Michel66377522007-12-04 22:35:58 +0000[diff] [blame]58
Dan Gohmancbad42c2008-11-18 19:49:32 +0000[diff] [blame]59 unsigned isLoadFromStackSlot(const MachineInstr *MI,
60 int &FrameIndex) const;
61 unsigned isStoreToStackSlot(const MachineInstr *MI,
62 int &FrameIndex) const;
Scott Michel52d00012009-01-03 00:27:53 +0000[diff] [blame^]63
Owen Anderson940f83e2008-08-26 18:03:31 +0000[diff] [blame]64 virtual bool copyRegToReg(MachineBasicBlock &MBB,
Owen Andersond10fd972007-12-31 06:32:00 +0000[diff] [blame]65 MachineBasicBlock::iterator MI,
66 unsigned DestReg, unsigned SrcReg,
67 const TargetRegisterClass *DestRC,
68 const TargetRegisterClass *SrcRC) const;
Scott Michel52d00012009-01-03 00:27:53 +0000[diff] [blame^]69
Owen Andersonf6372aa2008-01-01 21:11:32 +0000[diff] [blame]70 //! Store a register to a stack slot, based on its register class.
71 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator MBBI,
73 unsigned SrcReg, bool isKill, int FrameIndex,
74 const TargetRegisterClass *RC) const;
75
76 //! Store a register to an address, based on its register class
77 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
Scott Michel7f9ba9b2008-01-30 02:55:46 +0000[diff] [blame]78 SmallVectorImpl<MachineOperand> &Addr,
79 const TargetRegisterClass *RC,
80 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Owen Andersonf6372aa2008-01-01 21:11:32 +0000[diff] [blame]81
82 //! Load a register from a stack slot, based on its register class.
83 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MBBI,
85 unsigned DestReg, int FrameIndex,
86 const TargetRegisterClass *RC) const;
87
88 //! Loqad a register from an address, based on its register class
89 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Scott Michel7f9ba9b2008-01-30 02:55:46 +0000[diff] [blame]90 SmallVectorImpl<MachineOperand> &Addr,
91 const TargetRegisterClass *RC,
Owen Anderson43dbe052008-01-07 01:35:02 +0000[diff] [blame]92 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Owen Anderson43dbe052008-01-07 01:35:02 +0000[diff] [blame]93
Scott Michel52d00012009-01-03 00:27:53 +0000[diff] [blame^]94 //! Return true if the specified load or store can be folded
95 virtual
96 bool canFoldMemoryOperand(const MachineInstr *MI,
97 const SmallVectorImpl<unsigned> &Ops) const;
98
99 //! Return true if the specified block does not fall through
100 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
101
102 //! Reverses a branch's condition, returning false on success.
103 virtual
104 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
Scott Michelaedc6372008-12-10 00:15:19 +0000[diff] [blame]105
106 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
107 MachineBasicBlock *&FBB,
108 SmallVectorImpl<MachineOperand> &Cond) const;
Scott Michel52d00012009-01-03 00:27:53 +0000[diff] [blame^]109
Scott Michelaedc6372008-12-10 00:15:19 +0000[diff] [blame]110 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
Scott Michel52d00012009-01-03 00:27:53 +0000[diff] [blame^]111
Scott Michelaedc6372008-12-10 00:15:19 +0000[diff] [blame]112 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
113 MachineBasicBlock *FBB,
114 const SmallVectorImpl<MachineOperand> &Cond) const;
115 };
Scott Michel66377522007-12-04 22:35:58 +0000[diff] [blame]116}
117
118#endif