David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1 | //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file implements a simple register coalescing pass that attempts to |
| 11 | // aggressively coalesce every register copy that it can. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Evan Cheng | 3b1f55e | 2007-07-31 22:37:44 +0000 | [diff] [blame] | 15 | #define DEBUG_TYPE "regcoalescing" |
Evan Cheng | a461c4d | 2007-11-05 17:41:38 +0000 | [diff] [blame] | 16 | #include "SimpleRegisterCoalescing.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 17 | #include "VirtRegMap.h" |
Evan Cheng | a461c4d | 2007-11-05 17:41:38 +0000 | [diff] [blame] | 18 | #include "llvm/CodeGen/LiveIntervalAnalysis.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 19 | #include "llvm/Value.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/LiveVariables.h" |
| 21 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 22 | #include "llvm/CodeGen/MachineInstr.h" |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineLoopInfo.h" |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 24 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/Passes.h" |
David Greene | 2c17c4d | 2007-09-06 16:18:45 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/RegisterCoalescer.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 27 | #include "llvm/Target/TargetInstrInfo.h" |
| 28 | #include "llvm/Target/TargetMachine.h" |
| 29 | #include "llvm/Support/CommandLine.h" |
| 30 | #include "llvm/Support/Debug.h" |
| 31 | #include "llvm/ADT/SmallSet.h" |
| 32 | #include "llvm/ADT/Statistic.h" |
| 33 | #include "llvm/ADT/STLExtras.h" |
| 34 | #include <algorithm> |
| 35 | #include <cmath> |
| 36 | using namespace llvm; |
| 37 | |
| 38 | STATISTIC(numJoins , "Number of interval joins performed"); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 39 | STATISTIC(numCommutes , "Number of instruction commuting performed"); |
| 40 | STATISTIC(numExtends , "Number of copies extended"); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 41 | STATISTIC(numPeep , "Number of identity moves eliminated after coalescing"); |
| 42 | STATISTIC(numAborts , "Number of times interval joining aborted"); |
| 43 | |
| 44 | char SimpleRegisterCoalescing::ID = 0; |
| 45 | namespace { |
| 46 | static cl::opt<bool> |
| 47 | EnableJoining("join-liveintervals", |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 48 | cl::desc("Coalesce copies (default=true)"), |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 49 | cl::init(true)); |
| 50 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 51 | static cl::opt<bool> |
| 52 | NewHeuristic("new-coalescer-heuristic", |
| 53 | cl::desc("Use new coalescer heuristic"), |
| 54 | cl::init(false)); |
| 55 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 56 | static cl::opt<bool> |
| 57 | CommuteDef("coalescer-commute-instrs", |
| 58 | cl::init(false), cl::Hidden); |
| 59 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 60 | RegisterPass<SimpleRegisterCoalescing> |
Chris Lattner | e76fad2 | 2007-08-05 18:45:33 +0000 | [diff] [blame] | 61 | X("simple-register-coalescing", "Simple Register Coalescing"); |
David Greene | 2c17c4d | 2007-09-06 16:18:45 +0000 | [diff] [blame] | 62 | |
| 63 | // Declare that we implement the RegisterCoalescer interface |
| 64 | RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | const PassInfo *llvm::SimpleRegisterCoalescingID = X.getPassInfo(); |
| 68 | |
| 69 | void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 70 | AU.addPreserved<LiveIntervals>(); |
Bill Wendling | 67d65bb | 2008-01-04 20:54:55 +0000 | [diff] [blame] | 71 | AU.addPreserved<MachineLoopInfo>(); |
| 72 | AU.addPreservedID(MachineDominatorsID); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 73 | AU.addPreservedID(PHIEliminationID); |
| 74 | AU.addPreservedID(TwoAddressInstructionPassID); |
| 75 | AU.addRequired<LiveVariables>(); |
| 76 | AU.addRequired<LiveIntervals>(); |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 77 | AU.addRequired<MachineLoopInfo>(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 78 | MachineFunctionPass::getAnalysisUsage(AU); |
| 79 | } |
| 80 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 81 | /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 82 | /// being the source and IntB being the dest, thus this defines a value number |
| 83 | /// in IntB. If the source value number (in IntA) is defined by a copy from B, |
| 84 | /// see if we can merge these two pieces of B into a single value number, |
| 85 | /// eliminating a copy. For example: |
| 86 | /// |
| 87 | /// A3 = B0 |
| 88 | /// ... |
| 89 | /// B1 = A3 <- this copy |
| 90 | /// |
| 91 | /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1 |
| 92 | /// value number to be replaced with B0 (which simplifies the B liveinterval). |
| 93 | /// |
| 94 | /// This returns true if an interval was modified. |
| 95 | /// |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 96 | bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, |
| 97 | LiveInterval &IntB, |
| 98 | MachineInstr *CopyMI) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 99 | unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); |
| 100 | |
| 101 | // BValNo is a value number in B that is defined by a copy from A. 'B3' in |
| 102 | // the example above. |
| 103 | LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 104 | VNInfo *BValNo = BLR->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 105 | |
| 106 | // Get the location that B is defined at. Two options: either this value has |
| 107 | // an unknown definition point or it is defined at CopyIdx. If unknown, we |
| 108 | // can't process it. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 109 | if (!BValNo->copy) return false; |
| 110 | assert(BValNo->def == CopyIdx && "Copy doesn't define the value?"); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 111 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 112 | // AValNo is the value number in A that defines the copy, A3 in the example. |
| 113 | LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1); |
| 114 | VNInfo *AValNo = ALR->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 115 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 116 | // If AValNo is defined as a copy from IntB, we can potentially process this. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 117 | // Get the instruction that defines this value number. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 118 | unsigned SrcReg = li_->getVNInfoSourceReg(AValNo); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 119 | if (!SrcReg) return false; // Not defined by a copy. |
| 120 | |
| 121 | // If the value number is not defined by a copy instruction, ignore it. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 122 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 123 | // If the source register comes from an interval other than IntB, we can't |
| 124 | // handle this. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 125 | if (SrcReg != IntB.reg) return false; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 126 | |
| 127 | // Get the LiveRange in IntB that this value number starts with. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 128 | LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 129 | |
| 130 | // Make sure that the end of the live range is inside the same block as |
| 131 | // CopyMI. |
| 132 | MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1); |
| 133 | if (!ValLREndInst || |
| 134 | ValLREndInst->getParent() != CopyMI->getParent()) return false; |
| 135 | |
| 136 | // Okay, we now know that ValLR ends in the same block that the CopyMI |
| 137 | // live-range starts. If there are no intervening live ranges between them in |
| 138 | // IntB, we can merge them. |
| 139 | if (ValLR+1 != BLR) return false; |
Evan Cheng | dc5294f | 2007-08-14 23:19:28 +0000 | [diff] [blame] | 140 | |
| 141 | // If a live interval is a physical register, conservatively check if any |
| 142 | // of its sub-registers is overlapping the live interval of the virtual |
| 143 | // register. If so, do not coalesce. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 144 | if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) && |
| 145 | *tri_->getSubRegisters(IntB.reg)) { |
| 146 | for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) |
Evan Cheng | dc5294f | 2007-08-14 23:19:28 +0000 | [diff] [blame] | 147 | if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) { |
| 148 | DOUT << "Interfere with sub-register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 149 | DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); |
Evan Cheng | dc5294f | 2007-08-14 23:19:28 +0000 | [diff] [blame] | 150 | return false; |
| 151 | } |
| 152 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 153 | |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 154 | DOUT << "\nExtending: "; IntB.print(DOUT, tri_); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 155 | |
Evan Cheng | a8d94f1 | 2007-08-07 23:49:57 +0000 | [diff] [blame] | 156 | unsigned FillerStart = ValLR->end, FillerEnd = BLR->start; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 157 | // We are about to delete CopyMI, so need to remove it as the 'instruction |
Evan Cheng | a8d94f1 | 2007-08-07 23:49:57 +0000 | [diff] [blame] | 158 | // that defines this value #'. Update the the valnum with the new defining |
| 159 | // instruction #. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 160 | BValNo->def = FillerStart; |
| 161 | BValNo->copy = NULL; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 162 | |
| 163 | // Okay, we can merge them. We need to insert a new liverange: |
| 164 | // [ValLR.end, BLR.begin) of either value number, then we merge the |
| 165 | // two value numbers. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 166 | IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo)); |
| 167 | |
| 168 | // If the IntB live range is assigned to a physical register, and if that |
| 169 | // physreg has aliases, |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 170 | if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 171 | // Update the liveintervals of sub-registers. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 172 | for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 173 | LiveInterval &AliasLI = li_->getInterval(*AS); |
| 174 | AliasLI.addRange(LiveRange(FillerStart, FillerEnd, |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 175 | AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator()))); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 176 | } |
| 177 | } |
| 178 | |
| 179 | // Okay, merge "B1" into the same value number as "B0". |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 180 | if (BValNo != ValLR->valno) |
| 181 | IntB.MergeValueNumberInto(BValNo, ValLR->valno); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 182 | DOUT << " result = "; IntB.print(DOUT, tri_); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 183 | DOUT << "\n"; |
| 184 | |
| 185 | // If the source instruction was killing the source register before the |
| 186 | // merge, unset the isKill marker given the live range has been extended. |
| 187 | int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true); |
| 188 | if (UIdx != -1) |
Chris Lattner | f738230 | 2007-12-30 21:56:09 +0000 | [diff] [blame] | 189 | ValLREndInst->getOperand(UIdx).setIsKill(false); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 190 | |
| 191 | ++numExtends; |
| 192 | return true; |
| 193 | } |
| 194 | |
Evan Cheng | 559f422 | 2008-02-16 02:32:17 +0000 | [diff] [blame^] | 195 | /// HasOtherReachingDefs - Return true if there are definitions of IntB |
| 196 | /// other than BValNo val# that can reach uses of AValno val# of IntA. |
| 197 | bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA, |
| 198 | LiveInterval &IntB, |
| 199 | VNInfo *AValNo, |
| 200 | VNInfo *BValNo) { |
| 201 | for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end(); |
| 202 | AI != AE; ++AI) { |
| 203 | if (AI->valno != AValNo) continue; |
| 204 | LiveInterval::Ranges::iterator BI = |
| 205 | std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start); |
| 206 | if (BI != IntB.ranges.begin()) |
| 207 | --BI; |
| 208 | for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) { |
| 209 | if (BI->valno == BValNo) |
| 210 | continue; |
| 211 | if (BI->start <= AI->start && BI->end > AI->start) |
| 212 | return true; |
| 213 | if (BI->start > AI->start && BI->start < AI->end) |
| 214 | return true; |
| 215 | } |
| 216 | } |
| 217 | return false; |
| 218 | } |
| 219 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 220 | /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA |
| 221 | /// being the source and IntB being the dest, thus this defines a value number |
| 222 | /// in IntB. If the source value number (in IntA) is defined by a commutable |
| 223 | /// instruction and its other operand is coalesced to the copy dest register, |
| 224 | /// see if we can transform the copy into a noop by commuting the definition. For |
| 225 | /// example, |
| 226 | /// |
| 227 | /// A3 = op A2 B0<kill> |
| 228 | /// ... |
| 229 | /// B1 = A3 <- this copy |
| 230 | /// ... |
| 231 | /// = op A3 <- more uses |
| 232 | /// |
| 233 | /// ==> |
| 234 | /// |
| 235 | /// B2 = op B0 A2<kill> |
| 236 | /// ... |
| 237 | /// B1 = B2 <- now an identify copy |
| 238 | /// ... |
| 239 | /// = op B2 <- more uses |
| 240 | /// |
| 241 | /// This returns true if an interval was modified. |
| 242 | /// |
| 243 | bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, |
| 244 | LiveInterval &IntB, |
| 245 | MachineInstr *CopyMI) { |
| 246 | if (!CommuteDef) return false; |
| 247 | |
| 248 | unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); |
| 249 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 250 | // BValNo is a value number in B that is defined by a copy from A. 'B3' in |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 251 | // the example above. |
| 252 | LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); |
| 253 | VNInfo *BValNo = BLR->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 254 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 255 | // Get the location that B is defined at. Two options: either this value has |
| 256 | // an unknown definition point or it is defined at CopyIdx. If unknown, we |
| 257 | // can't process it. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 258 | if (!BValNo->copy) return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 259 | assert(BValNo->def == CopyIdx && "Copy doesn't define the value?"); |
| 260 | |
| 261 | // AValNo is the value number in A that defines the copy, A3 in the example. |
| 262 | LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1); |
| 263 | VNInfo *AValNo = ALR->valno; |
Evan Cheng | e35a6d1 | 2008-02-13 08:41:08 +0000 | [diff] [blame] | 264 | // If other defs can reach uses of this def, then it's not safe to perform |
| 265 | // the optimization. |
| 266 | if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill) |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 267 | return false; |
| 268 | MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def); |
| 269 | const TargetInstrDesc &TID = DefMI->getDesc(); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 270 | unsigned NewDstIdx; |
| 271 | if (!TID.isCommutable() || |
| 272 | !tii_->CommuteChangesDestination(DefMI, NewDstIdx)) |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 273 | return false; |
| 274 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 275 | MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); |
| 276 | unsigned NewReg = NewDstMO.getReg(); |
| 277 | if (NewReg != IntB.reg || !NewDstMO.isKill()) |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 278 | return false; |
| 279 | |
| 280 | // Make sure there are no other definitions of IntB that would reach the |
| 281 | // uses which the new definition can reach. |
Evan Cheng | 559f422 | 2008-02-16 02:32:17 +0000 | [diff] [blame^] | 282 | if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo)) |
| 283 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 284 | |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 285 | // At this point we have decided that it is legal to do this |
| 286 | // transformation. Start by commuting the instruction. |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 287 | MachineBasicBlock *MBB = DefMI->getParent(); |
| 288 | MachineInstr *NewMI = tii_->commuteInstruction(DefMI); |
Evan Cheng | 559f422 | 2008-02-16 02:32:17 +0000 | [diff] [blame^] | 289 | if (!NewMI) |
| 290 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 291 | if (NewMI != DefMI) { |
| 292 | li_->ReplaceMachineInstrInMaps(DefMI, NewMI); |
| 293 | MBB->insert(DefMI, NewMI); |
| 294 | MBB->erase(DefMI); |
| 295 | } |
| 296 | unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg); |
| 297 | NewMI->getOperand(OpIdx).setIsKill(); |
| 298 | |
| 299 | // Update uses of IntA of the specific Val# with IntB. |
| 300 | bool BHasPHIKill = BValNo->hasPHIKill; |
| 301 | SmallVector<VNInfo*, 4> BDeadValNos; |
| 302 | SmallVector<unsigned, 4> BKills; |
| 303 | std::map<unsigned, unsigned> BExtend; |
| 304 | for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg), |
| 305 | UE = mri_->use_end(); UI != UE;) { |
| 306 | MachineOperand &UseMO = UI.getOperand(); |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 307 | MachineInstr *UseMI = &*UI; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 308 | ++UI; |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 309 | if (JoinedCopies.count(UseMI)) |
| 310 | continue; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 311 | unsigned UseIdx = li_->getInstructionIndex(UseMI); |
| 312 | LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); |
| 313 | if (ULR->valno != AValNo) |
| 314 | continue; |
| 315 | UseMO.setReg(NewReg); |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 316 | if (UseMI == CopyMI) |
| 317 | continue; |
Evan Cheng | bd3e5aa | 2008-02-15 21:36:51 +0000 | [diff] [blame] | 318 | if (UseMO.isKill()) |
| 319 | BKills.push_back(li_->getUseIndex(UseIdx)+1); |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 320 | unsigned SrcReg, DstReg; |
| 321 | if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) |
| 322 | continue; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 323 | if (DstReg == IntB.reg) { |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 324 | // This copy will become a noop. If it's defining a new val#, |
| 325 | // remove that val# as well. However this live range is being |
| 326 | // extended to the end of the existing live range defined by the copy. |
| 327 | unsigned DefIdx = li_->getDefIndex(UseIdx); |
| 328 | LiveInterval::iterator DLR = IntB.FindLiveRangeContaining(DefIdx); |
| 329 | BHasPHIKill |= DLR->valno->hasPHIKill; |
| 330 | assert(DLR->valno->def == DefIdx); |
| 331 | BDeadValNos.push_back(DLR->valno); |
| 332 | BExtend[DLR->start] = DLR->end; |
| 333 | JoinedCopies.insert(UseMI); |
| 334 | // If this is a kill but it's going to be removed, the last use |
| 335 | // of the same val# is the new kill. |
| 336 | if (UseMO.isKill()) { |
| 337 | BKills.pop_back(); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 338 | } |
| 339 | } |
| 340 | } |
| 341 | |
| 342 | // We need to insert a new liverange: [ALR.start, LastUse). It may be we can |
| 343 | // simply extend BLR if CopyMI doesn't end the range. |
| 344 | DOUT << "\nExtending: "; IntB.print(DOUT, tri_); |
| 345 | |
| 346 | IntB.removeValNo(BValNo); |
| 347 | for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) |
| 348 | IntB.removeValNo(BDeadValNos[i]); |
| 349 | VNInfo *ValNo = IntB.getNextValue(ALR->start, 0, li_->getVNInfoAllocator()); |
| 350 | for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end(); |
| 351 | AI != AE; ++AI) { |
| 352 | if (AI->valno != AValNo) continue; |
| 353 | unsigned End = AI->end; |
| 354 | std::map<unsigned, unsigned>::iterator EI = BExtend.find(End); |
| 355 | if (EI != BExtend.end()) |
| 356 | End = EI->second; |
| 357 | IntB.addRange(LiveRange(AI->start, End, ValNo)); |
| 358 | } |
| 359 | IntB.addKills(ValNo, BKills); |
| 360 | ValNo->hasPHIKill = BHasPHIKill; |
| 361 | |
| 362 | DOUT << " result = "; IntB.print(DOUT, tri_); |
| 363 | DOUT << "\n"; |
| 364 | |
| 365 | DOUT << "\nShortening: "; IntA.print(DOUT, tri_); |
| 366 | IntA.removeValNo(AValNo); |
| 367 | DOUT << " result = "; IntA.print(DOUT, tri_); |
| 368 | DOUT << "\n"; |
| 369 | |
| 370 | ++numCommutes; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 371 | return true; |
| 372 | } |
| 373 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 374 | /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate |
| 375 | /// due to live range lengthening as the result of coalescing. |
| 376 | void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg, |
| 377 | LiveInterval &LI) { |
| 378 | for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg), |
| 379 | UE = mri_->use_end(); UI != UE; ++UI) { |
| 380 | MachineOperand &UseMO = UI.getOperand(); |
| 381 | if (UseMO.isKill()) { |
| 382 | MachineInstr *UseMI = UseMO.getParent(); |
| 383 | unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI)); |
| 384 | if (JoinedCopies.count(UseMI)) |
| 385 | continue; |
| 386 | LiveInterval::const_iterator UI = LI.FindLiveRangeContaining(UseIdx); |
| 387 | assert(UI != LI.end()); |
| 388 | if (!LI.isKill(UI->valno, UseIdx+1)) |
| 389 | UseMO.setIsKill(false); |
| 390 | } |
Evan Cheng | 4ae31a5 | 2007-10-18 07:49:59 +0000 | [diff] [blame] | 391 | } |
| 392 | } |
| 393 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 394 | /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy. |
| 395 | /// |
| 396 | bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI, |
| 397 | unsigned DstReg) { |
| 398 | MachineBasicBlock *MBB = CopyMI->getParent(); |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 399 | const MachineLoop *L = loopInfo->getLoopFor(MBB); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 400 | if (!L) |
| 401 | return false; |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 402 | if (MBB != L->getLoopLatch()) |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 403 | return false; |
| 404 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 405 | LiveInterval &LI = li_->getInterval(DstReg); |
| 406 | unsigned DefIdx = li_->getInstructionIndex(CopyMI); |
| 407 | LiveInterval::const_iterator DstLR = |
| 408 | LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx)); |
| 409 | if (DstLR == LI.end()) |
| 410 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 411 | unsigned KillIdx = li_->getInstructionIndex(&MBB->back()) + InstrSlots::NUM; |
| 412 | if (DstLR->valno->kills.size() == 1 && |
| 413 | DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill) |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 414 | return true; |
| 415 | return false; |
| 416 | } |
| 417 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 418 | /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and |
| 419 | /// update the subregister number if it is not zero. If DstReg is a |
| 420 | /// physical register and the existing subregister number of the def / use |
| 421 | /// being updated is not zero, make sure to set it to the correct physical |
| 422 | /// subregister. |
| 423 | void |
| 424 | SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, |
| 425 | unsigned SubIdx) { |
| 426 | bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); |
| 427 | if (DstIsPhys && SubIdx) { |
| 428 | // Figure out the real physical register we are updating with. |
| 429 | DstReg = tri_->getSubReg(DstReg, SubIdx); |
| 430 | SubIdx = 0; |
| 431 | } |
| 432 | |
| 433 | for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg), |
| 434 | E = mri_->reg_end(); I != E; ) { |
| 435 | MachineOperand &O = I.getOperand(); |
| 436 | ++I; |
| 437 | if (DstIsPhys) { |
| 438 | unsigned UseSubIdx = O.getSubReg(); |
| 439 | unsigned UseDstReg = DstReg; |
| 440 | if (UseSubIdx) |
| 441 | UseDstReg = tri_->getSubReg(DstReg, UseSubIdx); |
| 442 | O.setReg(UseDstReg); |
| 443 | O.setSubReg(0); |
| 444 | } else { |
| 445 | unsigned OldSubIdx = O.getSubReg(); |
| 446 | assert((!SubIdx || !OldSubIdx) && "Conflicting sub-register index!"); |
| 447 | if (SubIdx) |
| 448 | O.setSubReg(SubIdx); |
| 449 | O.setReg(DstReg); |
| 450 | } |
| 451 | } |
| 452 | } |
| 453 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 454 | /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, |
| 455 | /// which are the src/dst of the copy instruction CopyMI. This returns true |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 456 | /// if the copy was successfully coalesced away. If it is not currently |
| 457 | /// possible to coalesce this interval, but it may be possible if other |
| 458 | /// things get coalesced, then it returns true by reference in 'Again'. |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 459 | bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 460 | MachineInstr *CopyMI = TheCopy.MI; |
| 461 | |
| 462 | Again = false; |
| 463 | if (JoinedCopies.count(CopyMI)) |
| 464 | return false; // Already done. |
| 465 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 466 | DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI; |
| 467 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 468 | unsigned SrcReg; |
| 469 | unsigned DstReg; |
| 470 | bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG; |
| 471 | unsigned SubIdx = 0; |
| 472 | if (isExtSubReg) { |
| 473 | DstReg = CopyMI->getOperand(0).getReg(); |
| 474 | SrcReg = CopyMI->getOperand(1).getReg(); |
| 475 | } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) { |
| 476 | assert(0 && "Unrecognized copy instruction!"); |
| 477 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 478 | } |
| 479 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 480 | // If they are already joined we continue. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 481 | if (SrcReg == DstReg) { |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 482 | DOUT << "\tCopy already coalesced.\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 483 | return false; // Not coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 484 | } |
| 485 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 486 | bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); |
| 487 | bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 488 | |
| 489 | // If they are both physical registers, we cannot join them. |
| 490 | if (SrcIsPhys && DstIsPhys) { |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 491 | DOUT << "\tCan not coalesce physregs.\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 492 | return false; // Not coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 493 | } |
| 494 | |
| 495 | // We only join virtual registers with allocatable physical registers. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 496 | if (SrcIsPhys && !allocatableRegs_[SrcReg]) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 497 | DOUT << "\tSrc reg is unallocatable physreg.\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 498 | return false; // Not coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 499 | } |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 500 | if (DstIsPhys && !allocatableRegs_[DstReg]) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 501 | DOUT << "\tDst reg is unallocatable physreg.\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 502 | return false; // Not coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 503 | } |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 504 | |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 505 | unsigned RealDstReg = 0; |
| 506 | if (isExtSubReg) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 507 | SubIdx = CopyMI->getOperand(2).getImm(); |
| 508 | if (SrcIsPhys) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 509 | // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be |
| 510 | // coalesced with AX. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 511 | SrcReg = tri_->getSubReg(SrcReg, SubIdx); |
| 512 | SubIdx = 0; |
| 513 | } else if (DstIsPhys) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 514 | // If this is a extract_subreg where dst is a physical register, e.g. |
| 515 | // cl = EXTRACT_SUBREG reg1024, 1 |
| 516 | // then create and update the actual physical register allocated to RHS. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 517 | const TargetRegisterClass *RC = mri_->getRegClass(SrcReg); |
| 518 | for (const unsigned *SRs = tri_->getSuperRegisters(DstReg); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 519 | unsigned SR = *SRs; ++SRs) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 520 | if (DstReg == tri_->getSubReg(SR, SubIdx) && |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 521 | RC->contains(SR)) { |
| 522 | RealDstReg = SR; |
| 523 | break; |
| 524 | } |
| 525 | } |
| 526 | assert(RealDstReg && "Invalid extra_subreg instruction!"); |
| 527 | |
| 528 | // For this type of EXTRACT_SUBREG, conservatively |
| 529 | // check if the live interval of the source register interfere with the |
| 530 | // actual super physical register we are trying to coalesce with. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 531 | LiveInterval &RHS = li_->getInterval(SrcReg); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 532 | if (li_->hasInterval(RealDstReg) && |
| 533 | RHS.overlaps(li_->getInterval(RealDstReg))) { |
| 534 | DOUT << "Interfere with register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 535 | DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_)); |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 536 | return false; // Not coalescable |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 537 | } |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 538 | for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR) |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 539 | if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { |
| 540 | DOUT << "Interfere with sub-register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 541 | DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 542 | return false; // Not coalescable |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 543 | } |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 544 | SubIdx = 0; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 545 | } else { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 546 | unsigned SrcSize= li_->getInterval(SrcReg).getSize() / InstrSlots::NUM; |
| 547 | unsigned DstSize= li_->getInterval(DstReg).getSize() / InstrSlots::NUM; |
| 548 | const TargetRegisterClass *RC = mri_->getRegClass(DstReg); |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 549 | unsigned Threshold = allocatableRCRegs_[RC].count(); |
Evan Cheng | 52c7ff7 | 2007-10-12 09:15:53 +0000 | [diff] [blame] | 550 | // Be conservative. If both sides are virtual registers, do not coalesce |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 551 | // if this will cause a high use density interval to target a smaller set |
| 552 | // of registers. |
| 553 | if (DstSize > Threshold || SrcSize > Threshold) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 554 | LiveVariables::VarInfo &svi = lv_->getVarInfo(SrcReg); |
| 555 | LiveVariables::VarInfo &dvi = lv_->getVarInfo(DstReg); |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 556 | if ((float)dvi.NumUses / DstSize < (float)svi.NumUses / SrcSize) { |
| 557 | Again = true; // May be possible to coalesce later. |
| 558 | return false; |
| 559 | } |
| 560 | } |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 561 | } |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 562 | } else if (differingRegisterClasses(SrcReg, DstReg)) { |
| 563 | // FIXME: What if the resul of a EXTRACT_SUBREG is then coalesced |
| 564 | // with another? If it's the resulting destination register, then |
| 565 | // the subidx must be propagated to uses (but only those defined |
| 566 | // by the EXTRACT_SUBREG). If it's being coalesced into another |
| 567 | // register, it should be safe because register is assumed to have |
| 568 | // the register class of the super-register. |
| 569 | |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 570 | // If they are not of the same register class, we cannot join them. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 571 | DOUT << "\tSrc/Dest are different register classes.\n"; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 572 | // Allow the coalescer to try again in case either side gets coalesced to |
| 573 | // a physical register that's compatible with the other side. e.g. |
| 574 | // r1024 = MOV32to32_ r1025 |
| 575 | // but later r1024 is assigned EAX then r1025 may be coalesced with EAX. |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 576 | Again = true; // May be possible to coalesce later. |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 577 | return false; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 578 | } |
| 579 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 580 | LiveInterval &SrcInt = li_->getInterval(SrcReg); |
| 581 | LiveInterval &DstInt = li_->getInterval(DstReg); |
| 582 | assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg && |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 583 | "Register mapping is horribly broken!"); |
| 584 | |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 585 | DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_); |
| 586 | DOUT << " and "; DstInt.print(DOUT, tri_); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 587 | DOUT << ": "; |
| 588 | |
| 589 | // Check if it is necessary to propagate "isDead" property before intervals |
| 590 | // are joined. |
| 591 | MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg); |
| 592 | bool isDead = mopd->isDead(); |
| 593 | bool isShorten = false; |
| 594 | unsigned SrcStart = 0, RemoveStart = 0; |
| 595 | unsigned SrcEnd = 0, RemoveEnd = 0; |
| 596 | if (isDead) { |
| 597 | unsigned CopyIdx = li_->getInstructionIndex(CopyMI); |
| 598 | LiveInterval::iterator SrcLR = |
| 599 | SrcInt.FindLiveRangeContaining(li_->getUseIndex(CopyIdx)); |
| 600 | RemoveStart = SrcStart = SrcLR->start; |
| 601 | RemoveEnd = SrcEnd = SrcLR->end; |
| 602 | // The instruction which defines the src is only truly dead if there are |
| 603 | // no intermediate uses and there isn't a use beyond the copy. |
| 604 | // FIXME: find the last use, mark is kill and shorten the live range. |
| 605 | if (SrcEnd > li_->getDefIndex(CopyIdx)) { |
| 606 | isDead = false; |
| 607 | } else { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 608 | unsigned LastUseIdx; |
| 609 | MachineOperand *LastUse = |
| 610 | lastRegisterUse(SrcStart, CopyIdx, SrcReg, LastUseIdx); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 611 | if (LastUse) { |
| 612 | // Shorten the liveinterval to the end of last use. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 613 | LastUse->setIsKill(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 614 | isDead = false; |
| 615 | isShorten = true; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 616 | RemoveStart = li_->getDefIndex(LastUseIdx); |
| 617 | RemoveEnd = SrcEnd; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 618 | } else { |
| 619 | MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart); |
| 620 | if (SrcMI) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 621 | MachineOperand *mops = findDefOperand(SrcMI, SrcReg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 622 | if (mops) |
| 623 | // A dead def should have a single cycle interval. |
| 624 | ++RemoveStart; |
| 625 | } |
| 626 | } |
| 627 | } |
| 628 | } |
| 629 | |
| 630 | // We need to be careful about coalescing a source physical register with a |
| 631 | // virtual register. Once the coalescing is done, it cannot be broken and |
| 632 | // these are not spillable! If the destination interval uses are far away, |
| 633 | // think twice about coalescing them! |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 634 | if (!mopd->isDead() && (SrcIsPhys || DstIsPhys) && !isExtSubReg) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 635 | LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 636 | unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg; |
| 637 | unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg; |
| 638 | const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg); |
Evan Cheng | 6894942 | 2007-12-20 02:23:25 +0000 | [diff] [blame] | 639 | unsigned Threshold = allocatableRCRegs_[RC].count() * 2; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 640 | if (TheCopy.isBackEdge) |
| 641 | Threshold *= 2; // Favors back edge copies. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 642 | |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 643 | // If the virtual register live interval is long but it has low use desity, |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 644 | // do not join them, instead mark the physical register as its allocation |
| 645 | // preference. |
| 646 | unsigned Length = JoinVInt.getSize() / InstrSlots::NUM; |
| 647 | LiveVariables::VarInfo &vi = lv_->getVarInfo(JoinVReg); |
| 648 | if (Length > Threshold && |
| 649 | (((float)vi.NumUses / Length) < (1.0 / Threshold))) { |
| 650 | JoinVInt.preference = JoinPReg; |
| 651 | ++numAborts; |
| 652 | DOUT << "\tMay tie down a physical register, abort!\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 653 | Again = true; // May be possible to coalesce later. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 654 | return false; |
| 655 | } |
| 656 | } |
| 657 | |
| 658 | // Okay, attempt to join these two intervals. On failure, this returns false. |
| 659 | // Otherwise, if one of the intervals being joined is a physreg, this method |
| 660 | // always canonicalizes DstInt to be it. The output "SrcInt" will not have |
| 661 | // been modified, so we can use this information below to update aliases. |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 662 | bool Swapped = false; |
| 663 | if (JoinIntervals(DstInt, SrcInt, Swapped)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 664 | if (isDead) { |
| 665 | // Result of the copy is dead. Propagate this property. |
| 666 | if (SrcStart == 0) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 667 | assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 668 | "Live-in must be a physical register!"); |
| 669 | // Live-in to the function but dead. Remove it from entry live-in set. |
| 670 | // JoinIntervals may end up swapping the two intervals. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 671 | mf_->begin()->removeLiveIn(SrcReg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 672 | } else { |
| 673 | MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart); |
| 674 | if (SrcMI) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 675 | MachineOperand *mops = findDefOperand(SrcMI, SrcReg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 676 | if (mops) |
| 677 | mops->setIsDead(); |
| 678 | } |
| 679 | } |
| 680 | } |
| 681 | |
| 682 | if (isShorten || isDead) { |
Evan Cheng | ccb36a4 | 2007-08-12 01:26:19 +0000 | [diff] [blame] | 683 | // Shorten the destination live interval. |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 684 | if (Swapped) |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 685 | SrcInt.removeRange(RemoveStart, RemoveEnd, true); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 686 | } |
| 687 | } else { |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 688 | // Coalescing failed. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 689 | |
| 690 | // If we can eliminate the copy without merging the live ranges, do so now. |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 691 | if (!isExtSubReg && |
| 692 | (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) || |
| 693 | RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) { |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 694 | JoinedCopies.insert(CopyMI); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 695 | return true; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 696 | } |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 697 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 698 | // Otherwise, we are unable to join the intervals. |
| 699 | DOUT << "Interference!\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 700 | Again = true; // May be possible to coalesce later. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 701 | return false; |
| 702 | } |
| 703 | |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 704 | LiveInterval *ResSrcInt = &SrcInt; |
| 705 | LiveInterval *ResDstInt = &DstInt; |
| 706 | if (Swapped) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 707 | std::swap(SrcReg, DstReg); |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 708 | std::swap(ResSrcInt, ResDstInt); |
| 709 | } |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 710 | assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 711 | "LiveInterval::join didn't work right!"); |
| 712 | |
| 713 | // If we're about to merge live ranges into a physical register live range, |
| 714 | // we have to update any aliased register's live ranges to indicate that they |
| 715 | // have clobbered values for this range. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 716 | if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 717 | // Unset unnecessary kills. |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 718 | if (!ResDstInt->containsOneValue()) { |
| 719 | for (LiveInterval::Ranges::const_iterator I = ResSrcInt->begin(), |
| 720 | E = ResSrcInt->end(); I != E; ++I) |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 721 | unsetRegisterKills(I->start, I->end, DstReg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 722 | } |
| 723 | |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 724 | // If this is a extract_subreg where dst is a physical register, e.g. |
| 725 | // cl = EXTRACT_SUBREG reg1024, 1 |
| 726 | // then create and update the actual physical register allocated to RHS. |
| 727 | if (RealDstReg) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 728 | LiveInterval &RealDstInt = li_->getOrCreateInterval(RealDstReg); |
Evan Cheng | f5c7359 | 2007-10-15 18:33:50 +0000 | [diff] [blame] | 729 | SmallSet<const VNInfo*, 4> CopiedValNos; |
| 730 | for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(), |
| 731 | E = ResSrcInt->ranges.end(); I != E; ++I) { |
| 732 | LiveInterval::const_iterator DstLR = |
| 733 | ResDstInt->FindLiveRangeContaining(I->start); |
| 734 | assert(DstLR != ResDstInt->end() && "Invalid joined interval!"); |
| 735 | const VNInfo *DstValNo = DstLR->valno; |
| 736 | if (CopiedValNos.insert(DstValNo)) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 737 | VNInfo *ValNo = RealDstInt.getNextValue(DstValNo->def, DstValNo->copy, |
Evan Cheng | f5c7359 | 2007-10-15 18:33:50 +0000 | [diff] [blame] | 738 | li_->getVNInfoAllocator()); |
Evan Cheng | c3fc7d9 | 2007-11-29 09:49:23 +0000 | [diff] [blame] | 739 | ValNo->hasPHIKill = DstValNo->hasPHIKill; |
Evan Cheng | f5c7359 | 2007-10-15 18:33:50 +0000 | [diff] [blame] | 740 | RealDstInt.addKills(ValNo, DstValNo->kills); |
| 741 | RealDstInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo); |
| 742 | } |
Evan Cheng | 3472925 | 2007-10-14 10:08:34 +0000 | [diff] [blame] | 743 | } |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 744 | DstReg = RealDstReg; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 745 | } |
| 746 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 747 | // Update the liveintervals of sub-registers. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 748 | for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS) |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 749 | li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt, |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 750 | li_->getVNInfoAllocator()); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 751 | } else { |
| 752 | // Merge use info if the destination is a virtual register. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 753 | LiveVariables::VarInfo& dVI = lv_->getVarInfo(DstReg); |
| 754 | LiveVariables::VarInfo& sVI = lv_->getVarInfo(SrcReg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 755 | dVI.NumUses += sVI.NumUses; |
| 756 | } |
| 757 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 758 | // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the |
| 759 | // larger super-register. |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 760 | if (isExtSubReg && !SrcIsPhys && !DstIsPhys) { |
| 761 | if (!Swapped) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 762 | ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator()); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 763 | std::swap(SrcReg, DstReg); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 764 | std::swap(ResSrcInt, ResDstInt); |
| 765 | } |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 766 | } |
| 767 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 768 | if (NewHeuristic) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 769 | // Add all copies that define val# in the source interval into the queue. |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 770 | for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(), |
| 771 | e = ResSrcInt->vni_end(); i != e; ++i) { |
| 772 | const VNInfo *vni = *i; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 773 | if (!vni->def || vni->def == ~1U || vni->def == ~0U) |
| 774 | continue; |
| 775 | MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def); |
| 776 | unsigned NewSrcReg, NewDstReg; |
| 777 | if (CopyMI && |
| 778 | JoinedCopies.count(CopyMI) == 0 && |
| 779 | tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg)) { |
| 780 | unsigned LoopDepth = loopInfo->getLoopDepth(CopyMI->getParent()); |
| 781 | JoinQueue->push(CopyRec(CopyMI, LoopDepth, |
| 782 | isBackEdgeCopy(CopyMI, DstReg))); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 783 | } |
| 784 | } |
| 785 | } |
| 786 | |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 787 | DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 788 | DOUT << "\n"; |
| 789 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 790 | // Remember to delete the copy instruction. |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 791 | JoinedCopies.insert(CopyMI); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 792 | |
| 793 | // Some live range has been lengthened due to colaescing, eliminate the |
| 794 | // unnecessary kills. |
| 795 | RemoveUnnecessaryKills(SrcReg, *ResDstInt); |
| 796 | if (TargetRegisterInfo::isVirtualRegister(DstReg)) |
| 797 | RemoveUnnecessaryKills(DstReg, *ResDstInt); |
| 798 | |
| 799 | // SrcReg is guarateed to be the register whose live interval that is |
| 800 | // being merged. |
| 801 | li_->removeInterval(SrcReg); |
| 802 | UpdateRegDefsUses(SrcReg, DstReg, SubIdx); |
| 803 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 804 | ++numJoins; |
| 805 | return true; |
| 806 | } |
| 807 | |
| 808 | /// ComputeUltimateVN - Assuming we are going to join two live intervals, |
| 809 | /// compute what the resultant value numbers for each value in the input two |
| 810 | /// ranges will be. This is complicated by copies between the two which can |
| 811 | /// and will commonly cause multiple value numbers to be merged into one. |
| 812 | /// |
| 813 | /// VN is the value number that we're trying to resolve. InstDefiningValue |
| 814 | /// keeps track of the new InstDefiningValue assignment for the result |
| 815 | /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of |
| 816 | /// whether a value in this or other is a copy from the opposite set. |
| 817 | /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have |
| 818 | /// already been assigned. |
| 819 | /// |
| 820 | /// ThisFromOther[x] - If x is defined as a copy from the other interval, this |
| 821 | /// contains the value number the copy is from. |
| 822 | /// |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 823 | static unsigned ComputeUltimateVN(VNInfo *VNI, |
| 824 | SmallVector<VNInfo*, 16> &NewVNInfo, |
Evan Cheng | fadfb5b | 2007-08-31 21:23:06 +0000 | [diff] [blame] | 825 | DenseMap<VNInfo*, VNInfo*> &ThisFromOther, |
| 826 | DenseMap<VNInfo*, VNInfo*> &OtherFromThis, |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 827 | SmallVector<int, 16> &ThisValNoAssignments, |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 828 | SmallVector<int, 16> &OtherValNoAssignments) { |
| 829 | unsigned VN = VNI->id; |
| 830 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 831 | // If the VN has already been computed, just return it. |
| 832 | if (ThisValNoAssignments[VN] >= 0) |
| 833 | return ThisValNoAssignments[VN]; |
| 834 | // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?"); |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 835 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 836 | // If this val is not a copy from the other val, then it must be a new value |
| 837 | // number in the destination. |
Evan Cheng | fadfb5b | 2007-08-31 21:23:06 +0000 | [diff] [blame] | 838 | DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI); |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 839 | if (I == ThisFromOther.end()) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 840 | NewVNInfo.push_back(VNI); |
| 841 | return ThisValNoAssignments[VN] = NewVNInfo.size()-1; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 842 | } |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 843 | VNInfo *OtherValNo = I->second; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 844 | |
| 845 | // Otherwise, this *is* a copy from the RHS. If the other side has already |
| 846 | // been computed, return it. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 847 | if (OtherValNoAssignments[OtherValNo->id] >= 0) |
| 848 | return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id]; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 849 | |
| 850 | // Mark this value number as currently being computed, then ask what the |
| 851 | // ultimate value # of the other value is. |
| 852 | ThisValNoAssignments[VN] = -2; |
| 853 | unsigned UltimateVN = |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 854 | ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther, |
| 855 | OtherValNoAssignments, ThisValNoAssignments); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 856 | return ThisValNoAssignments[VN] = UltimateVN; |
| 857 | } |
| 858 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 859 | static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 860 | return std::find(V.begin(), V.end(), Val) != V.end(); |
| 861 | } |
| 862 | |
| 863 | /// SimpleJoin - Attempt to joint the specified interval into this one. The |
| 864 | /// caller of this method must guarantee that the RHS only contains a single |
| 865 | /// value number and that the RHS is not defined by a copy from this |
| 866 | /// interval. This returns false if the intervals are not joinable, or it |
| 867 | /// joins them and returns true. |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 868 | bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){ |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 869 | assert(RHS.containsOneValue()); |
| 870 | |
| 871 | // Some number (potentially more than one) value numbers in the current |
| 872 | // interval may be defined as copies from the RHS. Scan the overlapping |
| 873 | // portions of the LHS and RHS, keeping track of this and looking for |
| 874 | // overlapping live ranges that are NOT defined as copies. If these exist, we |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 875 | // cannot coalesce. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 876 | |
| 877 | LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end(); |
| 878 | LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end(); |
| 879 | |
| 880 | if (LHSIt->start < RHSIt->start) { |
| 881 | LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start); |
| 882 | if (LHSIt != LHS.begin()) --LHSIt; |
| 883 | } else if (RHSIt->start < LHSIt->start) { |
| 884 | RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start); |
| 885 | if (RHSIt != RHS.begin()) --RHSIt; |
| 886 | } |
| 887 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 888 | SmallVector<VNInfo*, 8> EliminatedLHSVals; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 889 | |
| 890 | while (1) { |
| 891 | // Determine if these live intervals overlap. |
| 892 | bool Overlaps = false; |
| 893 | if (LHSIt->start <= RHSIt->start) |
| 894 | Overlaps = LHSIt->end > RHSIt->start; |
| 895 | else |
| 896 | Overlaps = RHSIt->end > LHSIt->start; |
| 897 | |
| 898 | // If the live intervals overlap, there are two interesting cases: if the |
| 899 | // LHS interval is defined by a copy from the RHS, it's ok and we record |
| 900 | // that the LHS value # is the same as the RHS. If it's not, then we cannot |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 901 | // coalesce these live ranges and we bail out. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 902 | if (Overlaps) { |
| 903 | // If we haven't already recorded that this value # is safe, check it. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 904 | if (!InVector(LHSIt->valno, EliminatedLHSVals)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 905 | // Copy from the RHS? |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 906 | unsigned SrcReg = li_->getVNInfoSourceReg(LHSIt->valno); |
| 907 | if (SrcReg != RHS.reg) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 908 | return false; // Nope, bail out. |
| 909 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 910 | EliminatedLHSVals.push_back(LHSIt->valno); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 911 | } |
| 912 | |
| 913 | // We know this entire LHS live range is okay, so skip it now. |
| 914 | if (++LHSIt == LHSEnd) break; |
| 915 | continue; |
| 916 | } |
| 917 | |
| 918 | if (LHSIt->end < RHSIt->end) { |
| 919 | if (++LHSIt == LHSEnd) break; |
| 920 | } else { |
| 921 | // One interesting case to check here. It's possible that we have |
| 922 | // something like "X3 = Y" which defines a new value number in the LHS, |
| 923 | // and is the last use of this liverange of the RHS. In this case, we |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 924 | // want to notice this copy (so that it gets coalesced away) even though |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 925 | // the live ranges don't actually overlap. |
| 926 | if (LHSIt->start == RHSIt->end) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 927 | if (InVector(LHSIt->valno, EliminatedLHSVals)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 928 | // We already know that this value number is going to be merged in |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 929 | // if coalescing succeeds. Just skip the liverange. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 930 | if (++LHSIt == LHSEnd) break; |
| 931 | } else { |
| 932 | // Otherwise, if this is a copy from the RHS, mark it as being merged |
| 933 | // in. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 934 | if (li_->getVNInfoSourceReg(LHSIt->valno) == RHS.reg) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 935 | EliminatedLHSVals.push_back(LHSIt->valno); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 936 | |
| 937 | // We know this entire LHS live range is okay, so skip it now. |
| 938 | if (++LHSIt == LHSEnd) break; |
| 939 | } |
| 940 | } |
| 941 | } |
| 942 | |
| 943 | if (++RHSIt == RHSEnd) break; |
| 944 | } |
| 945 | } |
| 946 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 947 | // If we got here, we know that the coalescing will be successful and that |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 948 | // the value numbers in EliminatedLHSVals will all be merged together. Since |
| 949 | // the most common case is that EliminatedLHSVals has a single number, we |
| 950 | // optimize for it: if there is more than one value, we merge them all into |
| 951 | // the lowest numbered one, then handle the interval as if we were merging |
| 952 | // with one value number. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 953 | VNInfo *LHSValNo; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 954 | if (EliminatedLHSVals.size() > 1) { |
| 955 | // Loop through all the equal value numbers merging them into the smallest |
| 956 | // one. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 957 | VNInfo *Smallest = EliminatedLHSVals[0]; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 958 | for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 959 | if (EliminatedLHSVals[i]->id < Smallest->id) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 960 | // Merge the current notion of the smallest into the smaller one. |
| 961 | LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]); |
| 962 | Smallest = EliminatedLHSVals[i]; |
| 963 | } else { |
| 964 | // Merge into the smallest. |
| 965 | LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest); |
| 966 | } |
| 967 | } |
| 968 | LHSValNo = Smallest; |
| 969 | } else { |
| 970 | assert(!EliminatedLHSVals.empty() && "No copies from the RHS?"); |
| 971 | LHSValNo = EliminatedLHSVals[0]; |
| 972 | } |
| 973 | |
| 974 | // Okay, now that there is a single LHS value number that we're merging the |
| 975 | // RHS into, update the value number info for the LHS to indicate that the |
| 976 | // value number is defined where the RHS value number was. |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 977 | const VNInfo *VNI = RHS.getValNumInfo(0); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 978 | LHSValNo->def = VNI->def; |
| 979 | LHSValNo->copy = VNI->copy; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 980 | |
| 981 | // Okay, the final step is to loop over the RHS live intervals, adding them to |
| 982 | // the LHS. |
Evan Cheng | c3fc7d9 | 2007-11-29 09:49:23 +0000 | [diff] [blame] | 983 | LHSValNo->hasPHIKill |= VNI->hasPHIKill; |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 984 | LHS.addKills(LHSValNo, VNI->kills); |
Evan Cheng | 430a7b0 | 2007-08-14 01:56:58 +0000 | [diff] [blame] | 985 | LHS.MergeRangesInAsValue(RHS, LHSValNo); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 986 | LHS.weight += RHS.weight; |
| 987 | if (RHS.preference && !LHS.preference) |
| 988 | LHS.preference = RHS.preference; |
| 989 | |
| 990 | return true; |
| 991 | } |
| 992 | |
| 993 | /// JoinIntervals - Attempt to join these two intervals. On failure, this |
| 994 | /// returns false. Otherwise, if one of the intervals being joined is a |
| 995 | /// physreg, this method always canonicalizes LHS to be it. The output |
| 996 | /// "RHS" will not have been modified, so we can use this information |
| 997 | /// below to update aliases. |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 998 | bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, |
| 999 | LiveInterval &RHS, bool &Swapped) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1000 | // Compute the final value assignment, assuming that the live ranges can be |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1001 | // coalesced. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1002 | SmallVector<int, 16> LHSValNoAssignments; |
| 1003 | SmallVector<int, 16> RHSValNoAssignments; |
Evan Cheng | fadfb5b | 2007-08-31 21:23:06 +0000 | [diff] [blame] | 1004 | DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS; |
| 1005 | DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1006 | SmallVector<VNInfo*, 16> NewVNInfo; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1007 | |
| 1008 | // If a live interval is a physical register, conservatively check if any |
| 1009 | // of its sub-registers is overlapping the live interval of the virtual |
| 1010 | // register. If so, do not coalesce. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1011 | if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) && |
| 1012 | *tri_->getSubRegisters(LHS.reg)) { |
| 1013 | for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1014 | if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { |
| 1015 | DOUT << "Interfere with sub-register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1016 | DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1017 | return false; |
| 1018 | } |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1019 | } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) && |
| 1020 | *tri_->getSubRegisters(RHS.reg)) { |
| 1021 | for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1022 | if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) { |
| 1023 | DOUT << "Interfere with sub-register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1024 | DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1025 | return false; |
| 1026 | } |
| 1027 | } |
| 1028 | |
| 1029 | // Compute ultimate value numbers for the LHS and RHS values. |
| 1030 | if (RHS.containsOneValue()) { |
| 1031 | // Copies from a liveinterval with a single value are simple to handle and |
| 1032 | // very common, handle the special case here. This is important, because |
| 1033 | // often RHS is small and LHS is large (e.g. a physreg). |
| 1034 | |
| 1035 | // Find out if the RHS is defined as a copy from some value in the LHS. |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1036 | int RHSVal0DefinedFromLHS = -1; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1037 | int RHSValID = -1; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1038 | VNInfo *RHSValNoInfo = NULL; |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 1039 | VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1040 | unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0); |
| 1041 | if ((RHSSrcReg == 0 || RHSSrcReg != LHS.reg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1042 | // If RHS is not defined as a copy from the LHS, we can use simpler and |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1043 | // faster checks to see if the live ranges are coalescable. This joiner |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1044 | // can't swap the LHS/RHS intervals though. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1045 | if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1046 | return SimpleJoin(LHS, RHS); |
| 1047 | } else { |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1048 | RHSValNoInfo = RHSValNoInfo0; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1049 | } |
| 1050 | } else { |
| 1051 | // It was defined as a copy from the LHS, find out what value # it is. |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1052 | RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1053 | RHSValID = RHSValNoInfo->id; |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1054 | RHSVal0DefinedFromLHS = RHSValID; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1055 | } |
| 1056 | |
| 1057 | LHSValNoAssignments.resize(LHS.getNumValNums(), -1); |
| 1058 | RHSValNoAssignments.resize(RHS.getNumValNums(), -1); |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1059 | NewVNInfo.resize(LHS.getNumValNums(), NULL); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1060 | |
| 1061 | // Okay, *all* of the values in LHS that are defined as a copy from RHS |
| 1062 | // should now get updated. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1063 | for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); |
| 1064 | i != e; ++i) { |
| 1065 | VNInfo *VNI = *i; |
| 1066 | unsigned VN = VNI->id; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1067 | if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) { |
| 1068 | if (LHSSrcReg != RHS.reg) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1069 | // If this is not a copy from the RHS, its value number will be |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1070 | // unmodified by the coalescing. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1071 | NewVNInfo[VN] = VNI; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1072 | LHSValNoAssignments[VN] = VN; |
| 1073 | } else if (RHSValID == -1) { |
| 1074 | // Otherwise, it is a copy from the RHS, and we don't already have a |
| 1075 | // value# for it. Keep the current value number, but remember it. |
| 1076 | LHSValNoAssignments[VN] = RHSValID = VN; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1077 | NewVNInfo[VN] = RHSValNoInfo; |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1078 | LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1079 | } else { |
| 1080 | // Otherwise, use the specified value #. |
| 1081 | LHSValNoAssignments[VN] = RHSValID; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1082 | if (VN == (unsigned)RHSValID) { // Else this val# is dead. |
| 1083 | NewVNInfo[VN] = RHSValNoInfo; |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1084 | LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0; |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1085 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1086 | } |
| 1087 | } else { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1088 | NewVNInfo[VN] = VNI; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1089 | LHSValNoAssignments[VN] = VN; |
| 1090 | } |
| 1091 | } |
| 1092 | |
| 1093 | assert(RHSValID != -1 && "Didn't find value #?"); |
| 1094 | RHSValNoAssignments[0] = RHSValID; |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1095 | if (RHSVal0DefinedFromLHS != -1) { |
Evan Cheng | 3430135 | 2007-09-01 02:03:17 +0000 | [diff] [blame] | 1096 | // This path doesn't go through ComputeUltimateVN so just set |
| 1097 | // it to anything. |
| 1098 | RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1; |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1099 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1100 | } else { |
| 1101 | // Loop over the value numbers of the LHS, seeing if any are defined from |
| 1102 | // the RHS. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1103 | for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); |
| 1104 | i != e; ++i) { |
| 1105 | VNInfo *VNI = *i; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1106 | if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy? |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1107 | continue; |
| 1108 | |
| 1109 | // DstReg is known to be a register in the LHS interval. If the src is |
| 1110 | // from the RHS interval, we can use its value #. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1111 | if (li_->getVNInfoSourceReg(VNI) != RHS.reg) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1112 | continue; |
| 1113 | |
| 1114 | // Figure out the value # from the RHS. |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 1115 | LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1116 | } |
| 1117 | |
| 1118 | // Loop over the value numbers of the RHS, seeing if any are defined from |
| 1119 | // the LHS. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1120 | for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end(); |
| 1121 | i != e; ++i) { |
| 1122 | VNInfo *VNI = *i; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1123 | if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy? |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1124 | continue; |
| 1125 | |
| 1126 | // DstReg is known to be a register in the RHS interval. If the src is |
| 1127 | // from the LHS interval, we can use its value #. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1128 | if (li_->getVNInfoSourceReg(VNI) != LHS.reg) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1129 | continue; |
| 1130 | |
| 1131 | // Figure out the value # from the LHS. |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 1132 | RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1133 | } |
| 1134 | |
| 1135 | LHSValNoAssignments.resize(LHS.getNumValNums(), -1); |
| 1136 | RHSValNoAssignments.resize(RHS.getNumValNums(), -1); |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1137 | NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1138 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1139 | for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); |
| 1140 | i != e; ++i) { |
| 1141 | VNInfo *VNI = *i; |
| 1142 | unsigned VN = VNI->id; |
| 1143 | if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1144 | continue; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1145 | ComputeUltimateVN(VNI, NewVNInfo, |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1146 | LHSValsDefinedFromRHS, RHSValsDefinedFromLHS, |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1147 | LHSValNoAssignments, RHSValNoAssignments); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1148 | } |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1149 | for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end(); |
| 1150 | i != e; ++i) { |
| 1151 | VNInfo *VNI = *i; |
| 1152 | unsigned VN = VNI->id; |
| 1153 | if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1154 | continue; |
| 1155 | // If this value number isn't a copy from the LHS, it's a new number. |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1156 | if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1157 | NewVNInfo.push_back(VNI); |
| 1158 | RHSValNoAssignments[VN] = NewVNInfo.size()-1; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1159 | continue; |
| 1160 | } |
| 1161 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1162 | ComputeUltimateVN(VNI, NewVNInfo, |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1163 | RHSValsDefinedFromLHS, LHSValsDefinedFromRHS, |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1164 | RHSValNoAssignments, LHSValNoAssignments); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1165 | } |
| 1166 | } |
| 1167 | |
| 1168 | // Armed with the mappings of LHS/RHS values to ultimate values, walk the |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1169 | // interval lists to see if these intervals are coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1170 | LiveInterval::const_iterator I = LHS.begin(); |
| 1171 | LiveInterval::const_iterator IE = LHS.end(); |
| 1172 | LiveInterval::const_iterator J = RHS.begin(); |
| 1173 | LiveInterval::const_iterator JE = RHS.end(); |
| 1174 | |
| 1175 | // Skip ahead until the first place of potential sharing. |
| 1176 | if (I->start < J->start) { |
| 1177 | I = std::upper_bound(I, IE, J->start); |
| 1178 | if (I != LHS.begin()) --I; |
| 1179 | } else if (J->start < I->start) { |
| 1180 | J = std::upper_bound(J, JE, I->start); |
| 1181 | if (J != RHS.begin()) --J; |
| 1182 | } |
| 1183 | |
| 1184 | while (1) { |
| 1185 | // Determine if these two live ranges overlap. |
| 1186 | bool Overlaps; |
| 1187 | if (I->start < J->start) { |
| 1188 | Overlaps = I->end > J->start; |
| 1189 | } else { |
| 1190 | Overlaps = J->end > I->start; |
| 1191 | } |
| 1192 | |
| 1193 | // If so, check value # info to determine if they are really different. |
| 1194 | if (Overlaps) { |
| 1195 | // If the live range overlap will map to the same value number in the |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1196 | // result liverange, we can still coalesce them. If not, we can't. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1197 | if (LHSValNoAssignments[I->valno->id] != |
| 1198 | RHSValNoAssignments[J->valno->id]) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1199 | return false; |
| 1200 | } |
| 1201 | |
| 1202 | if (I->end < J->end) { |
| 1203 | ++I; |
| 1204 | if (I == IE) break; |
| 1205 | } else { |
| 1206 | ++J; |
| 1207 | if (J == JE) break; |
| 1208 | } |
| 1209 | } |
| 1210 | |
Evan Cheng | 3472925 | 2007-10-14 10:08:34 +0000 | [diff] [blame] | 1211 | // Update kill info. Some live ranges are extended due to copy coalescing. |
| 1212 | for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(), |
| 1213 | E = LHSValsDefinedFromRHS.end(); I != E; ++I) { |
| 1214 | VNInfo *VNI = I->first; |
| 1215 | unsigned LHSValID = LHSValNoAssignments[VNI->id]; |
| 1216 | LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def); |
Evan Cheng | c3fc7d9 | 2007-11-29 09:49:23 +0000 | [diff] [blame] | 1217 | NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill; |
Evan Cheng | 3472925 | 2007-10-14 10:08:34 +0000 | [diff] [blame] | 1218 | RHS.addKills(NewVNInfo[LHSValID], VNI->kills); |
| 1219 | } |
| 1220 | |
| 1221 | // Update kill info. Some live ranges are extended due to copy coalescing. |
| 1222 | for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(), |
| 1223 | E = RHSValsDefinedFromLHS.end(); I != E; ++I) { |
| 1224 | VNInfo *VNI = I->first; |
| 1225 | unsigned RHSValID = RHSValNoAssignments[VNI->id]; |
| 1226 | LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def); |
Evan Cheng | c3fc7d9 | 2007-11-29 09:49:23 +0000 | [diff] [blame] | 1227 | NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill; |
Evan Cheng | 3472925 | 2007-10-14 10:08:34 +0000 | [diff] [blame] | 1228 | LHS.addKills(NewVNInfo[RHSValID], VNI->kills); |
| 1229 | } |
| 1230 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1231 | // If we get here, we know that we can coalesce the live ranges. Ask the |
| 1232 | // intervals to coalesce themselves now. |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1233 | if ((RHS.ranges.size() > LHS.ranges.size() && |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1234 | TargetRegisterInfo::isVirtualRegister(LHS.reg)) || |
| 1235 | TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1236 | RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo); |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1237 | Swapped = true; |
| 1238 | } else { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1239 | LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo); |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1240 | Swapped = false; |
| 1241 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1242 | return true; |
| 1243 | } |
| 1244 | |
| 1245 | namespace { |
| 1246 | // DepthMBBCompare - Comparison predicate that sort first based on the loop |
| 1247 | // depth of the basic block (the unsigned), and then on the MBB number. |
| 1248 | struct DepthMBBCompare { |
| 1249 | typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; |
| 1250 | bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { |
| 1251 | if (LHS.first > RHS.first) return true; // Deeper loops first |
| 1252 | return LHS.first == RHS.first && |
| 1253 | LHS.second->getNumber() < RHS.second->getNumber(); |
| 1254 | } |
| 1255 | }; |
| 1256 | } |
| 1257 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1258 | /// getRepIntervalSize - Returns the size of the interval that represents the |
| 1259 | /// specified register. |
| 1260 | template<class SF> |
| 1261 | unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) { |
| 1262 | return Rc->getRepIntervalSize(Reg); |
| 1263 | } |
| 1264 | |
| 1265 | /// CopyRecSort::operator - Join priority queue sorting function. |
| 1266 | /// |
| 1267 | bool CopyRecSort::operator()(CopyRec left, CopyRec right) const { |
| 1268 | // Inner loops first. |
| 1269 | if (left.LoopDepth > right.LoopDepth) |
| 1270 | return false; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1271 | else if (left.LoopDepth == right.LoopDepth) |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1272 | if (left.isBackEdge && !right.isBackEdge) |
| 1273 | return false; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1274 | return true; |
| 1275 | } |
| 1276 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1277 | void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB, |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1278 | std::vector<CopyRec> &TryAgain) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1279 | DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n"; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1280 | |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1281 | std::vector<CopyRec> VirtCopies; |
| 1282 | std::vector<CopyRec> PhysCopies; |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 1283 | unsigned LoopDepth = loopInfo->getLoopDepth(MBB); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1284 | for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); |
| 1285 | MII != E;) { |
| 1286 | MachineInstr *Inst = MII++; |
| 1287 | |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1288 | // If this isn't a copy nor a extract_subreg, we can't join intervals. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1289 | unsigned SrcReg, DstReg; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1290 | if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) { |
| 1291 | DstReg = Inst->getOperand(0).getReg(); |
| 1292 | SrcReg = Inst->getOperand(1).getReg(); |
| 1293 | } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) |
| 1294 | continue; |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1295 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1296 | bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); |
| 1297 | bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1298 | if (NewHeuristic) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1299 | JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg))); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1300 | } else { |
| 1301 | if (SrcIsPhys || DstIsPhys) |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1302 | PhysCopies.push_back(CopyRec(Inst, 0, false)); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1303 | else |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1304 | VirtCopies.push_back(CopyRec(Inst, 0, false)); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1305 | } |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1306 | } |
| 1307 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1308 | if (NewHeuristic) |
| 1309 | return; |
| 1310 | |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1311 | // Try coalescing physical register + virtual register first. |
| 1312 | for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) { |
| 1313 | CopyRec &TheCopy = PhysCopies[i]; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1314 | bool Again = false; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1315 | if (!JoinCopy(TheCopy, Again)) |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1316 | if (Again) |
| 1317 | TryAgain.push_back(TheCopy); |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1318 | } |
| 1319 | for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) { |
| 1320 | CopyRec &TheCopy = VirtCopies[i]; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1321 | bool Again = false; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1322 | if (!JoinCopy(TheCopy, Again)) |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1323 | if (Again) |
| 1324 | TryAgain.push_back(TheCopy); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1325 | } |
| 1326 | } |
| 1327 | |
| 1328 | void SimpleRegisterCoalescing::joinIntervals() { |
| 1329 | DOUT << "********** JOINING INTERVALS ***********\n"; |
| 1330 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1331 | if (NewHeuristic) |
| 1332 | JoinQueue = new JoinPriorityQueue<CopyRecSort>(this); |
| 1333 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1334 | std::vector<CopyRec> TryAgainList; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1335 | if (loopInfo->begin() == loopInfo->end()) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1336 | // If there are no loops in the function, join intervals in function order. |
| 1337 | for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); |
| 1338 | I != E; ++I) |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1339 | CopyCoalesceInMBB(I, TryAgainList); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1340 | } else { |
| 1341 | // Otherwise, join intervals in inner loops before other intervals. |
| 1342 | // Unfortunately we can't just iterate over loop hierarchy here because |
| 1343 | // there may be more MBB's than BB's. Collect MBB's for sorting. |
| 1344 | |
| 1345 | // Join intervals in the function prolog first. We want to join physical |
| 1346 | // registers with virtual registers before the intervals got too long. |
| 1347 | std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 1348 | for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){ |
| 1349 | MachineBasicBlock *MBB = I; |
| 1350 | MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I)); |
| 1351 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1352 | |
| 1353 | // Sort by loop depth. |
| 1354 | std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); |
| 1355 | |
| 1356 | // Finally, join intervals in loop nest order. |
| 1357 | for (unsigned i = 0, e = MBBs.size(); i != e; ++i) |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1358 | CopyCoalesceInMBB(MBBs[i].second, TryAgainList); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1359 | } |
| 1360 | |
| 1361 | // Joining intervals can allow other intervals to be joined. Iteratively join |
| 1362 | // until we make no progress. |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1363 | if (NewHeuristic) { |
| 1364 | SmallVector<CopyRec, 16> TryAgain; |
| 1365 | bool ProgressMade = true; |
| 1366 | while (ProgressMade) { |
| 1367 | ProgressMade = false; |
| 1368 | while (!JoinQueue->empty()) { |
| 1369 | CopyRec R = JoinQueue->pop(); |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1370 | bool Again = false; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1371 | bool Success = JoinCopy(R, Again); |
| 1372 | if (Success) |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1373 | ProgressMade = true; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1374 | else if (Again) |
| 1375 | TryAgain.push_back(R); |
| 1376 | } |
| 1377 | |
| 1378 | if (ProgressMade) { |
| 1379 | while (!TryAgain.empty()) { |
| 1380 | JoinQueue->push(TryAgain.back()); |
| 1381 | TryAgain.pop_back(); |
| 1382 | } |
| 1383 | } |
| 1384 | } |
| 1385 | } else { |
| 1386 | bool ProgressMade = true; |
| 1387 | while (ProgressMade) { |
| 1388 | ProgressMade = false; |
| 1389 | |
| 1390 | for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) { |
| 1391 | CopyRec &TheCopy = TryAgainList[i]; |
| 1392 | if (TheCopy.MI) { |
| 1393 | bool Again = false; |
| 1394 | bool Success = JoinCopy(TheCopy, Again); |
| 1395 | if (Success || !Again) { |
| 1396 | TheCopy.MI = 0; // Mark this one as done. |
| 1397 | ProgressMade = true; |
| 1398 | } |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1399 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1400 | } |
| 1401 | } |
| 1402 | } |
| 1403 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1404 | if (NewHeuristic) |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1405 | delete JoinQueue; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1406 | } |
| 1407 | |
| 1408 | /// Return true if the two specified registers belong to different register |
| 1409 | /// classes. The registers may be either phys or virt regs. |
| 1410 | bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA, |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1411 | unsigned RegB) const { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1412 | |
| 1413 | // Get the register classes for the first reg. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1414 | if (TargetRegisterInfo::isPhysicalRegister(RegA)) { |
| 1415 | assert(TargetRegisterInfo::isVirtualRegister(RegB) && |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1416 | "Shouldn't consider two physregs!"); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1417 | return !mri_->getRegClass(RegB)->contains(RegA); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1418 | } |
| 1419 | |
| 1420 | // Compare against the regclass for the second reg. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1421 | const TargetRegisterClass *RegClass = mri_->getRegClass(RegA); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1422 | if (TargetRegisterInfo::isVirtualRegister(RegB)) |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1423 | return RegClass != mri_->getRegClass(RegB); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1424 | else |
| 1425 | return !RegClass->contains(RegB); |
| 1426 | } |
| 1427 | |
| 1428 | /// lastRegisterUse - Returns the last use of the specific register between |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1429 | /// cycles Start and End or NULL if there are no uses. |
| 1430 | MachineOperand * |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 1431 | SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1432 | unsigned Reg, unsigned &UseIdx) const{ |
| 1433 | UseIdx = 0; |
| 1434 | if (TargetRegisterInfo::isVirtualRegister(Reg)) { |
| 1435 | MachineOperand *LastUse = NULL; |
| 1436 | for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg), |
| 1437 | E = mri_->use_end(); I != E; ++I) { |
| 1438 | MachineOperand &Use = I.getOperand(); |
| 1439 | MachineInstr *UseMI = Use.getParent(); |
| 1440 | unsigned Idx = li_->getInstructionIndex(UseMI); |
| 1441 | if (Idx >= Start && Idx < End && Idx >= UseIdx) { |
| 1442 | LastUse = &Use; |
| 1443 | UseIdx = Idx; |
| 1444 | } |
| 1445 | } |
| 1446 | return LastUse; |
| 1447 | } |
| 1448 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1449 | int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM; |
| 1450 | int s = Start; |
| 1451 | while (e >= s) { |
| 1452 | // Skip deleted instructions |
| 1453 | MachineInstr *MI = li_->getInstructionFromIndex(e); |
| 1454 | while ((e - InstrSlots::NUM) >= s && !MI) { |
| 1455 | e -= InstrSlots::NUM; |
| 1456 | MI = li_->getInstructionFromIndex(e); |
| 1457 | } |
| 1458 | if (e < s || MI == NULL) |
| 1459 | return NULL; |
| 1460 | |
| 1461 | for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1462 | MachineOperand &Use = MI->getOperand(i); |
| 1463 | if (Use.isRegister() && Use.isUse() && Use.getReg() && |
| 1464 | tri_->regsOverlap(Use.getReg(), Reg)) { |
| 1465 | UseIdx = e; |
| 1466 | return &Use; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1467 | } |
| 1468 | } |
| 1469 | |
| 1470 | e -= InstrSlots::NUM; |
| 1471 | } |
| 1472 | |
| 1473 | return NULL; |
| 1474 | } |
| 1475 | |
| 1476 | |
| 1477 | /// findDefOperand - Returns the MachineOperand that is a def of the specific |
| 1478 | /// register. It returns NULL if the def is not found. |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 1479 | MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1480 | unsigned Reg) const { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1481 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 1482 | MachineOperand &MO = MI->getOperand(i); |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 1483 | if (MO.isRegister() && MO.isDef() && |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1484 | tri_->regsOverlap(MO.getReg(), Reg)) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1485 | return &MO; |
| 1486 | } |
| 1487 | return NULL; |
| 1488 | } |
| 1489 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1490 | /// unsetRegisterKills - Unset IsKill property of all uses of specific register |
| 1491 | /// between cycles Start and End. |
| 1492 | void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End, |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 1493 | unsigned Reg) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1494 | int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM; |
| 1495 | int s = Start; |
| 1496 | while (e >= s) { |
| 1497 | // Skip deleted instructions |
| 1498 | MachineInstr *MI = li_->getInstructionFromIndex(e); |
| 1499 | while ((e - InstrSlots::NUM) >= s && !MI) { |
| 1500 | e -= InstrSlots::NUM; |
| 1501 | MI = li_->getInstructionFromIndex(e); |
| 1502 | } |
| 1503 | if (e < s || MI == NULL) |
| 1504 | return; |
| 1505 | |
| 1506 | for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { |
| 1507 | MachineOperand &MO = MI->getOperand(i); |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 1508 | if (MO.isRegister() && MO.isKill() && MO.getReg() && |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1509 | tri_->regsOverlap(MO.getReg(), Reg)) { |
Chris Lattner | f738230 | 2007-12-30 21:56:09 +0000 | [diff] [blame] | 1510 | MO.setIsKill(false); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1511 | } |
| 1512 | } |
| 1513 | |
| 1514 | e -= InstrSlots::NUM; |
| 1515 | } |
| 1516 | } |
| 1517 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1518 | void SimpleRegisterCoalescing::printRegName(unsigned reg) const { |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1519 | if (TargetRegisterInfo::isPhysicalRegister(reg)) |
| 1520 | cerr << tri_->getName(reg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1521 | else |
| 1522 | cerr << "%reg" << reg; |
| 1523 | } |
| 1524 | |
| 1525 | void SimpleRegisterCoalescing::releaseMemory() { |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1526 | JoinedCopies.clear(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1527 | } |
| 1528 | |
| 1529 | static bool isZeroLengthInterval(LiveInterval *li) { |
| 1530 | for (LiveInterval::Ranges::const_iterator |
| 1531 | i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i) |
| 1532 | if (i->end - i->start > LiveIntervals::InstrSlots::NUM) |
| 1533 | return false; |
| 1534 | return true; |
| 1535 | } |
| 1536 | |
| 1537 | bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { |
| 1538 | mf_ = &fn; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 1539 | mri_ = &fn.getRegInfo(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1540 | tm_ = &fn.getTarget(); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1541 | tri_ = tm_->getRegisterInfo(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1542 | tii_ = tm_->getInstrInfo(); |
| 1543 | li_ = &getAnalysis<LiveIntervals>(); |
| 1544 | lv_ = &getAnalysis<LiveVariables>(); |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 1545 | loopInfo = &getAnalysis<MachineLoopInfo>(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1546 | |
| 1547 | DOUT << "********** SIMPLE REGISTER COALESCING **********\n" |
| 1548 | << "********** Function: " |
| 1549 | << ((Value*)mf_->getFunction())->getName() << '\n'; |
| 1550 | |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1551 | allocatableRegs_ = tri_->getAllocatableSet(fn); |
| 1552 | for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(), |
| 1553 | E = tri_->regclass_end(); I != E; ++I) |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 1554 | allocatableRCRegs_.insert(std::make_pair(*I, |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1555 | tri_->getAllocatableSet(fn, *I))); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1556 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1557 | // Join (coalesce) intervals if requested. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1558 | if (EnableJoining) { |
| 1559 | joinIntervals(); |
| 1560 | DOUT << "********** INTERVALS POST JOINING **********\n"; |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 1561 | for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){ |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1562 | I->second.print(DOUT, tri_); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1563 | DOUT << "\n"; |
| 1564 | } |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1565 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1566 | // Delete all coalesced copies. |
| 1567 | for (SmallPtrSet<MachineInstr*,32>::iterator I = JoinedCopies.begin(), |
| 1568 | E = JoinedCopies.end(); I != E; ++I) { |
| 1569 | li_->RemoveMachineInstrFromMaps(*I); |
| 1570 | (*I)->eraseFromParent(); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 1571 | ++numPeep; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1572 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1573 | } |
| 1574 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1575 | // Perform a final pass over the instructions and compute spill weights |
| 1576 | // and remove identity moves. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1577 | for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); |
| 1578 | mbbi != mbbe; ++mbbi) { |
| 1579 | MachineBasicBlock* mbb = mbbi; |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 1580 | unsigned loopDepth = loopInfo->getLoopDepth(mbb); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1581 | |
| 1582 | for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); |
| 1583 | mii != mie; ) { |
| 1584 | // if the move will be an identity move delete it |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1585 | unsigned srcReg, dstReg; |
| 1586 | if (tii_->isMoveInstr(*mii, srcReg, dstReg) && srcReg == dstReg) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1587 | // remove from def list |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1588 | LiveInterval &RegInt = li_->getOrCreateInterval(srcReg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1589 | MachineOperand *MO = mii->findRegisterDefOperand(dstReg); |
| 1590 | // If def of this move instruction is dead, remove its live range from |
| 1591 | // the dstination register's live interval. |
| 1592 | if (MO->isDead()) { |
| 1593 | unsigned MoveIdx = li_->getDefIndex(li_->getInstructionIndex(mii)); |
| 1594 | LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 1595 | RegInt.removeRange(MLR->start, MoveIdx+1, true); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1596 | if (RegInt.empty()) |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1597 | li_->removeInterval(srcReg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1598 | } |
| 1599 | li_->RemoveMachineInstrFromMaps(mii); |
| 1600 | mii = mbbi->erase(mii); |
| 1601 | ++numPeep; |
| 1602 | } else { |
| 1603 | SmallSet<unsigned, 4> UniqueUses; |
| 1604 | for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { |
| 1605 | const MachineOperand &mop = mii->getOperand(i); |
| 1606 | if (mop.isRegister() && mop.getReg() && |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1607 | TargetRegisterInfo::isVirtualRegister(mop.getReg())) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1608 | unsigned reg = mop.getReg(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1609 | // Multiple uses of reg by the same instruction. It should not |
| 1610 | // contribute to spill weight again. |
| 1611 | if (UniqueUses.count(reg) != 0) |
| 1612 | continue; |
| 1613 | LiveInterval &RegInt = li_->getInterval(reg); |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 1614 | RegInt.weight += |
| 1615 | li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1616 | UniqueUses.insert(reg); |
| 1617 | } |
| 1618 | } |
| 1619 | ++mii; |
| 1620 | } |
| 1621 | } |
| 1622 | } |
| 1623 | |
| 1624 | for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) { |
| 1625 | LiveInterval &LI = I->second; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1626 | if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1627 | // If the live interval length is essentially zero, i.e. in every live |
| 1628 | // range the use follows def immediately, it doesn't make sense to spill |
| 1629 | // it and hope it will be easier to allocate for this li. |
| 1630 | if (isZeroLengthInterval(&LI)) |
| 1631 | LI.weight = HUGE_VALF; |
Evan Cheng | 5ef3a04 | 2007-12-06 00:01:56 +0000 | [diff] [blame] | 1632 | else { |
| 1633 | bool isLoad = false; |
Evan Cheng | 63a18c4 | 2008-02-09 08:36:28 +0000 | [diff] [blame] | 1634 | if (li_->isReMaterializable(LI, isLoad)) { |
Evan Cheng | 5ef3a04 | 2007-12-06 00:01:56 +0000 | [diff] [blame] | 1635 | // If all of the definitions of the interval are re-materializable, |
| 1636 | // it is a preferred candidate for spilling. If non of the defs are |
| 1637 | // loads, then it's potentially very cheap to re-materialize. |
| 1638 | // FIXME: this gets much more complicated once we support non-trivial |
| 1639 | // re-materialization. |
| 1640 | if (isLoad) |
| 1641 | LI.weight *= 0.9F; |
| 1642 | else |
| 1643 | LI.weight *= 0.5F; |
| 1644 | } |
| 1645 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1646 | |
| 1647 | // Slightly prefer live interval that has been assigned a preferred reg. |
| 1648 | if (LI.preference) |
| 1649 | LI.weight *= 1.01F; |
| 1650 | |
| 1651 | // Divide the weight of the interval by its size. This encourages |
| 1652 | // spilling of intervals that are large and have few uses, and |
| 1653 | // discourages spilling of small intervals with many uses. |
| 1654 | LI.weight /= LI.getSize(); |
| 1655 | } |
| 1656 | } |
| 1657 | |
| 1658 | DEBUG(dump()); |
| 1659 | return true; |
| 1660 | } |
| 1661 | |
| 1662 | /// print - Implement the dump method. |
| 1663 | void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const { |
| 1664 | li_->print(O, m); |
| 1665 | } |
David Greene | 2c17c4d | 2007-09-06 16:18:45 +0000 | [diff] [blame] | 1666 | |
| 1667 | RegisterCoalescer* llvm::createSimpleRegisterCoalescer() { |
| 1668 | return new SimpleRegisterCoalescing(); |
| 1669 | } |
| 1670 | |
| 1671 | // Make sure that anything that uses RegisterCoalescer pulls in this file... |
| 1672 | DEFINING_FILE_FOR(SimpleRegisterCoalescing) |