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Vikram S. Adve0799fc42001-09-18 12:58:33 +00001//===-- SchedInfo.cpp - Generic code to support target schedulers ----------==//
John Criswellb576c942003-10-20 19:43:21 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Vikram S. Adve0799fc42001-09-18 12:58:33 +00009//
10// This file implements the generic part of a Scheduler description for a
11// target. This functionality is defined in the llvm/Target/SchedInfo.h file.
12//
13//===----------------------------------------------------------------------===//
14
Chris Lattnerd0f166a2002-12-29 03:13:05 +000015#include "llvm/Target/TargetSchedInfo.h"
Chris Lattner884f4b52002-02-03 07:47:05 +000016#include "llvm/Target/TargetMachine.h"
Vikram S. Adve0799fc42001-09-18 12:58:33 +000017
Brian Gaeked0fde302003-11-11 22:41:34 +000018namespace llvm {
19
Tanya Lattner0e1c48b2004-04-30 20:40:38 +000020resourceId_t CPUResource::nextId = 0;
Vikram S. Adve0799fc42001-09-18 12:58:33 +000021
Chris Lattner55a47002004-05-01 11:17:13 +000022CPUResource::CPUResource(const std::string& resourceName, int maxUsers)
23 : rname(resourceName), rid(nextId++), maxNumUsers(maxUsers) {}
24
Vikram S. Adve0799fc42001-09-18 12:58:33 +000025// Check if fromRVec and toRVec have *any* common entries.
26// Assume the vectors are sorted in increasing order.
27// Algorithm copied from function set_intersection() for sorted ranges
28// (stl_algo.h).
29//
30inline static bool
Chris Lattner697954c2002-01-20 22:54:45 +000031RUConflict(const std::vector<resourceId_t>& fromRVec,
32 const std::vector<resourceId_t>& toRVec)
Vikram S. Adve0799fc42001-09-18 12:58:33 +000033{
34
35 unsigned fN = fromRVec.size(), tN = toRVec.size();
36 unsigned fi = 0, ti = 0;
37
Misha Brukmanb10cea82003-08-05 00:02:06 +000038 while (fi < fN && ti < tN) {
39 if (fromRVec[fi] < toRVec[ti])
40 ++fi;
41 else if (toRVec[ti] < fromRVec[fi])
42 ++ti;
43 else
44 return true;
45 }
Vikram S. Adve0799fc42001-09-18 12:58:33 +000046 return false;
47}
48
49
50static cycles_t
51ComputeMinGap(const InstrRUsage &fromRU,
52 const InstrRUsage &toRU)
53{
54 cycles_t minGap = 0;
55
56 if (fromRU.numBubbles > 0)
57 minGap = fromRU.numBubbles;
58
Misha Brukmanb10cea82003-08-05 00:02:06 +000059 if (minGap < fromRU.numCycles) {
60 // only need to check from cycle `minGap' onwards
61 for (cycles_t gap=minGap; gap <= fromRU.numCycles-1; gap++) {
62 // check if instr. #2 can start executing `gap' cycles after #1
63 // by checking for resource conflicts in each overlapping cycle
64 cycles_t numOverlap =std::min(fromRU.numCycles - gap, toRU.numCycles);
65 for (cycles_t c = 0; c <= numOverlap-1; c++)
66 if (RUConflict(fromRU.resourcesByCycle[gap + c],
67 toRU.resourcesByCycle[c])) {
68 // conflict found so minGap must be more than `gap'
69 minGap = gap+1;
70 break;
71 }
Vikram S. Adve0799fc42001-09-18 12:58:33 +000072 }
Misha Brukmanb10cea82003-08-05 00:02:06 +000073 }
Vikram S. Adve0799fc42001-09-18 12:58:33 +000074
75 return minGap;
76}
77
78
79//---------------------------------------------------------------------------
Chris Lattnerd0f166a2002-12-29 03:13:05 +000080// class TargetSchedInfo
Vikram S. Adve0799fc42001-09-18 12:58:33 +000081// Interface to machine description for instruction scheduling
82//---------------------------------------------------------------------------
83
Chris Lattnerd0f166a2002-12-29 03:13:05 +000084TargetSchedInfo::TargetSchedInfo(const TargetMachine& tgt,
85 int NumSchedClasses,
86 const InstrClassRUsage* ClassRUsages,
87 const InstrRUsageDelta* UsageDeltas,
88 const InstrIssueDelta* IssueDeltas,
89 unsigned NumUsageDeltas,
90 unsigned NumIssueDeltas)
Vikram S. Adve7a2f1e72001-11-08 05:15:08 +000091 : target(tgt),
92 numSchedClasses(NumSchedClasses), mii(& tgt.getInstrInfo()),
Vikram S. Adve0799fc42001-09-18 12:58:33 +000093 classRUsages(ClassRUsages), usageDeltas(UsageDeltas),
94 issueDeltas(IssueDeltas), numUsageDeltas(NumUsageDeltas),
95 numIssueDeltas(NumIssueDeltas)
96{}
97
98void
Chris Lattnerd0f166a2002-12-29 03:13:05 +000099TargetSchedInfo::initializeResources()
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000100{
101 assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal()
102 && "Insufficient slots for static data! Increase MAX_NUM_SLOTS");
103
104 // First, compute common resource usage info for each class because
105 // most instructions will probably behave the same as their class.
106 // Cannot allocate a vector of InstrRUsage so new each one.
107 //
Chris Lattner697954c2002-01-20 22:54:45 +0000108 std::vector<InstrRUsage> instrRUForClasses;
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000109 instrRUForClasses.resize(numSchedClasses);
110 for (InstrSchedClass sc = 0; sc < numSchedClasses; sc++) {
111 // instrRUForClasses.push_back(new InstrRUsage);
112 instrRUForClasses[sc].setMaxSlots(getMaxNumIssueTotal());
Chris Lattner30587612002-02-04 05:56:30 +0000113 instrRUForClasses[sc].setTo(classRUsages[sc]);
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000114 }
115
116 computeInstrResources(instrRUForClasses);
117 computeIssueGaps(instrRUForClasses);
118}
119
120
121void
Chris Lattnerd0f166a2002-12-29 03:13:05 +0000122TargetSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000123 instrRUForClasses)
124{
Chris Lattnerbceb6882004-02-29 06:31:16 +0000125 int numOpCodes = mii->getNumOpcodes();
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000126 instrRUsages.resize(numOpCodes);
127
128 // First get the resource usage information from the class resource usages.
129 for (MachineOpCode op = 0; op < numOpCodes; ++op) {
130 InstrSchedClass sc = getSchedClass(op);
Chris Lattner07541a22002-10-28 04:59:43 +0000131 assert(sc < numSchedClasses);
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000132 instrRUsages[op] = instrRUForClasses[sc];
133 }
134
135 // Now, modify the resource usages as specified in the deltas.
136 for (unsigned i = 0; i < numUsageDeltas; ++i) {
137 MachineOpCode op = usageDeltas[i].opCode;
138 assert(op < numOpCodes);
139 instrRUsages[op].addUsageDelta(usageDeltas[i]);
140 }
141
142 // Then modify the issue restrictions as specified in the deltas.
143 for (unsigned i = 0; i < numIssueDeltas; ++i) {
144 MachineOpCode op = issueDeltas[i].opCode;
145 assert(op < numOpCodes);
146 instrRUsages[issueDeltas[i].opCode].addIssueDelta(issueDeltas[i]);
147 }
148}
149
150
151void
Chris Lattnerd0f166a2002-12-29 03:13:05 +0000152TargetSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>&
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000153 instrRUForClasses)
154{
Chris Lattnerbceb6882004-02-29 06:31:16 +0000155 int numOpCodes = mii->getNumOpcodes();
Vikram S. Adve5aefcad2002-10-13 00:37:46 +0000156 issueGaps.resize(numOpCodes);
157 conflictLists.resize(numOpCodes);
158
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000159 assert(numOpCodes < (1 << MAX_OPCODE_SIZE) - 1
160 && "numOpCodes invalid for implementation of class OpCodePair!");
Vikram S. Adve5aefcad2002-10-13 00:37:46 +0000161
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000162 // First, compute issue gaps between pairs of classes based on common
163 // resources usages for each class, because most instruction pairs will
164 // usually behave the same as their class.
165 //
166 int classPairGaps[numSchedClasses][numSchedClasses];
167 for (InstrSchedClass fromSC=0; fromSC < numSchedClasses; fromSC++)
Misha Brukmanb10cea82003-08-05 00:02:06 +0000168 for (InstrSchedClass toSC=0; toSC < numSchedClasses; toSC++) {
169 int classPairGap = ComputeMinGap(instrRUForClasses[fromSC],
170 instrRUForClasses[toSC]);
171 classPairGaps[fromSC][toSC] = classPairGap;
172 }
Vikram S. Adve5aefcad2002-10-13 00:37:46 +0000173
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000174 // Now, for each pair of instructions, use the class pair gap if both
175 // instructions have identical resource usage as their respective classes.
176 // If not, recompute the gap for the pair from scratch.
Vikram S. Adve5aefcad2002-10-13 00:37:46 +0000177
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000178 longestIssueConflict = 0;
Vikram S. Adve5aefcad2002-10-13 00:37:46 +0000179
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000180 for (MachineOpCode fromOp=0; fromOp < numOpCodes; fromOp++)
Misha Brukmanb10cea82003-08-05 00:02:06 +0000181 for (MachineOpCode toOp=0; toOp < numOpCodes; toOp++) {
182 int instrPairGap =
183 (instrRUsages[fromOp].sameAsClass && instrRUsages[toOp].sameAsClass)
184 ? classPairGaps[getSchedClass(fromOp)][getSchedClass(toOp)]
185 : ComputeMinGap(instrRUsages[fromOp], instrRUsages[toOp]);
Vikram S. Adve5aefcad2002-10-13 00:37:46 +0000186
Misha Brukmanb10cea82003-08-05 00:02:06 +0000187 if (instrPairGap > 0) {
188 this->setGap(instrPairGap, fromOp, toOp);
189 conflictLists[fromOp].push_back(toOp);
190 longestIssueConflict=std::max(longestIssueConflict, instrPairGap);
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000191 }
Misha Brukmanb10cea82003-08-05 00:02:06 +0000192 }
Vikram S. Adve0799fc42001-09-18 12:58:33 +0000193}
194
Chris Lattner30587612002-02-04 05:56:30 +0000195
196void InstrRUsage::setTo(const InstrClassRUsage& classRU) {
197 sameAsClass = true;
198 isSingleIssue = classRU.isSingleIssue;
199 breaksGroup = classRU.breaksGroup;
200 numBubbles = classRU.numBubbles;
201
Misha Brukmanb10cea82003-08-05 00:02:06 +0000202 for (unsigned i=0; i < classRU.numSlots; i++) {
203 unsigned slot = classRU.feasibleSlots[i];
204 assert(slot < feasibleSlots.size() && "Invalid slot specified!");
205 this->feasibleSlots[slot] = true;
206 }
Chris Lattner30587612002-02-04 05:56:30 +0000207
208 numCycles = classRU.totCycles;
209 resourcesByCycle.resize(this->numCycles);
210
211 for (unsigned i=0; i < classRU.numRUEntries; i++)
212 for (unsigned c=classRU.V[i].startCycle, NC = c + classRU.V[i].numCycles;
213 c < NC; c++)
214 this->resourcesByCycle[c].push_back(classRU.V[i].resourceId);
215
Misha Brukmanb10cea82003-08-05 00:02:06 +0000216 // Sort each resource usage vector by resourceId_t to speed up conflict
217 // checking
Chris Lattner30587612002-02-04 05:56:30 +0000218 for (unsigned i=0; i < this->resourcesByCycle.size(); i++)
219 sort(resourcesByCycle[i].begin(), resourcesByCycle[i].end());
Chris Lattner30587612002-02-04 05:56:30 +0000220}
221
222// Add the extra resource usage requirements specified in the delta.
223// Note that a negative value of `numCycles' means one entry for that
224// resource should be deleted for each cycle.
225//
226void InstrRUsage::addUsageDelta(const InstrRUsageDelta &delta) {
227 int NC = delta.numCycles;
228 sameAsClass = false;
229
230 // resize the resources vector if more cycles are specified
231 unsigned maxCycles = this->numCycles;
232 maxCycles = std::max(maxCycles, delta.startCycle + abs(NC) - 1);
Misha Brukmanb10cea82003-08-05 00:02:06 +0000233 if (maxCycles > this->numCycles) {
234 this->resourcesByCycle.resize(maxCycles);
235 this->numCycles = maxCycles;
236 }
Chris Lattner30587612002-02-04 05:56:30 +0000237
238 if (NC >= 0)
239 for (unsigned c=delta.startCycle, last=c+NC-1; c <= last; c++)
240 this->resourcesByCycle[c].push_back(delta.resourceId);
241 else
242 // Remove the resource from all NC cycles.
Misha Brukmanb10cea82003-08-05 00:02:06 +0000243 for (unsigned c=delta.startCycle, last=(c-NC)-1; c <= last; c++) {
244 // Look for the resource backwards so we remove the last entry
245 // for that resource in each cycle.
246 std::vector<resourceId_t>& rvec = this->resourcesByCycle[c];
247 int r;
248 for (r = rvec.size() - 1; r >= 0; r--)
249 if (rvec[r] == delta.resourceId) {
250 // found last entry for the resource
251 rvec.erase(rvec.begin() + r);
252 break;
253 }
254 assert(r >= 0 && "Resource to remove was unused in cycle c!");
255 }
Chris Lattner30587612002-02-04 05:56:30 +0000256}
Brian Gaeked0fde302003-11-11 22:41:34 +0000257
258} // End llvm namespace