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Scott Michel564427e2007-12-05 01:24:05 +00001//===- SPUSchedule.td - Cell Scheduling Definitions --------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by a team from the Computer Systems Research
6// Department at The Aerospace Corporation.
7//
8// See README.txt for details.
9//
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Even pipeline:
14
15def EVEN_UNIT : FuncUnit; // Even execution unit: (PC & 0x7 == 000)
16def ODD_UNIT : FuncUnit; // Odd execution unit: (PC & 0x7 == 100)
17
18//===----------------------------------------------------------------------===//
19// Instruction Itinerary classes used for Cell SPU
20//===----------------------------------------------------------------------===//
21
22def LoadStore : InstrItinClass; // ODD_UNIT
23def BranchHints : InstrItinClass; // ODD_UNIT
24def BranchResolv : InstrItinClass; // ODD_UNIT
25def ChanOpSPR : InstrItinClass; // ODD_UNIT
26def ShuffleOp : InstrItinClass; // ODD_UNIT
27def SelectOp : InstrItinClass; // ODD_UNIT
28def GatherOp : InstrItinClass; // ODD_UNIT
29def LoadNOP : InstrItinClass; // ODD_UNIT
30def ExecNOP : InstrItinClass; // EVEN_UNIT
31def SPrecFP : InstrItinClass; // EVEN_UNIT
32def DPrecFP : InstrItinClass; // EVEN_UNIT
33def FPInt : InstrItinClass; // EVEN_UNIT (FP<->integer)
34def ByteOp : InstrItinClass; // EVEN_UNIT
35def IntegerOp : InstrItinClass; // EVEN_UNIT
36def IntegerMulDiv: InstrItinClass; // EVEN_UNIT
37def RotateShift : InstrItinClass; // EVEN_UNIT
38def ImmLoad : InstrItinClass; // EVEN_UNIT
39
40/* Note: The itinerary for the Cell SPU is somewhat contrived... */
41def SPUItineraries : ProcessorItineraries<[
42 InstrItinData<LoadStore , [InstrStage<6, [ODD_UNIT]>]>,
43 InstrItinData<BranchHints , [InstrStage<6, [ODD_UNIT]>]>,
44 InstrItinData<BranchResolv, [InstrStage<4, [ODD_UNIT]>]>,
45 InstrItinData<ChanOpSPR , [InstrStage<6, [ODD_UNIT]>]>,
46 InstrItinData<ShuffleOp , [InstrStage<4, [ODD_UNIT]>]>,
47 InstrItinData<SelectOp , [InstrStage<4, [ODD_UNIT]>]>,
48 InstrItinData<GatherOp , [InstrStage<4, [ODD_UNIT]>]>,
49 InstrItinData<LoadNOP , [InstrStage<1, [ODD_UNIT]>]>,
50 InstrItinData<ExecNOP , [InstrStage<1, [EVEN_UNIT]>]>,
51 InstrItinData<SPrecFP , [InstrStage<6, [EVEN_UNIT]>]>,
52 InstrItinData<DPrecFP , [InstrStage<13, [EVEN_UNIT]>]>,
53 InstrItinData<FPInt , [InstrStage<2, [EVEN_UNIT]>]>,
54 InstrItinData<ByteOp , [InstrStage<4, [EVEN_UNIT]>]>,
55 InstrItinData<IntegerOp , [InstrStage<2, [EVEN_UNIT]>]>,
56 InstrItinData<RotateShift , [InstrStage<4, [EVEN_UNIT]>]>,
57 InstrItinData<IntegerMulDiv,[InstrStage<7, [EVEN_UNIT]>]>,
58 InstrItinData<ImmLoad , [InstrStage<2, [EVEN_UNIT]>]>
59 ]>;