blob: e2211106f3f33a17a60636691d34e506f70210ba [file] [log] [blame]
Tom Stellardf98f2ce2012-12-11 21:25:42 +00001//===- AMDIL.td - AMDIL Target Machine -------------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// Target-independent interfaces which we are implementing
10//===----------------------------------------------------------------------===//
11
12include "llvm/Target/Target.td"
13
14// Dummy Instruction itineraries for pseudo instructions
15def ALU_NULL : FuncUnit;
16def NullALU : InstrItinClass;
17
18//===----------------------------------------------------------------------===//
19// AMDIL Subtarget features.
20//===----------------------------------------------------------------------===//
21def FeatureFP64 : SubtargetFeature<"fp64",
22 "CapsOverride[AMDGPUDeviceInfo::DoubleOps]",
23 "true",
24 "Enable 64bit double precision operations">;
25def FeatureByteAddress : SubtargetFeature<"byte_addressable_store",
26 "CapsOverride[AMDGPUDeviceInfo::ByteStores]",
27 "true",
28 "Enable byte addressable stores">;
29def FeatureBarrierDetect : SubtargetFeature<"barrier_detect",
30 "CapsOverride[AMDGPUDeviceInfo::BarrierDetect]",
31 "true",
32 "Enable duplicate barrier detection(HD5XXX or later).">;
33def FeatureImages : SubtargetFeature<"images",
34 "CapsOverride[AMDGPUDeviceInfo::Images]",
35 "true",
36 "Enable image functions">;
37def FeatureMultiUAV : SubtargetFeature<"multi_uav",
38 "CapsOverride[AMDGPUDeviceInfo::MultiUAV]",
39 "true",
40 "Generate multiple UAV code(HD5XXX family or later)">;
41def FeatureMacroDB : SubtargetFeature<"macrodb",
42 "CapsOverride[AMDGPUDeviceInfo::MacroDB]",
43 "true",
44 "Use internal macrodb, instead of macrodb in driver">;
45def FeatureNoAlias : SubtargetFeature<"noalias",
46 "CapsOverride[AMDGPUDeviceInfo::NoAlias]",
47 "true",
48 "assert that all kernel argument pointers are not aliased">;
49def FeatureNoInline : SubtargetFeature<"no-inline",
50 "CapsOverride[AMDGPUDeviceInfo::NoInline]",
51 "true",
52 "specify whether to not inline functions">;
53
54def Feature64BitPtr : SubtargetFeature<"64BitPtr",
55 "Is64bit",
56 "false",
57 "Specify if 64bit addressing should be used.">;
58
59def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
60 "Is32on64bit",
61 "false",
62 "Specify if 64bit sized pointers with 32bit addressing should be used.">;
63def FeatureDebug : SubtargetFeature<"debug",
64 "CapsOverride[AMDGPUDeviceInfo::Debug]",
65 "true",
66 "Debug mode is enabled, so disable hardware accelerated address spaces.">;
67def FeatureDumpCode : SubtargetFeature <"DumpCode",
68 "DumpCode",
69 "true",
70 "Dump MachineInstrs in the CodeEmitter">;
71
72def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
73 "R600ALUInst",
74 "false",
75 "Older version of ALU instructions encoding.">;
76
Vincent Lejeune631591e2013-04-30 00:13:39 +000077def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
78 "HasVertexCache",
79 "true",
80 "Specify use of dedicated vertex cache.">;
Tom Stellardf98f2ce2012-12-11 21:25:42 +000081
82//===----------------------------------------------------------------------===//
83// Register File, Calling Conv, Instruction Descriptions
84//===----------------------------------------------------------------------===//
85
86
87include "AMDILRegisterInfo.td"
88include "AMDILInstrInfo.td"
89