| Bob Wilson | e60fee0 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 1 | ; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t |
| 2 | ; RUN: grep {vqmovn\\.s16} %t | count 1 |
| 3 | ; RUN: grep {vqmovn\\.s32} %t | count 1 |
| 4 | ; RUN: grep {vqmovn\\.s64} %t | count 1 |
| 5 | ; RUN: grep {vqmovn\\.u16} %t | count 1 |
| 6 | ; RUN: grep {vqmovn\\.u32} %t | count 1 |
| 7 | ; RUN: grep {vqmovn\\.u64} %t | count 1 |
| 8 | ; RUN: grep {vqmovun\\.s16} %t | count 1 |
| 9 | ; RUN: grep {vqmovun\\.s32} %t | count 1 |
| 10 | ; RUN: grep {vqmovun\\.s64} %t | count 1 |
| 11 | |
| 12 | define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind { |
| 13 | %tmp1 = load <8 x i16>* %A |
| 14 | %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1) |
| 15 | ret <8 x i8> %tmp2 |
| 16 | } |
| 17 | |
| 18 | define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind { |
| 19 | %tmp1 = load <4 x i32>* %A |
| 20 | %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1) |
| 21 | ret <4 x i16> %tmp2 |
| 22 | } |
| 23 | |
| 24 | define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind { |
| 25 | %tmp1 = load <2 x i64>* %A |
| 26 | %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1) |
| 27 | ret <2 x i32> %tmp2 |
| 28 | } |
| 29 | |
| 30 | define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind { |
| 31 | %tmp1 = load <8 x i16>* %A |
| 32 | %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1) |
| 33 | ret <8 x i8> %tmp2 |
| 34 | } |
| 35 | |
| 36 | define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind { |
| 37 | %tmp1 = load <4 x i32>* %A |
| 38 | %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1) |
| 39 | ret <4 x i16> %tmp2 |
| 40 | } |
| 41 | |
| 42 | define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind { |
| 43 | %tmp1 = load <2 x i64>* %A |
| 44 | %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1) |
| 45 | ret <2 x i32> %tmp2 |
| 46 | } |
| 47 | |
| 48 | define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind { |
| 49 | %tmp1 = load <8 x i16>* %A |
| 50 | %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1) |
| 51 | ret <8 x i8> %tmp2 |
| 52 | } |
| 53 | |
| 54 | define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind { |
| 55 | %tmp1 = load <4 x i32>* %A |
| 56 | %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1) |
| 57 | ret <4 x i16> %tmp2 |
| 58 | } |
| 59 | |
| 60 | define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind { |
| 61 | %tmp1 = load <2 x i64>* %A |
| 62 | %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1) |
| 63 | ret <2 x i32> %tmp2 |
| 64 | } |
| 65 | |
| 66 | declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone |
| 67 | declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) nounwind readnone |
| 68 | declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone |
| 69 | |
| 70 | declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone |
| 71 | declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) nounwind readnone |
| 72 | declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone |
| 73 | |
| 74 | declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone |
| 75 | declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone |
| 76 | declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone |