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Tom Stellardf98f2ce2012-12-11 21:25:42 +00001//===-- R600Defines.h - R600 Helper Macros ----------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8/// \file
9//===----------------------------------------------------------------------===//
10
11#ifndef R600DEFINES_H_
12#define R600DEFINES_H_
13
14#include "llvm/MC/MCRegisterInfo.h"
15
16// Operand Flags
17#define MO_FLAG_CLAMP (1 << 0)
18#define MO_FLAG_NEG (1 << 1)
19#define MO_FLAG_ABS (1 << 2)
20#define MO_FLAG_MASK (1 << 3)
21#define MO_FLAG_PUSH (1 << 4)
22#define MO_FLAG_NOT_LAST (1 << 5)
23#define MO_FLAG_LAST (1 << 6)
24#define NUM_MO_FLAGS 7
25
26/// \brief Helper for getting the operand index for the instruction flags
27/// operand.
28#define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
29
30namespace R600_InstFlag {
31 enum TIF {
32 TRANS_ONLY = (1 << 0),
33 TEX = (1 << 1),
34 REDUCTION = (1 << 2),
35 FC = (1 << 3),
36 TRIG = (1 << 4),
37 OP3 = (1 << 5),
38 VECTOR = (1 << 6),
39 //FlagOperand bits 7, 8
40 NATIVE_OPERANDS = (1 << 9),
41 OP1 = (1 << 10),
Vincent Lejeune631591e2013-04-30 00:13:39 +000042 OP2 = (1 << 11),
43 VTX_INST = (1 << 12),
44 TEX_INST = (1 << 13)
Tom Stellardf98f2ce2012-12-11 21:25:42 +000045 };
46}
47
48#define HAS_NATIVE_OPERANDS(Flags) ((Flags) & R600_InstFlag::NATIVE_OPERANDS)
49
50/// \brief Defines for extracting register infomation from register encoding
51#define HW_REG_MASK 0x1ff
52#define HW_CHAN_SHIFT 9
53
Tom Stellardc0b0c672013-02-06 17:32:29 +000054#define GET_REG_CHAN(reg) ((reg) >> HW_CHAN_SHIFT)
55#define GET_REG_INDEX(reg) ((reg) & HW_REG_MASK)
56
Tom Stellard32c76102013-05-06 17:50:57 +000057#define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
58#define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
59
Tom Stellard5e48a0e2013-06-25 21:22:18 +000060namespace OpName {
Tom Stellard9f7818d2013-01-23 02:09:06 +000061
Vincent Lejeune4ed99172013-05-17 16:50:32 +000062 enum VecOps {
63 UPDATE_EXEC_MASK_X,
64 UPDATE_PREDICATE_X,
65 WRITE_X,
66 OMOD_X,
67 DST_REL_X,
68 CLAMP_X,
69 SRC0_X,
70 SRC0_NEG_X,
71 SRC0_REL_X,
72 SRC0_ABS_X,
73 SRC0_SEL_X,
74 SRC1_X,
75 SRC1_NEG_X,
76 SRC1_REL_X,
77 SRC1_ABS_X,
78 SRC1_SEL_X,
79 PRED_SEL_X,
80 UPDATE_EXEC_MASK_Y,
81 UPDATE_PREDICATE_Y,
82 WRITE_Y,
83 OMOD_Y,
84 DST_REL_Y,
85 CLAMP_Y,
86 SRC0_Y,
87 SRC0_NEG_Y,
88 SRC0_REL_Y,
89 SRC0_ABS_Y,
90 SRC0_SEL_Y,
91 SRC1_Y,
92 SRC1_NEG_Y,
93 SRC1_REL_Y,
94 SRC1_ABS_Y,
95 SRC1_SEL_Y,
96 PRED_SEL_Y,
97 UPDATE_EXEC_MASK_Z,
98 UPDATE_PREDICATE_Z,
99 WRITE_Z,
100 OMOD_Z,
101 DST_REL_Z,
102 CLAMP_Z,
103 SRC0_Z,
104 SRC0_NEG_Z,
105 SRC0_REL_Z,
106 SRC0_ABS_Z,
107 SRC0_SEL_Z,
108 SRC1_Z,
109 SRC1_NEG_Z,
110 SRC1_REL_Z,
111 SRC1_ABS_Z,
112 SRC1_SEL_Z,
113 PRED_SEL_Z,
114 UPDATE_EXEC_MASK_W,
115 UPDATE_PREDICATE_W,
116 WRITE_W,
117 OMOD_W,
118 DST_REL_W,
119 CLAMP_W,
120 SRC0_W,
121 SRC0_NEG_W,
122 SRC0_REL_W,
123 SRC0_ABS_W,
124 SRC0_SEL_W,
125 SRC1_W,
126 SRC1_NEG_W,
127 SRC1_REL_W,
128 SRC1_ABS_W,
129 SRC1_SEL_W,
130 PRED_SEL_W,
131 IMM_0,
132 IMM_1,
133 VEC_COUNT
134 };
135
Tom Stellardf98f2ce2012-12-11 21:25:42 +0000136}
137
Tom Stellardf07b5372013-05-06 17:50:51 +0000138//===----------------------------------------------------------------------===//
139// Config register definitions
140//===----------------------------------------------------------------------===//
141
142#define R_02880C_DB_SHADER_CONTROL 0x02880C
143#define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6)
144
145// These fields are the same for all shader types and families.
146#define S_NUM_GPRS(x) (((x) & 0xFF) << 0)
147#define S_STACK_SIZE(x) (((x) & 0xFF) << 8)
148//===----------------------------------------------------------------------===//
149// R600, R700 Registers
150//===----------------------------------------------------------------------===//
151
152#define R_028850_SQ_PGM_RESOURCES_PS 0x028850
153#define R_028868_SQ_PGM_RESOURCES_VS 0x028868
154
155//===----------------------------------------------------------------------===//
156// Evergreen, Northern Islands Registers
157//===----------------------------------------------------------------------===//
158
159#define R_028844_SQ_PGM_RESOURCES_PS 0x028844
160#define R_028860_SQ_PGM_RESOURCES_VS 0x028860
161#define R_028878_SQ_PGM_RESOURCES_GS 0x028878
162#define R_0288D4_SQ_PGM_RESOURCES_LS 0x0288d4
163
Tom Stellardf98f2ce2012-12-11 21:25:42 +0000164#endif // R600DEFINES_H_