blob: 707f0510b91862f7469d0eb7fc098041fe8d4c80 [file] [log] [blame]
Owen Anderson654d5442010-09-28 21:57:50 +00001; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a9 | FileCheck %s
Evan Cheng3ef1c872010-09-10 01:29:16 +00002; rdar://8402126
3; Make sure if-converter is not predicating vldmia and ldmia. These are
4; micro-coded and would have long issue latency even if predicated on
5; false predicate.
6
7%0 = type { float, float, float, float }
8%pln = type { %vec, float }
9%vec = type { [4 x float] }
10
11define arm_aapcs_vfpcc float @aaa(%vec* nocapture %ustart, %vec* nocapture %udir, %vec* nocapture %vstart, %vec* nocapture %vdir, %vec* %upoint, %vec* %vpoint) {
12; CHECK: aaa:
13; CHECK: vldr.32
14; CHECK-NOT: vldrne
Jim Grosbache6be85e2010-09-17 22:36:38 +000015; CHECK-NOT: vpopne
16; CHECK-NOT: popne
17; CHECK: vpop
18; CHECK: pop
Evan Cheng3ef1c872010-09-10 01:29:16 +000019entry:
20 br i1 undef, label %bb81, label %bb48
21
22bb48: ; preds = %entry
23 %0 = call arm_aapcs_vfpcc %0 @bbb(%pln* undef, %vec* %vstart, %vec* undef) nounwind ; <%0> [#uses=0]
24 ret float 0.000000e+00
25
26bb81: ; preds = %entry
27 ret float 0.000000e+00
28}
29
30declare arm_aapcs_vfpcc %0 @bbb(%pln* nocapture, %vec* nocapture, %vec* nocapture) nounwind