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Anton Korobeynikov4403b932009-07-16 13:27:25 +00001//===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SystemZTargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "systemz-lower"
15
16#include "SystemZISelLowering.h"
17#include "SystemZ.h"
18#include "SystemZTargetMachine.h"
19#include "SystemZSubtarget.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/CallingConv.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/GlobalAlias.h"
26#include "llvm/CodeGen/CallingConvLower.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/ADT/VectorExtras.h"
36using namespace llvm;
37
38SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
39 TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
40
Anton Korobeynikov656ac6f2009-07-16 13:51:53 +000041 RegInfo = TM.getRegisterInfo();
42
Anton Korobeynikov4403b932009-07-16 13:27:25 +000043 // Set up the register classes.
Anton Korobeynikova51752c2009-07-16 13:42:31 +000044 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
Anton Korobeynikov4403b932009-07-16 13:27:25 +000045 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
46
47 // Compute derived properties from the register classes
48 computeRegisterProperties();
49
Anton Korobeynikov9e4816e2009-07-16 13:43:18 +000050 // Set shifts properties
51 setShiftAmountFlavor(Extend);
52 setShiftAmountType(MVT::i32);
53
Anton Korobeynikov4403b932009-07-16 13:27:25 +000054 // Provide all sorts of operation actions
55
Anton Korobeynikove0167c12009-07-16 13:35:30 +000056 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
Anton Korobeynikov4403b932009-07-16 13:27:25 +000057 setSchedulingPreference(SchedulingForLatency);
Anton Korobeynikov87a24e32009-07-16 13:28:59 +000058
59 setOperationAction(ISD::RET, MVT::Other, Custom);
Anton Korobeynikov4403b932009-07-16 13:27:25 +000060}
61
62SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
63 switch (Op.getOpcode()) {
Anton Korobeynikov87a24e32009-07-16 13:28:59 +000064 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
65 case ISD::RET: return LowerRET(Op, DAG);
Anton Korobeynikovba249e42009-07-16 13:50:21 +000066 case ISD::CALL: return LowerCALL(Op, DAG);
Anton Korobeynikov4403b932009-07-16 13:27:25 +000067 default:
68 assert(0 && "unimplemented operand");
69 return SDValue();
70 }
71}
72
73//===----------------------------------------------------------------------===//
74// Calling Convention Implementation
75//===----------------------------------------------------------------------===//
76
77#include "SystemZGenCallingConv.inc"
78
Anton Korobeynikov87a24e32009-07-16 13:28:59 +000079SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
80 SelectionDAG &DAG) {
81 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
82 switch (CC) {
83 default:
84 assert(0 && "Unsupported calling convention");
85 case CallingConv::C:
86 case CallingConv::Fast:
87 return LowerCCCArguments(Op, DAG);
88 }
89}
90
Anton Korobeynikovba249e42009-07-16 13:50:21 +000091SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
92 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
93 unsigned CallingConv = TheCall->getCallingConv();
94 switch (CallingConv) {
95 default:
96 assert(0 && "Unsupported calling convention");
97 case CallingConv::Fast:
98 case CallingConv::C:
99 return LowerCCCCallTo(Op, DAG, CallingConv);
100 }
101}
102
Anton Korobeynikov87a24e32009-07-16 13:28:59 +0000103/// LowerCCCArguments - transform physical registers into virtual registers and
104/// generate load operations for arguments places on the stack.
105// FIXME: struct return stuff
106// FIXME: varargs
107SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
108 SelectionDAG &DAG) {
109 MachineFunction &MF = DAG.getMachineFunction();
110 MachineFrameInfo *MFI = MF.getFrameInfo();
111 MachineRegisterInfo &RegInfo = MF.getRegInfo();
112 SDValue Root = Op.getOperand(0);
113 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
114 unsigned CC = MF.getFunction()->getCallingConv();
115 DebugLoc dl = Op.getDebugLoc();
116
117 // Assign locations to all of the incoming arguments.
118 SmallVector<CCValAssign, 16> ArgLocs;
119 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
120 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
121
122 assert(!isVarArg && "Varargs not supported yet");
123
124 SmallVector<SDValue, 16> ArgValues;
125 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
126 CCValAssign &VA = ArgLocs[i];
127 if (VA.isRegLoc()) {
128 // Arguments passed in registers
129 MVT RegVT = VA.getLocVT();
130 switch (RegVT.getSimpleVT()) {
131 default:
132 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
133 << RegVT.getSimpleVT()
134 << "\n";
135 abort();
136 case MVT::i64:
137 unsigned VReg =
138 RegInfo.createVirtualRegister(SystemZ::GR64RegisterClass);
139 RegInfo.addLiveIn(VA.getLocReg(), VReg);
140 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
141
142 // If this is an 8/16/32-bit value, it is really passed promoted to 64
143 // bits. Insert an assert[sz]ext to capture this, then truncate to the
144 // right size.
145 if (VA.getLocInfo() == CCValAssign::SExt)
146 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
147 DAG.getValueType(VA.getValVT()));
148 else if (VA.getLocInfo() == CCValAssign::ZExt)
149 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
150 DAG.getValueType(VA.getValVT()));
151
152 if (VA.getLocInfo() != CCValAssign::Full)
153 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
154
155 ArgValues.push_back(ArgValue);
156 }
157 } else {
158 // Sanity check
159 assert(VA.isMemLoc());
160 // Load the argument to a virtual register
161 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
162 if (ObjSize > 8) {
163 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
164 << VA.getLocVT().getSimpleVT()
165 << "\n";
166 }
167 // Create the frame index object for this incoming parameter...
168 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
169
170 // Create the SelectionDAG nodes corresponding to a load
171 //from this parameter
172 SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
173 ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
174 PseudoSourceValue::getFixedStack(FI), 0));
175 }
176 }
177
178 ArgValues.push_back(Root);
179
180 // Return the new list of results.
181 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
182 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
183}
184
Anton Korobeynikovba249e42009-07-16 13:50:21 +0000185/// LowerCCCCallTo - functions arguments are copied from virtual regs to
186/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
187/// TODO: sret.
188SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
189 unsigned CC) {
190 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
191 SDValue Chain = TheCall->getChain();
192 SDValue Callee = TheCall->getCallee();
193 bool isVarArg = TheCall->isVarArg();
194 DebugLoc dl = Op.getDebugLoc();
Anton Korobeynikov656ac6f2009-07-16 13:51:53 +0000195 MachineFunction &MF = DAG.getMachineFunction();
Anton Korobeynikovba249e42009-07-16 13:50:21 +0000196
197 // Analyze operands of the call, assigning locations to each operand.
198 SmallVector<CCValAssign, 16> ArgLocs;
199 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
200
201 CCInfo.AnalyzeCallOperands(TheCall, CC_SystemZ);
202
203 // Get a count of how many bytes are to be pushed on the stack.
204 unsigned NumBytes = CCInfo.getNextStackOffset();
205
206 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
207 getPointerTy(), true));
208
209 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
210 SmallVector<SDValue, 12> MemOpChains;
211 SDValue StackPtr;
212
213 // Walk the register/memloc assignments, inserting copies/loads.
214 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
215 CCValAssign &VA = ArgLocs[i];
216
217 // Arguments start after the 5 first operands of ISD::CALL
218 SDValue Arg = TheCall->getArg(i);
219
220 // Promote the value if needed.
221 switch (VA.getLocInfo()) {
222 default: assert(0 && "Unknown loc info!");
223 case CCValAssign::Full: break;
224 case CCValAssign::SExt:
225 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
226 break;
227 case CCValAssign::ZExt:
228 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
229 break;
230 case CCValAssign::AExt:
231 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
232 break;
233 }
234
235 // Arguments that can be passed on register must be kept at RegsToPass
236 // vector
237 if (VA.isRegLoc()) {
238 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
239 } else {
240 assert(VA.isMemLoc());
241
242 if (StackPtr.getNode() == 0)
Anton Korobeynikov656ac6f2009-07-16 13:51:53 +0000243 StackPtr =
244 DAG.getCopyFromReg(Chain, dl,
245 (RegInfo->hasFP(MF) ?
246 SystemZ::R11D : SystemZ::R15D),
247 getPointerTy());
Anton Korobeynikovba249e42009-07-16 13:50:21 +0000248
Anton Korobeynikov656ac6f2009-07-16 13:51:53 +0000249 SDValue PtrOff =
250 DAG.getNode(ISD::ADD, dl, getPointerTy(),
251 StackPtr,
252 DAG.getIntPtrConstant(160+VA.getLocMemOffset()));
Anton Korobeynikovba249e42009-07-16 13:50:21 +0000253
254 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
255 PseudoSourceValue::getStack(),
256 VA.getLocMemOffset()));
257 }
258 }
259
260 // Transform all store nodes into one single node because all store nodes are
261 // independent of each other.
262 if (!MemOpChains.empty())
263 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
264 &MemOpChains[0], MemOpChains.size());
265
266 // Build a sequence of copy-to-reg nodes chained together with token chain and
267 // flag operands which copy the outgoing args into registers. The InFlag in
268 // necessary since all emited instructions must be stuck together.
269 SDValue InFlag;
270 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
271 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
272 RegsToPass[i].second, InFlag);
273 InFlag = Chain.getValue(1);
274 }
275
276 // If the callee is a GlobalAddress node (quite common, every direct call is)
277 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
278 // Likewise ExternalSymbol -> TargetExternalSymbol.
279 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
280 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
281 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
282 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
283
284 // Returns a chain & a flag for retval copy to use.
285 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
286 SmallVector<SDValue, 8> Ops;
287 Ops.push_back(Chain);
288 Ops.push_back(Callee);
289
290 // Add argument registers to the end of the list so that they are
291 // known live into the call.
292 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
293 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
294 RegsToPass[i].second.getValueType()));
295
296 if (InFlag.getNode())
297 Ops.push_back(InFlag);
298
299 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
300 InFlag = Chain.getValue(1);
301
302 // Create the CALLSEQ_END node.
303 Chain = DAG.getCALLSEQ_END(Chain,
304 DAG.getConstant(NumBytes, getPointerTy(), true),
305 DAG.getConstant(0, getPointerTy(), true),
306 InFlag);
307 InFlag = Chain.getValue(1);
308
309 // Handle result values, copying them out of physregs into vregs that we
310 // return.
311 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
312 Op.getResNo());
313}
314
315/// LowerCallResult - Lower the result values of an ISD::CALL into the
316/// appropriate copies out of appropriate physical registers. This assumes that
317/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
318/// being lowered. Returns a SDNode with the same number of values as the
319/// ISD::CALL.
320SDNode*
321SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
322 CallSDNode *TheCall,
323 unsigned CallingConv,
324 SelectionDAG &DAG) {
325 bool isVarArg = TheCall->isVarArg();
326 DebugLoc dl = TheCall->getDebugLoc();
327
328 // Assign locations to each value returned by this call.
329 SmallVector<CCValAssign, 16> RVLocs;
330 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
331
332 CCInfo.AnalyzeCallResult(TheCall, RetCC_SystemZ);
333 SmallVector<SDValue, 8> ResultVals;
334
335 // Copy all of the result registers out of their specified physreg.
336 for (unsigned i = 0; i != RVLocs.size(); ++i) {
337 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
338 RVLocs[i].getValVT(), InFlag).getValue(1);
339 InFlag = Chain.getValue(2);
340 ResultVals.push_back(Chain.getValue(0));
341 }
342
343 ResultVals.push_back(Chain);
344
345 // Merge everything together with a MERGE_VALUES node.
346 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
347 &ResultVals[0], ResultVals.size()).getNode();
348}
349
350
Anton Korobeynikov87a24e32009-07-16 13:28:59 +0000351SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
352 // CCValAssign - represent the assignment of the return value to a location
353 SmallVector<CCValAssign, 16> RVLocs;
354 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
355 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
356 DebugLoc dl = Op.getDebugLoc();
357
358 // CCState - Info about the registers and stack slot.
359 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
360
361 // Analize return values of ISD::RET
362 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ);
363
364 // If this is the first return lowered for this function, add the regs to the
365 // liveout set for the function.
366 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
367 for (unsigned i = 0; i != RVLocs.size(); ++i)
368 if (RVLocs[i].isRegLoc())
369 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
370 }
371
372 // The chain is always operand #0
373 SDValue Chain = Op.getOperand(0);
374 SDValue Flag;
375
376 // Copy the result values into the output registers.
377 for (unsigned i = 0; i != RVLocs.size(); ++i) {
378 CCValAssign &VA = RVLocs[i];
Anton Korobeynikova51752c2009-07-16 13:42:31 +0000379 SDValue ResValue = Op.getOperand(i*2+1);
Anton Korobeynikov87a24e32009-07-16 13:28:59 +0000380 assert(VA.isRegLoc() && "Can only return in registers!");
381
Anton Korobeynikova51752c2009-07-16 13:42:31 +0000382 // If this is an 8/16/32-bit value, it is really should be passed promoted
383 // to 64 bits.
384 if (VA.getLocInfo() == CCValAssign::SExt)
385 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
386 else if (VA.getLocInfo() == CCValAssign::ZExt)
387 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
388 else if (VA.getLocInfo() == CCValAssign::AExt)
389 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
390
Anton Korobeynikov87a24e32009-07-16 13:28:59 +0000391 // ISD::RET => ret chain, (regnum1,val1), ...
392 // So i*2+1 index only the regnums
Anton Korobeynikova51752c2009-07-16 13:42:31 +0000393 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
Anton Korobeynikov87a24e32009-07-16 13:28:59 +0000394
395 // Guarantee that all emitted copies are stuck together,
396 // avoiding something bad.
397 Flag = Chain.getValue(1);
398 }
399
400 if (Flag.getNode())
401 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
402
403 // Return Void
404 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
405}
406
Anton Korobeynikov4403b932009-07-16 13:27:25 +0000407const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
408 switch (Opcode) {
Anton Korobeynikov87a24e32009-07-16 13:28:59 +0000409 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
Anton Korobeynikovba249e42009-07-16 13:50:21 +0000410 case SystemZISD::CALL: return "SystemZISD::CALL";
Anton Korobeynikov4403b932009-07-16 13:27:25 +0000411 default: return NULL;
412 }
413}
414