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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 67d5755d69f159e58f1a80bf625feaacfa6ae8bc / . / lib / Target / CellSPU / CellSDKIntrinsics.td
blob: bd1794c11ea3cd806d07cef7c11d502002128b23 [file] [log] [blame]
Scott Michel67d57552007-12-05 01:31:18 +0000[diff] [blame^]1//===-- CellSDKIntrinsics.td - Cell SDK Intrinsics ---------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by a team from the Computer Systems Research
6// Department at The Aerospace Corporation.
7//
8// See README.txt for details.
9//===----------------------------------------------------------------------===//
10
11///--==-- Arithmetic ops intrinsics --==--
12def CellSDKah:
13 RR_Int_v8i16<0b00010011000, "ah", IntegerOp, int_spu_si_ah>;
14def CellSDKahi:
15 RI10_Int_v8i16<0b00010011000, "ahi", IntegerOp, int_spu_si_ahi>;
16def CellSDKa:
17 RR_Int_v4i32<0b00000011000, "a", IntegerOp, int_spu_si_a>;
18def CellSDKai:
19 RI10_Int_v4i32<0b00111000, "ai", IntegerOp, int_spu_si_ai>;
20def CellSDKsfh:
21 RR_Int_v8i16<0b00010010000, "sfh", IntegerOp, int_spu_si_sfh>;
22def CellSDKsfhi:
23 RI10_Int_v8i16<0b10110000, "sfhi", IntegerOp, int_spu_si_sfhi>;
24def CellSDKsf:
25 RR_Int_v4i32<0b00000010000, "sf", IntegerOp, int_spu_si_sf>;
26def CellSDKsfi:
27 RI10_Int_v4i32<0b00110000, "sfi", IntegerOp, int_spu_si_sfi>;
28def CellSDKaddx:
29 RR_Int_v4i32<0b00000010110, "addx", IntegerOp, int_spu_si_addx>;
30def CellSDKcg:
31 RR_Int_v4i32<0b0100001100, "cg", IntegerOp, int_spu_si_cg>;
32def CellSDKcgx:
33 RR_Int_v4i32<0b01000010110, "cgx", IntegerOp, int_spu_si_cgx>;
34def CellSDKsfx:
35 RR_Int_v4i32<0b10000010110, "sfx", IntegerOp, int_spu_si_sfx>;
36def CellSDKbg:
37 RR_Int_v4i32<0b01000010000, "bg", IntegerOp, int_spu_si_bg>;
38def CellSDKbgx:
39 RR_Int_v4i32<0b11000010110, "bgx", IntegerOp, int_spu_si_bgx>;
40
41def CellSDKmpy:
42 RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
43 "mpy $rT, $rA, $rB", IntegerMulDiv,
44 [(set (v4i32 VECREG:$rT), (int_spu_si_mpy (v8i16 VECREG:$rA),
45 (v8i16 VECREG:$rB)))]>;
46
47def CellSDKmpyu:
48 RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
49 "mpyu $rT, $rA, $rB", IntegerMulDiv,
50 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyu (v8i16 VECREG:$rA),
51 (v8i16 VECREG:$rB)))] >;
52
53def CellSDKmpyi:
54 RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
55 "mpyi $rT, $rA, $val", IntegerMulDiv,
56 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyi (v8i16 VECREG:$rA),
57 i16ImmSExt10:$val))]>;
58
59def CellSDKmpyui:
60 RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
61 "mpyui $rT, $rA, $val", IntegerMulDiv,
62 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyui (v8i16 VECREG:$rA),
63 i16ImmSExt10:$val))]>;
64
65def CellSDKmpya:
66 RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
67 "mpya $rT, $rA, $rB, $rC", IntegerMulDiv,
68 [(set (v4i32 VECREG:$rT), (int_spu_si_mpya (v8i16 VECREG:$rA),
69 (v8i16 VECREG:$rB),
70 (v8i16 VECREG:$rC)))]>;
71
72def CellSDKmpyh:
73 RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
74 "mpyh $rT, $rA, $rB", IntegerMulDiv,
75 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyh (v4i32 VECREG:$rA),
76 (v8i16 VECREG:$rB)))]>;
77
78def CellSDKmpys:
79 RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
80 "mpys $rT, $rA, $rB", IntegerMulDiv,
81 [(set (v4i32 VECREG:$rT), (int_spu_si_mpys (v8i16 VECREG:$rA),
82 (v8i16 VECREG:$rB)))]>;
83
84def CellSDKmpyhh:
85 RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
86 "mpyhh $rT, $rA, $rB", IntegerMulDiv,
87 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhh (v8i16 VECREG:$rA),
88 (v8i16 VECREG:$rB)))]>;
89
90def CellSDKmpyhha:
91 RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
92 "mpyhha $rT, $rA, $rB", IntegerMulDiv,
93 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhha (v8i16 VECREG:$rA),
94 (v8i16 VECREG:$rB)))]>;
95
96// Not sure how to match a (set $rT, (add $rT (mpyhh $rA, $rB)))... so leave
97// as an intrinsic for the time being
98def CellSDKmpyhhu:
99 RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
100 "mpyhhu $rT, $rA, $rB", IntegerMulDiv,
101 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhhu (v8i16 VECREG:$rA),
102 (v8i16 VECREG:$rB)))]>;
103
104def CellSDKmpyhhau:
105 RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
106 "mpyhhau $rT, $rA, $rB", IntegerMulDiv,
107 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhhau (v8i16 VECREG:$rA),
108 (v8i16 VECREG:$rB)))]>;
109
110def CellSDKand:
111 RRForm<0b1000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
112 "add\t $rT, $rA, $rB", IntegerOp,
113 [(set (v4i32 VECREG:$rT),
114 (int_spu_si_and (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
115
116def CellSDKandc:
117 RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
118 "addc\t $rT, $rA, $rB", IntegerOp,
119 [(set (v4i32 VECREG:$rT),
120 (int_spu_si_andc (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
121
122def CellSDKandbi:
123 RI10Form<0b01101000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
124 "andbi\t $rT, $rA, $val", BranchResolv,
125 [(set (v16i8 VECREG:$rT),
126 (int_spu_si_andbi (v16i8 VECREG:$rA), immU8:$val))]>;
127
128def CellSDKandhi:
129 RI10Form<0b10101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
130 "andhi\t $rT, $rA, $val", BranchResolv,
131 [(set (v8i16 VECREG:$rT),
132 (int_spu_si_andhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
133
134def CellSDKandi:
135 RI10Form<0b00101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
136 "andi\t $rT, $rA, $val", BranchResolv,
137 [(set (v4i32 VECREG:$rT),
138 (int_spu_si_andi (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
139
140def CellSDKor:
141 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
142 "or\t $rT, $rA, $rB", IntegerOp,
143 [(set (v4i32 VECREG:$rT),
144 (int_spu_si_or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
145
146def CellSDKorc:
147 RRForm<0b10010011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
148 "addc\t $rT, $rA, $rB", IntegerOp,
149 [(set (v4i32 VECREG:$rT),
150 (int_spu_si_orc (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
151
152def CellSDKorbi:
153 RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
154 "orbi\t $rT, $rA, $val", BranchResolv,
155 [(set (v16i8 VECREG:$rT),
156 (int_spu_si_orbi (v16i8 VECREG:$rA), immU8:$val))]>;
157
158def CellSDKorhi:
159 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
160 "orhi\t $rT, $rA, $val", BranchResolv,
161 [(set (v8i16 VECREG:$rT),
162 (int_spu_si_orhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
163
164def CellSDKori:
165 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
166 "ori\t $rT, $rA, $val", BranchResolv,
167 [(set (v4i32 VECREG:$rT),
168 (int_spu_si_ori (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
169
170def CellSDKxor:
171 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
172 "xor\t $rT, $rA, $rB", IntegerOp,
173 [(set (v4i32 VECREG:$rT),
174 (int_spu_si_xor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
175
176def CellSDKxorbi:
177 RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
178 "xorbi\t $rT, $rA, $val", BranchResolv,
179 [(set (v16i8 VECREG:$rT), (int_spu_si_xorbi (v16i8 VECREG:$rA), immU8:$val))]>;
180
181def CellSDKxorhi:
182 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
183 "xorhi\t $rT, $rA, $val", BranchResolv,
184 [(set (v8i16 VECREG:$rT),
185 (int_spu_si_xorhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
186
187def CellSDKxori:
188 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
189 "xori\t $rT, $rA, $val", BranchResolv,
190 [(set (v4i32 VECREG:$rT),
191 (int_spu_si_xori (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
192
193def CellSDKnor:
194 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
195 "nor\t $rT, $rA, $rB", IntegerOp,
196 [(set (v4i32 VECREG:$rT),
197 (int_spu_si_nor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
198
199def CellSDKnand:
200 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
201 "nand\t $rT, $rA, $rB", IntegerOp,
202 [(set (v4i32 VECREG:$rT),
203 (int_spu_si_nand (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
204
205//===----------------------------------------------------------------------===//
206// Shift/rotate intrinsics:
207//===----------------------------------------------------------------------===//
208
209def CellSDKshli:
210 Pat<(int_spu_si_shli (v4i32 VECREG:$rA), uimm7:$val),
211 (SHLIv4i32 VECREG:$rA, uimm7:$val)>;
212
213def CellSDKshlqbi:
214 Pat<(int_spu_si_shlqbi VECREG:$rA, VECREG:$rB),
215 (SHLQBIvec VECREG:$rA, VECREG:$rB)>;
216
217def CellSDKshlqii:
218 Pat<(int_spu_si_shlqbii VECREG:$rA, uimm7:$val),
219 (SHLQBIIvec VECREG:$rA, uimm7:$val)>;
220
221def CellSDKshlqby:
222 Pat<(int_spu_si_shlqby VECREG:$rA, VECREG:$rB),
223 (SHLQBYvec VECREG:$rA, VECREG:$rB)>;
224
225def CellSDKshlqbyi:
226 Pat<(int_spu_si_shlqbyi VECREG:$rA, uimm7:$val),
227 (SHLQBYIvec VECREG:$rA, uimm7:$val)>;
228
229//===----------------------------------------------------------------------===//
230// Branch/compare intrinsics:
231//===----------------------------------------------------------------------===//
232
233def CellSDKceq:
234 RRForm<0b00000011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
235 "ceq\t $rT, $rA, $rB", BranchResolv,
236 [(set (v4i32 VECREG:$rT),
237 (int_spu_si_ceq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
238
239def CellSDKceqi:
240 RI10Form<0b00111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
241 "ceqi\t $rT, $rA, $val", BranchResolv,
242 [(set (v4i32 VECREG:$rT),
243 (int_spu_si_ceqi (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
244
245def CellSDKceqb:
246 RRForm<0b00001011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
247 "ceqb\t $rT, $rA, $rB", BranchResolv,
248 [(set (v16i8 VECREG:$rT),
249 (int_spu_si_ceqb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
250
251def CellSDKceqbi:
252 RI10Form<0b01111110, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
253 "ceqbi\t $rT, $rA, $val", BranchResolv,
254 [(set (v16i8 VECREG:$rT), (int_spu_si_ceqbi (v16i8 VECREG:$rA), immU8:$val))]>;
255
256def CellSDKceqh:
257 RRForm<0b00010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
258 "ceqh\t $rT, $rA, $rB", BranchResolv,
259 [(set (v8i16 VECREG:$rT),
260 (int_spu_si_ceqh (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
261
262def CellSDKceqhi:
263 RI10Form<0b10111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
264 "ceqhi\t $rT, $rA, $val", BranchResolv,
265 [(set (v8i16 VECREG:$rT),
266 (int_spu_si_ceqhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
267def CellSDKcgth:
268 RRForm<0b00010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
269 "cgth\t $rT, $rA, $rB", BranchResolv,
270 [(set (v8i16 VECREG:$rT),
271 (int_spu_si_cgth (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
272
273def CellSDKcgthi:
274 RI10Form<0b10111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
275 "cgthi\t $rT, $rA, $val", BranchResolv,
276 [(set (v8i16 VECREG:$rT),
277 (int_spu_si_cgthi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
278
279def CellSDKcgt:
280 RRForm<0b00000010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
281 "cgt\t $rT, $rA, $rB", BranchResolv,
282 [(set (v4i32 VECREG:$rT),
283 (int_spu_si_cgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
284
285def CellSDKcgti:
286 RI10Form<0b00110010, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
287 "cgti\t $rT, $rA, $val", BranchResolv,
288 [(set (v4i32 VECREG:$rT),
289 (int_spu_si_cgti (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
290
291def CellSDKcgtb:
292 RRForm<0b00001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
293 "cgtb\t $rT, $rA, $rB", BranchResolv,
294 [(set (v16i8 VECREG:$rT),
295 (int_spu_si_cgtb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
296
297def CellSDKcgtbi:
298 RI10Form<0b01110010, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
299 "cgtbi\t $rT, $rA, $val", BranchResolv,
300 [(set (v16i8 VECREG:$rT), (int_spu_si_cgtbi (v16i8 VECREG:$rA), immU8:$val))]>;
301
302def CellSDKclgth:
303 RRForm<0b00010011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
304 "clgth\t $rT, $rA, $rB", BranchResolv,
305 [(set (v8i16 VECREG:$rT),
306 (int_spu_si_clgth (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
307
308def CellSDKclgthi:
309 RI10Form<0b10111010, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
310 "clgthi\t $rT, $rA, $val", BranchResolv,
311 [(set (v8i16 VECREG:$rT),
312 (int_spu_si_clgthi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
313
314def CellSDKclgt:
315 RRForm<0b00000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
316 "clgt\t $rT, $rA, $rB", BranchResolv,
317 [(set (v4i32 VECREG:$rT),
318 (int_spu_si_clgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
319
320def CellSDKclgti:
321 RI10Form<0b00111010, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
322 "clgti\t $rT, $rA, $val", BranchResolv,
323 [(set (v4i32 VECREG:$rT),
324 (int_spu_si_clgti (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
325
326def CellSDKclgtb:
327 RRForm<0b00001011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
328 "clgtb\t $rT, $rA, $rB", BranchResolv,
329 [(set (v16i8 VECREG:$rT),
330 (int_spu_si_clgtb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
331
332def CellSDKclgtbi:
333 RI10Form<0b01111010, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
334 "clgtbi\t $rT, $rA, $val", BranchResolv,
335 [(set (v16i8 VECREG:$rT),
336 (int_spu_si_clgtbi (v16i8 VECREG:$rA), immU8:$val))]>;
337
338//===----------------------------------------------------------------------===//
339// Floating-point intrinsics:
340//===----------------------------------------------------------------------===//
341
342def CellSDKfa:
343 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
344 "fa\t $rT, $rA, $rB", SPrecFP,
345 [(set (v4f32 VECREG:$rT), (int_spu_si_fa (v4f32 VECREG:$rA),
346 (v4f32 VECREG:$rB)))]>;
347
348def CellSDKfs:
349 RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
350 "fs\t $rT, $rA, $rB", SPrecFP,
351 [(set (v4f32 VECREG:$rT), (int_spu_si_fs (v4f32 VECREG:$rA),
352 (v4f32 VECREG:$rB)))]>;
353
354def CellSDKfm:
355 RRForm<0b01100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
356 "fm\t $rT, $rA, $rB", SPrecFP,
357 [(set (v4f32 VECREG:$rT), (int_spu_si_fm (v4f32 VECREG:$rA),
358 (v4f32 VECREG:$rB)))]>;
359
360def CellSDKfceq:
361 RRForm<0b01000011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
362 "fceq\t $rT, $rA, $rB", SPrecFP,
363 [(set (v4f32 VECREG:$rT), (int_spu_si_fceq (v4f32 VECREG:$rA),
364 (v4f32 VECREG:$rB)))]>;
365
366def CellSDKfcgt:
367 RRForm<0b01000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
368 "fcgt\t $rT, $rA, $rB", SPrecFP,
369 [(set (v4f32 VECREG:$rT), (int_spu_si_fcgt (v4f32 VECREG:$rA),
370 (v4f32 VECREG:$rB)))]>;
371
372def CellSDKfcmeq:
373 RRForm<0b01010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
374 "fcmeq\t $rT, $rA, $rB", SPrecFP,
375 [(set (v4f32 VECREG:$rT), (int_spu_si_fcmeq (v4f32 VECREG:$rA),
376 (v4f32 VECREG:$rB)))]>;
377
378def CellSDKfcmgt:
379 RRForm<0b01010011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
380 "fcmgt\t $rT, $rA, $rB", SPrecFP,
381 [(set (v4f32 VECREG:$rT), (int_spu_si_fcmgt (v4f32 VECREG:$rA),
382 (v4f32 VECREG:$rB)))]>;
383
384def CellSDKfma:
385 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
386 "fma\t $rT, $rA, $rB, $rC", SPrecFP,
387 [(set (v4f32 VECREG:$rT), (int_spu_si_fma (v4f32 VECREG:$rA),
388 (v4f32 VECREG:$rB),
389 (v4f32 VECREG:$rC)))]>;
390
391def CellSDKfnms:
392 RRRForm<0b1011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
393 "fnms\t $rT, $rA, $rB, $rC", SPrecFP,
394 [(set (v4f32 VECREG:$rT), (int_spu_si_fnms (v4f32 VECREG:$rA),
395 (v4f32 VECREG:$rB),
396 (v4f32 VECREG:$rC)))]>;
397
398def CellSDKfms:
399 RRRForm<0b1111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
400 "fms\t $rT, $rA, $rB, $rC", SPrecFP,
401 [(set (v4f32 VECREG:$rT), (int_spu_si_fms (v4f32 VECREG:$rA),
402 (v4f32 VECREG:$rB),
403 (v4f32 VECREG:$rC)))]>;
404
405//===----------------------------------------------------------------------===//
406// Double precision floating-point intrinsics:
407//===----------------------------------------------------------------------===//
408
409def CellSDKdfa:
410 RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
411 "dfa\t $rT, $rA, $rB", DPrecFP,
412 [(set (v2f64 VECREG:$rT), (int_spu_si_dfa (v2f64 VECREG:$rA),
413 (v2f64 VECREG:$rB)))]>;
414
415def CellSDKdfs:
416 RRForm<0b10110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
417 "dfs\t $rT, $rA, $rB", DPrecFP,
418 [(set (v2f64 VECREG:$rT), (int_spu_si_dfs (v2f64 VECREG:$rA),
419 (v2f64 VECREG:$rB)))]>;
420
421def CellSDKdfm:
422 RRForm<0b01110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
423 "dfm\t $rT, $rA, $rB", DPrecFP,
424 [(set (v2f64 VECREG:$rT), (int_spu_si_dfm (v2f64 VECREG:$rA),
425 (v2f64 VECREG:$rB)))]>;
426
427def CellSDKdfma:
428 RRForm<0b00111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
429 "dfma\t $rT, $rA, $rB", DPrecFP,
430 [(set (v2f64 VECREG:$rT), (int_spu_si_dfma (v2f64 VECREG:$rA),
431 (v2f64 VECREG:$rB)))]>;
432
433def CellSDKdfnma:
434 RRForm<0b11111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
435 "dfnma\t $rT, $rA, $rB", DPrecFP,
436 [(set (v2f64 VECREG:$rT), (int_spu_si_dfnma (v2f64 VECREG:$rA),
437 (v2f64 VECREG:$rB)))]>;
438
439def CellSDKdfnms:
440 RRForm<0b01111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
441 "dfnms\t $rT, $rA, $rB", DPrecFP,
442 [(set (v2f64 VECREG:$rT), (int_spu_si_dfnms (v2f64 VECREG:$rA),
443 (v2f64 VECREG:$rB)))]>;
444
445def CellSDKdfms:
446 RRForm<0b10111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
447 "dfms\t $rT, $rA, $rB", DPrecFP,
448 [(set (v2f64 VECREG:$rT), (int_spu_si_dfms (v2f64 VECREG:$rA),
449 (v2f64 VECREG:$rB)))]>;