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Chris Lattner72614082002-10-25 22:55:53 +00001//===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===//
2//
Chris Lattner33f53b52002-10-29 20:48:56 +00003// This file contains the X86 implementation of the MachineInstrInfo class.
Chris Lattner72614082002-10-25 22:55:53 +00004//
5//===----------------------------------------------------------------------===//
6
7#ifndef X86INSTRUCTIONINFO_H
8#define X86INSTRUCTIONINFO_H
9
Chris Lattner9bbf4392002-10-29 17:43:19 +000010#include "llvm/Target/MachineInstrInfo.h"
Chris Lattner72614082002-10-25 22:55:53 +000011#include "X86RegisterInfo.h"
12
Chris Lattner9d177402002-10-30 01:09:34 +000013/// X86II - This namespace holds all of the target specific flags that
14/// instruction info tracks.
15///
16namespace X86II {
17 enum {
Chris Lattner6aab9cf2002-11-18 05:37:11 +000018 //===------------------------------------------------------------------===//
19 // Instruction types. These are the standard/most common forms for X86
20 // instructions.
21 //
22
23 /// Other - An instruction gets this form if it doesn't fit any of the
24 /// catagories below.
25 OtherFrm = 0,
26
27 /// Raw - This form is for instructions that don't have any operands, so
28 /// they are just a fixed opcode value, like 'leave'.
29 RawFrm = 1,
30
31 /// AddRegFrm - This form is used for instructions like 'push r32' that have
32 /// their one register operand added to their opcode.
33 AddRegFrm = 2,
34
35 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
36 /// to specify a destination, which in this case is a register.
37 ///
38 MRMDestReg = 3,
39
40 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
41 /// to specify a destination, which in this case is memory.
42 ///
43 MRMDestMem = 4,
44
45 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
46 /// to specify a source, which in this case is a register.
47 ///
48 MRMSrcReg = 5,
49
50 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
51 /// to specify a source, which in this case is memory.
52 ///
53 MRMSrcMem = 6,
54
55 /// TODO: Mod/RM that uses a fixed opcode extension, like /0
56
57
58 //===------------------------------------------------------------------===//
59 // Actual flags...
60
Chris Lattner239dcfd2002-11-18 01:59:28 +000061 /// Void - Set if this instruction produces no value
Chris Lattner6aab9cf2002-11-18 05:37:11 +000062 Void = 1 << 3,
Chris Lattner239dcfd2002-11-18 01:59:28 +000063
64 // TB - TwoByte - Set if this instruction has a two byte opcode, which
65 // starts with a 0x0F byte before the real opcode.
Chris Lattner6aab9cf2002-11-18 05:37:11 +000066 TB = 1 << 4,
Chris Lattner9d177402002-10-30 01:09:34 +000067 };
68}
69
Chris Lattner055c9652002-10-29 21:05:24 +000070class X86InstrInfo : public MachineInstrInfo {
Chris Lattner72614082002-10-25 22:55:53 +000071 const X86RegisterInfo RI;
72public:
Chris Lattner055c9652002-10-29 21:05:24 +000073 X86InstrInfo();
Chris Lattner72614082002-10-25 22:55:53 +000074
Chris Lattner33f53b52002-10-29 20:48:56 +000075 /// getRegisterInfo - MachineInstrInfo is a superset of MRegister info. As
Chris Lattner72614082002-10-25 22:55:53 +000076 /// such, whenever a client has an instance of instruction info, it should
77 /// always be able to get register info as well (through this method).
78 ///
79 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
80
Chris Lattnerdbb61c62002-11-17 22:53:13 +000081 /// print - Print out an x86 instruction in intel syntax
Chris Lattner72614082002-10-25 22:55:53 +000082 ///
Chris Lattner927dd092002-11-17 23:20:37 +000083 virtual void print(const MachineInstr *MI, std::ostream &O,
84 const TargetMachine &TM) const;
Chris Lattner9bbf4392002-10-29 17:43:19 +000085
86
87 //===--------------------------------------------------------------------===//
88 //
89 // These are stubs for pure virtual methods that should be factored out of
90 // MachineInstrInfo. We never call them, we don't want them, but we need
91 // stubs so that we can instatiate our class.
92 //
93 MachineOpCode getNOPOpCode() const { abort(); }
94 void CreateCodeToLoadConst(const TargetMachine& target, Function* F,
95 Value *V, Instruction *I,
96 std::vector<MachineInstr*>& mvec,
97 MachineCodeForInstruction& mcfi) const { abort(); }
98 void CreateCodeToCopyIntToFloat(const TargetMachine& target,
99 Function* F, Value* val, Instruction* dest,
100 std::vector<MachineInstr*>& mvec,
101 MachineCodeForInstruction& mcfi) const {
102 abort();
103 }
104 void CreateCodeToCopyFloatToInt(const TargetMachine& target, Function* F,
105 Value* val, Instruction* dest,
106 std::vector<MachineInstr*>& mvec,
107 MachineCodeForInstruction& mcfi)const {
108 abort();
109 }
110 void CreateCopyInstructionsByType(const TargetMachine& target,
111 Function* F, Value* src,
112 Instruction* dest,
113 std::vector<MachineInstr*>& mvec,
114 MachineCodeForInstruction& mcfi)const {
115 abort();
116 }
117
118 void CreateSignExtensionInstructions(const TargetMachine& target,
119 Function* F, Value* srcVal,
120 Value* destVal, unsigned numLowBits,
121 std::vector<MachineInstr*>& mvec,
122 MachineCodeForInstruction& mcfi) const {
123 abort();
124 }
125
126 void CreateZeroExtensionInstructions(const TargetMachine& target,
127 Function* F, Value* srcVal,
128 Value* destVal, unsigned srcSizeInBits,
129 std::vector<MachineInstr*>& mvec,
130 MachineCodeForInstruction& mcfi) const {
131 abort();
132 }
Chris Lattner72614082002-10-25 22:55:53 +0000133};
134
135
136#endif