| Jim Grosbach | 754578b | 2010-09-15 19:26:06 +0000 | [diff] [blame^] | 1 | //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains small standalone helper functions and enum definitions for |
| 11 | // the ARM target useful for the compiler back-end and the MC libraries. |
| 12 | // As such, it deliberately does not include references to LLVM core |
| 13 | // code gen types, passes, etc.. |
| 14 | // |
| 15 | //===----------------------------------------------------------------------===// |
| 16 | |
| 17 | #ifndef ARMBASEINFO_H |
| 18 | #define ARMBASEINFO_H |
| 19 | |
| 20 | #include "llvm/Support/ErrorHandling.h" |
| 21 | |
| 22 | namespace llvm { |
| 23 | |
| 24 | // Enums corresponding to ARM condition codes |
| 25 | namespace ARMCC { |
| 26 | // The CondCodes constants map directly to the 4-bit encoding of the |
| 27 | // condition field for predicated instructions. |
| 28 | enum CondCodes { // Meaning (integer) Meaning (floating-point) |
| 29 | EQ, // Equal Equal |
| 30 | NE, // Not equal Not equal, or unordered |
| 31 | HS, // Carry set >, ==, or unordered |
| 32 | LO, // Carry clear Less than |
| 33 | MI, // Minus, negative Less than |
| 34 | PL, // Plus, positive or zero >, ==, or unordered |
| 35 | VS, // Overflow Unordered |
| 36 | VC, // No overflow Not unordered |
| 37 | HI, // Unsigned higher Greater than, or unordered |
| 38 | LS, // Unsigned lower or same Less than or equal |
| 39 | GE, // Greater than or equal Greater than or equal |
| 40 | LT, // Less than Less than, or unordered |
| 41 | GT, // Greater than Greater than |
| 42 | LE, // Less than or equal <, ==, or unordered |
| 43 | AL // Always (unconditional) Always (unconditional) |
| 44 | }; |
| 45 | |
| 46 | inline static CondCodes getOppositeCondition(CondCodes CC) { |
| 47 | switch (CC) { |
| 48 | default: llvm_unreachable("Unknown condition code"); |
| 49 | case EQ: return NE; |
| 50 | case NE: return EQ; |
| 51 | case HS: return LO; |
| 52 | case LO: return HS; |
| 53 | case MI: return PL; |
| 54 | case PL: return MI; |
| 55 | case VS: return VC; |
| 56 | case VC: return VS; |
| 57 | case HI: return LS; |
| 58 | case LS: return HI; |
| 59 | case GE: return LT; |
| 60 | case LT: return GE; |
| 61 | case GT: return LE; |
| 62 | case LE: return GT; |
| 63 | } |
| 64 | } |
| 65 | } // namespace ARMCC |
| 66 | |
| 67 | inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { |
| 68 | switch (CC) { |
| 69 | default: llvm_unreachable("Unknown condition code"); |
| 70 | case ARMCC::EQ: return "eq"; |
| 71 | case ARMCC::NE: return "ne"; |
| 72 | case ARMCC::HS: return "hs"; |
| 73 | case ARMCC::LO: return "lo"; |
| 74 | case ARMCC::MI: return "mi"; |
| 75 | case ARMCC::PL: return "pl"; |
| 76 | case ARMCC::VS: return "vs"; |
| 77 | case ARMCC::VC: return "vc"; |
| 78 | case ARMCC::HI: return "hi"; |
| 79 | case ARMCC::LS: return "ls"; |
| 80 | case ARMCC::GE: return "ge"; |
| 81 | case ARMCC::LT: return "lt"; |
| 82 | case ARMCC::GT: return "gt"; |
| 83 | case ARMCC::LE: return "le"; |
| 84 | case ARMCC::AL: return "al"; |
| 85 | } |
| 86 | } |
| 87 | |
| 88 | namespace ARM_MB { |
| 89 | // The Memory Barrier Option constants map directly to the 4-bit encoding of |
| 90 | // the option field for memory barrier operations. |
| 91 | enum MemBOpt { |
| 92 | ST = 14, |
| 93 | ISH = 11, |
| 94 | ISHST = 10, |
| 95 | NSH = 7, |
| 96 | NSHST = 6, |
| 97 | OSH = 3, |
| 98 | OSHST = 2 |
| 99 | }; |
| 100 | |
| 101 | inline static const char *MemBOptToString(unsigned val) { |
| 102 | switch (val) { |
| 103 | default: llvm_unreachable("Unknown memory opetion"); |
| 104 | case ST: return "st"; |
| 105 | case ISH: return "ish"; |
| 106 | case ISHST: return "ishst"; |
| 107 | case NSH: return "nsh"; |
| 108 | case NSHST: return "nshst"; |
| 109 | case OSH: return "osh"; |
| 110 | case OSHST: return "oshst"; |
| 111 | } |
| 112 | } |
| 113 | } // namespace ARM_MB |
| 114 | } // end namespace llvm; |
| 115 | |
| 116 | // Note that the following auto-generated files only defined enum types, and |
| 117 | // so are safe to include here. |
| 118 | |
| 119 | // Defines symbolic names for ARM registers. This defines a mapping from |
| 120 | // register name to register number. |
| 121 | // |
| 122 | #include "ARMGenRegisterNames.inc" |
| 123 | |
| 124 | // Defines symbolic names for the ARM instructions. |
| 125 | // |
| 126 | #include "ARMGenInstrNames.inc" |
| 127 | |
| 128 | #endif |